JP4474982B2 - Solid-state imaging device and signal processing method for solid-state imaging device - Google Patents

Description

The present invention relates to a solid-state imaging device and a signal processing method for the solid-state imaging device, and in particular, has an amplification function for each unit pixel, and outputs a signal output from the unit pixel via a column signal line wired for each pixel column. The present invention relates to a solid-state imaging device configured to output and a signal processing method of the solid-state imaging device.

  As a solid-state imaging device, there is a CMOS image sensor that can be manufactured by a process similar to that of a CMOS integrated circuit. In this CMOS image sensor, an active structure having an amplification function for each pixel can be easily created by a miniaturization technique associated with the CMOS process, and a pixel array unit in which pixels are two-dimensionally arranged in a matrix form The driving circuit and the signal processing circuit can be integrated on the same chip as the pixel array portion. For this reason, in recent years, more research and development has been made on CMOS image sensors.

  A CMOS image sensor converts an analog signal output from a pixel into a digital signal while suppressing fixed pattern noise of the pixel by an analog-to-digital (A / D) conversion circuit that performs parallel processing for each pixel column of the pixel array unit. There is a column ADC (Analog Digital Converter) system for conversion and output (see Non-Patent Document 1, for example).

  FIG. 8 is a circuit diagram showing a circuit configuration from one pixel 101 in a certain column to the A-D conversion circuit 102 in the column in a conventional column ADC type CMOS image sensor.

  In FIG. 8, a pixel 101 has a configuration including a transfer transistor M1, a reset transistor M2, and an amplification transistor M3 in addition to a photodiode PD which is a photoelectric conversion element. The source of the amplification transistor M 3 is connected to the column signal line 103. One end of the column signal line 103 is connected to a constant current source 104 having a current mirror circuit configuration including MOS transistors M4 and M5. The MOS transistor M5 of the constant current source 104 forms a source follower circuit with the amplification transistor M3 of the pixel 101. The A-D conversion circuit 102 has a configuration using two-stage chopper comparators 111 and 112 and a latch circuit 113.

  Next, the circuit operation of the column ADC type CMOS image sensor according to the conventional example having the above configuration will be described with reference to the timing chart of FIG.

  In the pixel signal readout period corresponding to the horizontal blanking period, first, when the reset pulse Vrst rises (becomes “H” level), the reset transistor M2 of the pixel 101 is turned on to reset the floating diffusion FD. As a result, the potential of the floating diffusion FD is output to the column signal line 103 as a reset signal via the amplification transistor M3. At this time, in the A-D conversion circuit 102, the switch S3 for taking in the signal voltage Vx of the column signal line 103 is closed, then the switches S1 and S2 of the comparators 111 and 112 are simultaneously closed, and then the switch S1 is first. Next, the switch S2 is opened.

  Next, when the readout pulse Vtg is raised, the transfer transistor M1 of the pixel 101 is turned on, and the charge obtained by photoelectric conversion by the photodiode PD is transferred to the floating diffusion FD. As a result, the potential of the floating diffusion FD changes according to the transferred charge. Then, this potential is output to the column signal line 103 as a pixel signal through the amplification transistor M3.

  At this time, in the A-D conversion circuit 102, the sampling is performed with the switch S4 closed. When sampling is completed, the switch is opened and a reference signal Vref having a ramp (RAMP) waveform is applied from the switch S4. Then, according to the ramp waveform, the input voltage Vin (the signal voltage Vx of the column signal line 103) of the A-D conversion circuit 102 eventually exceeds the threshold voltage of the comparators 111 and 112, so that the comparator 112 at the second stage. The output of is inverted. The value of the n-bit counter (not shown) at that time becomes a pixel signal. The value of this pixel signal is stored in the latch circuit 113. The A-D conversion is completed by the series of operations described above.

Kazuya Yonemoto, “Basics and Applications of CCD / CMOS Image Sensors” (First Edition), CQ Publisher, published on August 10, 2003, pp.201-203

  In the column ADC type CMOS image sensor according to the conventional example having the above configuration, the pixel signal is directly supplied to the A / D conversion circuit 102 via the source follower circuit formed by the amplification transistor M3 and the MOS transistor M5. Therefore, since the substrate of the amplification transistor M3 is connected to the ground, when the source voltage of the amplification transistor M3 is increased, the source-substrate voltage Vsb is increased, and the threshold voltage Vth of the amplification transistor M3 is increased by the substrate bias effect. To rise.

When the threshold voltage Vth of the amplification transistor M3 rises, the following equation of Vth:
Vth = Vth0 + γ {√ (2Φf + Vsb) −√ (2Φf)}
As the source voltage of the amplification transistor M3 increases, the threshold voltage Vth of the amplification transistor M3 becomes non-linear (curves with √). As a result, when comparing the pixel signal with the reference voltage Vref having a ramp waveform, the pixel signal is compared with a pixel signal having a narrow dynamic range and poor linearity. In the Vth equation, Vth0 is a threshold voltage when no voltage is applied between the source and the substrate of the amplification transistor M3, and γ and Φf are coefficients determined by the process.

  As is apparent from the above description, a source follower circuit is formed by the amplification transistor M3 of the pixel 101 and the MOS transistor M5 of the constant current source 104, and a signal output from the pixel 101 is directly A via the source follower circuit. When the configuration for inputting to the −D conversion circuit 102 is adopted, the threshold voltage Vth of the amplification transistor M3 also varies due to the variation of the output voltage (source voltage) due to the substrate bias effect of the amplification transistor M3. As a result, the A / D conversion circuit Since the input dynamic range of the pixel 102 becomes narrow and the linearity of the pixel signal input to the A / D conversion circuit is deteriorated, an A / D conversion output proportional to the potential of the floating diffusion FD of the pixel 101 cannot be obtained. It will be.

  Here, the signal voltage Vx of the column signal line 103 which is the output of the source follower circuit formed by the amplification transistor M3 of the pixel 101 and the MOS transistor M5 of the constant current source 104 is A-D provided for each column. The conventional problem has been described by taking as an example a column ADC type CMOS image sensor that converts the digital signal by the conversion circuit 102 and outputs it. However, the problem is that the signal voltage Vx of the column signal line 103 is provided directly for each column. This is true for all CMOS image sensors configured to be input to the signal processing circuit.

  Specifically, for example, the signal voltage Vx of the column signal line 103 is directly input to a CDS (Correlated Double Sampling) circuit provided for each column, and the reset output from the pixel in the CDS circuit. Even in the column CDS type CMOS image sensor configured to output the analog signal as it is by performing the process of removing the fixed pattern noise of the pixel by taking the difference between the signal and the pixel signal, due to the substrate bias effect of the amplification transistor M3, The threshold voltage Vth of the amplification transistor M3 also fluctuates due to fluctuations in the output voltage (source voltage). As a result, the input dynamic range of the CDS circuit is narrowed, and the linearity of the pixel signal input to the CDS circuit is deteriorated.

The present invention has been made in view of the above problems, and the object of the present invention is to change the threshold voltage Vth of the amplification transistor due to the fluctuation of the output voltage (source voltage) due to the substrate bias effect of the amplification transistor of the pixel. Provided is a solid-state imaging device and a signal processing method for the solid-state imaging device that can obtain a pixel signal with good linearity without narrowing the dynamic range of a circuit that processes a signal output from a pixel. It is in.

In order to achieve the above object, in the present invention,
The photoelectric conversion element and the photoelectric conversion unit pixel having an amplification transistor that outputs a signal corresponding to the charge obtained by the element is arranged Rutotomoni, a pixel array portion signal line for each column is formed by the wiring,
A signal processing unit having a differential transistor that is provided on the same substrate as the pixel array unit and that forms a differential pair with the amplification transistor by commonly connecting the amplification transistor and the source via the signal line;
In a solid-state imaging device comprising:
When a signal output from the unit pixel to the signal line is derived through the differential transistor, a threshold voltage variation due to a substrate bias effect in the amplification transistor and the differential transistor is calculated by the amplification transistor and the difference. A configuration is adopted in which the differential operation of the dynamic transistors cancels out .

In the solid-state imaging device having the above configuration, the sources of the amplification transistor and the differential transistor of the unit pixel are commonly connected via the signal line, so that the source voltages of the amplification transistor and the differential transistor become the same potential, Since both transistors are integrated on the same substrate, the threshold voltage Vth due to the substrate bias effect in both transistors varies by the same amount. At this time, since the amplifying transistor and the differential transistor form a differential circuit, fluctuations in the threshold voltages Vth of the amplifying transistor and the differential transistor are canceled by the differential operation.

  According to the present invention, since the variation of the threshold voltage Vth due to the substrate bias effect in the amplification transistor of the unit pixel can be canceled by the differential transistor, without reducing the dynamic range of the circuit that processes the signal output from the pixel, In addition, the signal output from the unit pixel can be derived with good linearity.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing a configuration example of a solid-state imaging device according to the first embodiment of the present invention, for example, a column ADC type (column parallel ADC mounted) CMOS image sensor.

  In FIG. 1, a plurality of unit pixels (hereinafter simply referred to as “pixels”) 11 including photoelectric conversion elements constitute a pixel array unit 12 by being arranged two-dimensionally in a matrix form (matrix form). In the pixel array section 12, row control lines 13 (13-1, 13-2,...) Are wired for each row with respect to the matrix array of the pixels 11, and column signal lines 14 (14-1,. 14-2, ...) are wired. One end of each of the row control lines 13-1, 13-2,... Is connected to the output end of each stage of the row scanning circuit 15.

  The pixel 11 has a configuration including three transistors, for example, a transfer transistor 112, a reset transistor 113, and an amplification transistor 114 in addition to a photoelectric conversion element such as a photodiode 111. The source of the amplification transistor 114 is connected to the column signal line 14 (14-1, 14-2,...). The pixel 11 is not limited to a three-transistor configuration having three transistors 112 to 114. For example, the source of the amplification transistor 114 and the column signal line 14 (14-1, 14-2,...) A four-transistor structure in which a selection transistor is connected between the two may be used.

  The row scanning circuit 15 is composed of a shift register or the like, and controls row addresses and row scanning by sequentially outputting row selection pulses to the row control lines 13-1, 13-2,. Thereby, the pixels 11 for one row connected to the row control lines 13 (13-1, 13-2,...) To which the row selection pulse is given are selected. Then, from each pixel 11 in the selected row, a reset signal is output to the column signal lines 14-1, 14-2,... During the reset operation and a pixel signal is output during the read operation (transfer operation).

  A constant current source 16 is connected to one end side of the column signal lines 14-1, 14-2,. The constant current source 16 has an Nch MOS transistor 161 whose gate and drain are connected in common, a source connected to the ground, the MOS transistor 161 and the gate connected in common, and a drain connected to the column signal line 14 (14-1,. 14-2,..., And a current mirror circuit including NchMOS transistors 162 each having a source connected to the ground. The MOS transistor 162 of the constant current source 16 forms a source follower circuit together with the amplification transistor 114 of the pixel 11.

  The column processing unit (column signal processing unit) 10A is provided on one end side of the column signal lines 14-1, 14-2,..., For example, corresponding to each of the column signal lines 14-1, 14-2,. The AD converter circuit 17 (17-1, 17-2,...) Is provided. Further, in common with the A-D conversion circuit 17 (17-1, 17-2,...), A D-A (digital-analog) conversion circuit (DAC: Digital Analog Converter) 18 serving as a reference voltage generation unit. Counter 19 is provided. The DA conversion circuit 18 generates a reference voltage Vref having a ramp (RAMP) waveform in which the level changes in an inclined manner as time passes. The counter 19 measures the comparison time in the comparator 20 described later by performing a counting operation in synchronization with the clock CK having a predetermined period.

  The A-D conversion circuit 17 includes an analog signal supplied from the pixel 11 selected for each row control line 13-1, 13-2,... Via the column signal lines 14-1, 14-2,. The comparator 20 that compares the reference voltage Vref of the ramp waveform generated by the DA converter circuit 18 and the memory device 21 that holds the count result of the counter 19, and the analog signal output from the pixel 11 It is converted into an n-bit digital signal and output.

  The column scanning circuit 22 is configured by a shift register or the like, and sequentially outputs a column selection pulse to each of the A / D conversion circuits 17-1, 17-2,. Controls scanning. As a result, digital signals output from each of the A / D conversion circuits 17-1, 17-2,... Are sequentially selected and supplied to the output circuit 24 via the horizontal output line 23 having a 2n-bit width.

  The output circuit 24 includes 2n sense circuits, a subtraction circuit, an output amplifier, and the like provided corresponding to each of the horizontal output lines 23 having a 2n-bit width. Based on the master clock MCK, the timing control circuit 25 generates a clock signal that serves as a reference for operations of the row scanning circuit 15, the counter 19 and the column scanning circuit 22, and the like, and the row scanning circuit 15, the counter 19 and the column scanning circuit. Give to 22 etc.

  In the column ADC type CMOS image sensor according to the first embodiment having the above-described configuration, peripheral circuits and signal processing circuits that drive and control each pixel 11 of the pixel array unit 12, that is, the row scanning circuit 15 and the A-D conversion circuit 17. (17-1, 17-2,...), The DA conversion circuit 18, the counter 19, the column scanning circuit 22, the output circuit 24, the timing control circuit 25, and the like are on the same chip (substrate) as the pixel array unit 12. Is accumulated.

  FIG. 2 is a circuit diagram illustrating an example of a circuit configuration from one pixel 11 in a certain column to the comparator 20 in the column in the column ADC type CMOS image sensor according to the first embodiment having the above-described configuration.

2, for example, an Nch MOS transistor 201 whose source is connected to a column signal line 14 (14-1, 14-2,...) Is provided at the input stage of the comparator 20. Here, since the AD conversion circuit 17 including the comparator 20 is integrated on the same chip as the pixel array unit 12, the MOS transistor 201 has substantially the same transistor characteristics as the amplification transistor 114 of the pixel 11. It will be. The MOS transistor 201 has a source connected in common via the amplification transistor 114 of the pixel 11 and the column signal line 14 (14-1, 14-2,. Dynamic amplifier). Hereinafter, the MOS transistor 201 is referred to as a differential transistor 201.

  A reference voltage Vref having a ramp waveform generated by the DA conversion circuit 18 is applied to the gate of the differential transistor 201 via the capacitor 202. The drain of the differential transistor 201 is connected to the power supply line L1 of the voltage AVD via the Pch load MOS transistor 203. A DC gate voltage VGp is applied to the gate of the load MOS transistor 203. A capacitor 204 is connected between the gate of the load MOS transistor 203 and the power supply line L1. A Pch MOS switch (transistor) 205 is connected between the gate and drain of the differential transistor 201. An “L” level preset pulse PSET is applied to the gate of the MOS switch 205.

  The gate of the PchMOS transistor 206 is connected to the output terminal of the differential amplifier composed of the amplification transistor 114 and the differential transistor 201 of the pixel 11, that is, the drain of the differential transistor 201. The MOS transistor 206 has a source connected to the power supply line L 1 and a drain connected to the ground via the Nch MOS transistor 207. The MOS transistor 207 operates as a constant current source when a DC gate voltage VGn is applied to the gate. A capacitor 208 is connected between the gate of the MOS transistor 207 and the ground.

  The differential amplifier output derived from the drain of the MOS transistor 206 becomes a comparator output Vco through the buffer 209 and is supplied to the memory device 21 in the next stage. The buffer 209 is connected in series between the power supply line L2 of the voltage VDD and the ground, and is the same as the preceding stage CMOS inverter 212 including the PchMOS transistor 210 and the NchMOS transistor 211 in which the gates and drains are connected in common. Are connected in series between the power supply line L2 of the voltage VDD and the ground, and are composed of a CMOS inverter 215 in the subsequent stage composed of a PchMOS transistor 213 and an NchMOS transistor 214, the gates and drains of which are connected in common. .

  Next, regarding the circuit operation of the CMOS image sensor according to the present embodiment on which the A / D conversion circuit 17 (17-1, 17-2,...) Having the comparator 20 having the above configuration is mounted, FIG. 1 and FIG. The explanation will be based on this.

  First, the operation of the pixel 11 will be described with reference to the timing chart of FIG. In the pixel circuit of FIG. 2, the reset operation is performed by applying the “H” level reset pulse Vrst to the gate of the reset transistor 113, and the “H” level read pulse Vtg is applied to the gate of the transfer transistor 112. As a result, the transfer operation is performed.

  In the pixel signal reading period corresponding to the horizontal blanking period, first, when the reset pulse Vrst is raised, the reset transistor 113 of the pixel 11 is turned on to reset the floating diffusion FD. As a result, the potential of the floating diffusion FD is output to the column signal lines 14 (14-1, 14-2,...) As the reset signal (reset component V) via the amplification transistor 114.

  Next, when the read pulse Vtg is raised, the transfer transistor 112 of the pixel 11 is turned on, and the charge obtained by photoelectric conversion by the photodiode PD is transferred to the floating diffusion FD. As a result, the potential of the floating diffusion FD changes in accordance with the transferred charge amount. This potential is output to the column signal lines 14 (14-1, 14-2,...) As pixel signals (signal components) through the amplification transistor 114.

  Next, the circuit operation of the A / D conversion circuit 17 (17-1, 17-2,...) Will be described with reference to the timing chart of FIG.

  A row is selected by row scanning by the row scanning circuit 15, and after the first read operation from the pixel 11 of the selected row to the column signal lines 14-1, 14-2,. A preset pulse PSET is applied to the gate of the MOS switch 205. As a result, the gate and drain of the differential transistor 201 are short-circuited, and the operating point of the differential transistor 201 is determined. Thereafter, a ramp waveform reference voltage Vref is applied from the DA conversion circuit 18 to the gate of the differential transistor 201 via the capacitor 202.

  Accordingly, in the differential amplifier including the amplification transistor 114 and the differential transistor 201 of the pixel 11, the voltage Vfd of the floating diffusion FD of the pixel 11, that is, the gate voltage Vfd of the amplification transistor 114, and the reference voltage Vref of the ramp waveform, An operation of comparing the gate voltage Vref of the differential transistor 201 is performed. At the same time as the input of the reference voltage Vref from the DA conversion circuit 18, the counter 19 performs a first counting operation.

  In this way, the comparison operation between the gate voltage Vfd of the amplification transistor 114 and the gate voltage Vref of the differential transistor 201 and the count operation of the counter 19 are executed in parallel, and when both the gate voltages Vfd and Vref become equal. In addition, the polarity of the output Vco of the comparator 20 is inverted. Then, the count value N of the counter 19 is taken into the memory device 21 at this inversion timing. As a result, the memory device 21 holds the count value N of the counter 19 corresponding to the comparison period in the comparator 20.

In the first read operation, the reset component ΔV during the reset operation of the pixel 11 is read. This reset component ΔV includes fixed pattern noise that varies for each pixel 11 as an offset. However, since the variation of the reset component ΔV is generally small and the reset level is common to all pixels, the output of an arbitrary column signal line 14-x is approximately known. Therefore, when the reset component ΔV is read for the first time, the comparison period can be shortened by adjusting the reference voltage Vref of the ramp waveform. In this example, the reset component ΔV is compared in a count period (128 clocks) for 7 bits.

In the second read operation, in addition to the reset component ΔV , a signal component corresponding to the amount of incident light for each pixel 11 is read by the same operation as the first read operation. That is, after the second read operation from the pixel 11 of a selected row to the column signal lines 14-1, 14-2,... Is stabilized, the ramp waveform reference voltage Vref is applied to the gate of the differential transistor 201. Thus, in the differential amplifier including the amplification transistor 114 and the differential transistor 201 of the pixel 11, an operation of comparing the gate voltage Vfd of the amplification transistor 114 and the gate voltage Vref of the differential transistor 201 is performed. Simultaneously with the input of the reference voltage Vref, the counter 19 performs a second counting operation.

  Then, the comparison operation between the gate voltage Vfd of the amplification transistor 114 and the gate voltage Vref of the differential transistor 201 and the count operation of the counter 19 are executed in parallel, and the comparison is performed when both the gate voltages Vfd and Vref become equal. The polarity of the output Vco of the counter 20 is inverted, and the count value N of the counter 19 is held in the memory device 21 at this inversion timing. At this time, the first count value (memory value N1) and the second count value (memory value N2) are held in different locations in the memory device 21 as n-bit digital signals after A / D conversion. Is done.

  After the above series of A-D conversion operations, the first and second n-bit digital signals held in the memory device 21 are supplied to 2n horizontal output lines 23 by column scanning by the column scanning circuit 22. Then, it is sequentially supplied to the output circuit 24. The output circuit 24 incorporates a subtraction circuit (not shown), and after the CDS process is performed by the subtraction process (second digital signal) − (first digital signal) in the subtraction circuit, the external circuit Is output. Thereafter, the same operation is sequentially repeated for each row to generate a two-dimensional image.

  As described above, in the first embodiment of the present invention, A− for each column in the matrix arrangement of the pixels 11 having the amplification transistors 114, that is, for each column signal line 14 (14-1, 14-2,...). In the column ADC type CMOS image sensor in which the D conversion circuit 17 (17-1, 17-2,...) Is arranged, the column is connected to the column signal line 14 (14-1, 14-2,...). By connecting the differential transistor 201 that forms a differential pair with the amplification transistor 114 via the signal line 14 and deriving the signal output from the pixel 11 through the differential transistor 201, the following An effect can be obtained.

  That is, the source of the amplification transistor 114 of the pixel 11 and the source of the differential transistor 201 provided in the input stage of the comparator 20 are common via the column signal lines 14 (14-1, 14-2,...). Are connected to each other, the source voltages of the amplification transistor 114 and the differential transistor 201 become the same potential. At this time, since the amplification transistor 114 and the differential transistor 201 have substantially the same transistor characteristics, the threshold voltage Vth due to the substrate bias effect in both transistors 114 and 201 varies by the same amount. Is canceled by the differential operation of the differential transistor 201.

  As a result, when the comparator 20 compares the gate voltage Vfd of the amplification transistor 114 and the gate voltage Vref of the differential transistor 201, the comparison is performed without reducing the dynamic range and with good linearity with respect to the gate voltage Vfd. Therefore, an A / D conversion output proportional to the potential Vfd of the floating diffusion FD of the pixel 11 can be obtained.

  In the first embodiment, as an example, the A-D conversion circuit 17 is applied to a CMOS image sensor having the same number corresponding to each of the column signal lines 14-1, 14-2,. Although described above, the present invention is not limited to this application example. Specifically, a plurality of column signal lines 14-1, 14-2,... Are grouped, one AD conversion circuit 17 is provided for each group, and one group of a plurality of column signals is provided. A CMOS image sensor having a configuration in which a signal of the pixel 11 supplied via a line is selectively A / D converted by a single A / D conversion circuit 17, or the A / D conversion circuit 17 is placed above and below the pixel array unit 12. For example, one signal is arranged on each side, and the signals of the odd-numbered pixels 11 and the signals of the even-numbered pixels 11 are separated by the upper and lower A / D conversion circuits 17 and the column signal lines 14-1 and 14-2. ..,... The same function can be applied to a CMOS image sensor or the like that selectively performs A-D conversion every time.

[Second Embodiment]
FIG. 5 is a block diagram showing a configuration example of a solid-state imaging device according to the second embodiment of the present invention, for example, a column CDS (analog amplification type) CMOS image sensor. In FIG. The same reference numerals are given.

  The CMOS image sensor according to the first embodiment employs a configuration in which the analog signal output from the pixel 11 is converted into a digital signal by the column processing unit 10A and output, whereas the CMOS image according to the present embodiment is used. The sensor is greatly different in that the analog signal output from the pixel 11 is subjected to CDS processing and output in the column processing unit 10B as an analog signal.

  The column processing unit (column signal processing unit) 10B corresponds to one end side of the column signal lines 14-1, 14-2,..., For example, corresponding to each of the column signal lines 14-1, 14-2,. The CDS circuit 30 (30-1, 30-2,...) Is provided. The CDS circuit 30 (30-1, 30-2,...) Performs a process of removing the fixed pattern noise of the pixel 11 by taking the difference between the reset signal output from the pixel 11 and the pixel signal. The analog pixel signal from which noise has been removed by the CDS circuit 30 (30-1, 30-2,...) Is transferred to the analog front end (AFE) unit 31 via the horizontal output line 32, and the AFE unit 31 performs predetermined processing. Is output after the above process is performed.

  Also in the CMOS image sensor according to the present embodiment, the CDS circuit 30 (30-1, 30-2,...) And the analog front end unit 31 are the same chip as the pixel array unit 12, together with other peripheral drive circuits. It will be accumulated on top.

  FIG. 6 is a circuit diagram showing an example of a circuit configuration from one pixel 11 in a certain column to the analog front end unit 31 in the column CDS type CMOS image sensor according to the second embodiment having the above configuration. 2 are denoted by the same reference numerals.

  6, an NchMOS transistor 301 having a source connected to a column signal line 14 (14-1, 14-2,...) Is provided at the input stage of the CDS circuit 30. Here, since the CDS circuit 30 is integrated on the same chip as the pixel array unit 12, the MOS transistor 301 has substantially the same transistor characteristics as the amplification transistor 114 of the pixel 11. The MOS transistor 301 has a source connected in common via the amplification transistor 114 of the pixel 11 and the column signal line column signal line 14 (14-1, 14-2,. An amplifier (differential circuit) is formed. Hereinafter, the MOS transistor 301 is referred to as a differential transistor 301.

  The drain of the differential transistor 301 is connected to the power supply line L 1 of the voltage AVD via the Pch load MOS transistor 302. A DC gate voltage VGp is applied to the gate of the load MOS transistor 302. A capacitor 303 is connected between the gate of the load MOS transistor 302 and the power supply line L1. The gate of the Pch MOS transistor 304 is connected to the output terminal of the differential amplifier composed of the amplification transistor 114 and the differential transistor 301 of the pixel 11, that is, the drain of the differential transistor 301. The MOS transistor 304 has a source connected to the power supply line L 1 and a drain connected to the ground via the Nch MOS transistor 305. The MOS transistor 305 operates as a constant current source when a DC gate voltage VGn is applied to the gate. A capacitor 306 is connected between the gate of the MOS transistor 305 and the ground.

  The differential amplifier output Vo derived from the drain of the MOS transistor 304 becomes the gate input of the differential transistor 301 and is given to the CDS unit 307. The CDS unit 307 includes a clamp capacitor C11, a clamp switch S11, a hold capacitor C12, and a sampling switch S12. The pixel signal subjected to CDS processing by the CDS unit 307, that is, the pixel signal output from the CDS circuit 30, is selectively supplied to the analog front end unit 31 via the horizontal selection switch S13.

  The analog front end unit 31 has an operational amplifier OP having a pixel signal from the CDS circuit 30 as an inverting (−) input and a reference voltage Vr as a non-inverting (+) input, and between the inverting input terminal and the output terminal of the operational amplifier OP. Are connected by a feedback capacitor C13 and a switch S14, a sampling switch S15, a hold capacitor C14, a source follower MOS transistor Tr, and a load resistor R.

  Next, regarding the circuit operation of the CMOS image sensor according to the present embodiment on which the CDS circuit 30 (30-1, 30-2,...) Having the above configuration is mounted, the timing chart of FIG. 7 based on FIG. 5 and FIG. Will be described. Note that the operation of the pixel 11 is the same as that in the first embodiment, and therefore the description thereof is omitted here.

  In the pixel signal readout period corresponding to the horizontal blanking period, first, the switches S11, S12, and S14 are closed in the P phase (preset phase) in which the reset signal of the pixel 11 is output. Next, the pixel signal is sampled by opening only the switch S11 while keeping the switches S12 and S14 closed in the D phase (data phase) where the pixel signal of the pixel 11 is output. As a result, the CDS unit 307 performs CDS processing for removing the fixed pattern noise of the pixel 11 by subtracting the reset signal from the pixel signal including the reset signal.

  After the CDS process is completed, the column capacity reading period starts. In this column capacity reading period, when the switch S14 is opened and the horizontal selection switch S13 is closed and then the switch S15 is closed, the pixel signal subjected to the CDS processing in the CDS unit 307 is read, and the analog pixel signal It is output to the outside as it is.

  As described above, in the second embodiment of the present invention, the CDS circuit is provided for each column in the matrix arrangement of the pixels 11 having the amplification transistors 114, that is, for each column signal line 14 (14-1, 14-2,...). In the column CDS type CMOS image sensor in which 30 (30-1, 30-2,...) Are arranged, the column signal line 14 is connected to the column signal line 14 (14-1, 14-2,...). A differential transistor 301 that forms a differential pair together with the amplification transistor 114 is connected via a transistor to have a configuration similar to a voltage forward amplifier, and a signal output from the pixel 11 is derived through the differential transistor 301. Thus, the following operational effects can be obtained.

  That is, the source of the amplifying transistor 114 of the pixel 11 and the source of the differential transistor 301 provided at the input stage of the CDS circuit 30 are common via the column signal lines 14 (14-1, 14-2,...). As a result, the source voltages of the amplification transistor 114 and the differential transistor 301 become the same potential. At this time, since the amplification transistor 114 and the differential transistor 301 have substantially the same transistor characteristics, the threshold voltage Vth due to the substrate bias effect in both transistors 114 and 301 varies by the same amount. Is canceled by the differential operation of the differential transistor 301. Therefore, the signal output from the pixel 11 can be supplied to the CDS circuit 30 that does not deteriorate linearity unlike the source follower and does not narrow the dynamic range.

  In the first and second embodiments, the case where the pixel 11 is applied to an area sensor in which the pixels 11 are two-dimensionally arranged in a matrix has been described as an example. However, the present invention is limited to application to the area sensor. For example, the present invention can be similarly applied to a linear sensor (line sensor) in which the pixels 11 are linearly arranged one-dimensionally.

  In the second embodiment, the case where the CDS circuit 30 is applied to a CMOS image sensor having the same number corresponding to each of the column signal lines 14-1, 14-2,. However, the present invention is not limited to this application example. Specifically, a plurality of column signal lines 14-1, 14-2,... Are grouped, one CDS circuit 30 is provided for each group, and one group of a plurality of column signal lines is routed. The CMOS image sensor configured to selectively perform CDS processing of the signals of the pixels 11 supplied by the single CDS circuit 30 and the CDS circuits 30 are disposed, for example, one on each of the upper and lower sides of the pixel array unit 12, and odd-numbered rows CMOS image having a configuration in which the signals of the pixels 11 and the signals of the pixels 11 in the even rows are selectively subjected to CDS processing separately by the upper and lower CDS circuits 30 and for each of the column signal lines 14-1, 14-2,. The same applies to sensors and the like.

1 is a block diagram showing a configuration example of a column ADC type (column parallel ADC mounted) CMOS image sensor according to a first embodiment of the present invention. FIG. FIG. 3 is a circuit diagram illustrating an example of a circuit configuration from one pixel in a column to a comparator in the column in the column ADC type CMOS image sensor according to the first embodiment. 6 is a timing chart for explaining circuit operations of a unit pixel. 6 is a timing chart for explaining the circuit operation of the A-D conversion circuit according to the first embodiment. It is a block diagram which shows the structural example of the column CDS system (analog amplification type) CMOS image sensor which concerns on 2nd Embodiment of this invention. It is a circuit diagram which shows an example of the circuit structure from one pixel of a certain column to the AFE part in the column CDS type CMOS image sensor according to the second embodiment. It is a timing chart with which it uses for description of the circuit operation | movement of the CDS circuit which concerns on 2nd Embodiment. It is a circuit diagram which shows the circuit structure from one pixel of a certain column to the AD converter circuit of the said column in the conventional column ADC type CMOS image sensor. It is a timing chart with which it uses for description of the circuit operation | movement of the AD converter circuit which concerns on a prior art example.

Explanation of symbols

  10A, 10B ... column processing unit (column signal processing unit), 11 unit pixel, 12 ... pixel array unit, 13 (13-1, 13-2) ... row control line, 14 (14-1, 14-2) DESCRIPTION OF SYMBOLS ... Column signal line, 15 ... Row scanning circuit, 16 ... Constant current source, 17 (17-1, 17-2) ... AD converter circuit, 18 ... DA converter circuit, 19 ... Counter, 20 ... Comparator , 21 ... Memory device, 22 ... Column scanning circuit, 23, 32 ... Horizontal output line, 24 ... Output circuit, 25 ... Timing control circuit, 30 (30-1, 30-2) ... CDS circuit, 31 ... Analog front end 111, photodiode, 112, transfer transistor, 113, reset transistor, 114, amplification transistor, 201, 301 ... differential transistor

Claims (5)

The photoelectric conversion element and the photoelectric conversion unit pixel having an amplification transistor that outputs a signal corresponding to the charge obtained by the element is arranged Rutotomoni, a pixel array portion signal line for each column is formed by the wiring,
A signal processing unit having a differential transistor that is provided on the same substrate as the pixel array unit and that forms a differential pair with the amplification transistor by commonly connecting the amplification transistor and the source via the signal line ; With
When the signal processing means derives a signal output from the unit pixel to the signal line through the differential transistor, the signal processing means calculates a threshold voltage variation due to a substrate bias effect in the amplification transistor and the differential transistor. A solid-state imaging device that cancels out by a differential operation of the amplification transistor and the differential transistor . The signal processing means includes the differential transistor in an input stage, and converts an analog signal input from the unit pixel via the differential transistor into an n-bit digital signal and outputs the analog signal. The solid-state imaging device according to claim 1. The analog-digital conversion circuit includes a comparator having a differential configuration including the pixel transistor having a floating diffusion potential in the unit pixel as a gate input and the differential transistor having a reference voltage as a gate input. Item 3. The solid-state imaging device according to Item 2. The solid-state imaging device according to claim 2, wherein the analog-digital conversion circuit is provided for each column signal line. The photoelectric conversion element and the photoelectric conversion unit pixel having an amplification transistor that outputs a signal corresponding to the charge obtained by the element is arranged Rutotomoni, a pixel array portion signal line for each column is formed by the wiring,
A signal processing unit having a differential transistor that is provided on the same substrate as the pixel array unit and that forms a differential pair with the amplification transistor by commonly connecting the amplification transistor and the source via the signal line;
Against the driving of the solid state imaging device provided with,
In the signal processing means, when a signal output from the unit pixel to the signal line is derived through the differential transistor, a variation in threshold voltage due to a substrate bias effect in the amplification transistor and the differential transistor is calculated. A signal processing method of a solid-state imaging device that cancels out by a differential operation of the amplification transistor and the differential transistor .

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