JP6845927B2 - Solid-state image sensor, manufacturing method of solid-state image sensor, and electronic equipment - Google Patents

Description

The present invention relates to a solid-state image sensor, a method for manufacturing a solid-state image sensor, and an electronic device.

A CMOS (Complementary Metal Oxide Semiconductor) type image sensor is attracting attention as a solid-state image sensor that can be produced at low cost because it can be produced by a semiconductor forming process, which is a general-purpose CMOS process.

By the way, in generating high-quality still images and moving images, the output ratio (S / N ratio) of the voltage signal and noise is improved by reducing vertical line noise (also referred to as "row noise"). It is an important matter to let them do it.

In particular, in a CMOS image sensor, it is a big problem to reduce baseline noise, which is perceived as a phenomenon in which an image does not turn black even in the dark. It is known that the baseline noise has a strong correlation with the 1 / f noise (also referred to as “flicker noise”) generated by the amplification transistor included in the pixel. In order to reduce the baseline noise, it is important to reduce the 1 / f noise generated in the amplification transistor.

In order to reduce 1 / f noise, it is known that it is effective to reduce dangling bonds (unbonded hands) existing in the silicon of the amplification transistor and the gate oxide film. One method of reducing dangling bonds is to bond fluorine to dangling bonds. For example, it is conceivable to introduce fluorine into the amplification transistor by the ion implantation method.

In view of this situation, a CMOS image sensor that reduces 1 / f noise by injecting fluorine into an amplification transistor has been proposed (Patent Document 1).

Japanese Patent Publication "Japanese Unexamined Patent Publication No. 2015-90971 (published on May 11, 2015)"

However, even the CMOS image sensor of Patent Document 1 has a problem that the reduction of 1 / f noise is not sufficient.

Patent Document 1 is a method of injecting fluorine into an amplification transistor in a limited manner to reduce 1 / f noise caused by a pixel region. The present inventor has considered that while the performance of the solid-state image sensor has been improved by reducing the 1 / f noise caused by the pixel region, there is a limit to the reduction of the 1 / f noise by itself.

Therefore, from another viewpoint, it was examined whether 1 / f noise could be reduced. As a result, they have found that further performance improvement can be achieved by reducing 1 / f noise caused by the analog-to-digital conversion circuit unit, and have completed the invention.

One aspect of the present invention is an object of the present invention to provide a further method for improving the performance of a solid-state image sensor in view of the above problems.

In order to solve the above problems, the solid-state image sensor according to one aspect of the present invention is an analog-to-digital conversion circuit that analog-digitally converts voltage signals output from a pixel region and pixels arranged in the pixel region. The analog-to-digital conversion circuit unit includes a MOS transistor in which fluorine is integrated in the vicinity of the interface between the semiconductor substrate and the gate oxide film arranged on the semiconductor substrate.

According to one aspect of the present invention, the solid-state image sensor has an effect of obtaining performance that has never been achieved so far.

It is a top view which shows the schematic structure of the solid-state image sensor which concerns on one Embodiment of this invention. It is a top view which shows the schematic structure of the ADC circuit part included in the solid-state image sensor. It is a circuit diagram which shows the structure of the Comparator included in the ADC circuit part. (A) to (e) are cross-sectional views showing a manufacturing process of the n-type MOS transistor included in the Comparator. It is a graph which shows the fluorine concentration profile in the n-type MOS transistor immediately after the fluorine injection and after the process final process, respectively.

Hereinafter, embodiments of the present invention will be described in detail.

In the drawings used in the following description, the same parts are designated by the same reference numerals. Their names and functions are also the same. Therefore, the detailed description of them will not be repeated.

The drawings are schematic, and the relationship between the thickness and the plane dimensions, the ratio of the thickness of each layer, etc. are different from the actual ones. Even between drawings, there are parts where the relationship and ratio of dimensions are different from each other.

(Structure of solid-state image sensor 1)
The solid-state image sensor 1 according to the embodiment of the present invention is a CMOS image sensor. The CMOS type image sensor generally has a light receiving region, a floating diffusion unit (FD unit), and an analog-digital conversion circuit unit (Analog Digital Converter, hereinafter referred to as “ADC circuit unit”). The light receiving region performs photoelectric conversion of the image light, the floating diffusion unit converts the signal charge obtained by the photoelectric conversion into a voltage signal, and the ADC circuit unit converts the converted signal charge into analog-digital conversion. The light receiving region, the floating diffusion unit, and the ADC circuit unit are provided on a common substrate.

In the light receiving area, photodiodes as a plurality of light receiving parts that generate electric charges by light irradiation are provided for each pixel, and in the FD part, the electric charges generated in each light receiving part of the light receiving area are pixels as signal charges. Read from. The read signal charge is converted into a voltage signal, which is an analog signal, in the pixel. The voltage signal is read out for each pixel via the signal wiring and input to the ADC circuit unit. The ADC circuit unit converts the input voltage signal into a digital signal.

Hereinafter, the solid-state image sensor 1 will be specifically described with reference to FIG. FIG. 1 is a plan view showing a schematic configuration of a solid-state image sensor 1 according to an embodiment of the present invention.

As shown in FIG. 1, the solid-state image sensor 1 includes a pixel region 11, an ADC circuit unit 12, and a peripheral circuit unit 13.

In the pixel region 11, a plurality of pixels 51 (see FIG. 2) are arranged in a two-dimensional matrix (array) to form a rectangular imaging region. The ADC circuit unit 12 and the peripheral circuit unit 13 are arranged around the pixel region 11. The ADC circuit unit 12 performs analog-digital conversion of the voltage signal output from each pixel of the pixel area 11 for each column of the pixel area 11. The peripheral circuit unit 13 generates an captured image by performing logic processing on the voltage signal converted from analog to digital by the ADC circuit unit 12.

(Structure of ADC circuit unit 12)
FIG. 2 is a plan view showing a schematic configuration of the ADC circuit unit 12.

As shown in FIG. 2, a Sensor Array 50 in which a plurality of pixels 51 are arranged in a two-dimensional matrix is arranged in the pixel region 11. The ADC circuit unit 12 analog-digitally converts the voltage signal output from each pixel 51 of the Sensor Array 50 arranged in the pixel region 11 for each column.

Specifically, the ADC circuit unit 12 corresponds to each row of the RAM P22 and the pixel area 11 (more specifically, the Sensor Array50), and a plurality of Column A / D23s and Gray provided for each row. Includes Code Counter 24. Since the Gray Code Counter 24 is a member that is not directly related to the present embodiment, the description thereof will be omitted, but it may be understood that the Gray Code Counter 24 is the same as a known one.

A voltage signal output from the pixel 51 included in the row of the pixel region 11 corresponding to the Column A / D 23 is input to each Column A / D 23 via the Column 25. The Comparator 26 (comparator) compares the input voltage signal with the RAMP waveform (reference value) generated by the RAMP 22, and outputs the comparison result to the W-Latch 27.

(Structure of Comparator 26)
FIG. 3 is a circuit diagram showing the configuration of the Company 26. As shown in FIG. 3, the Compactor 26 includes an inverter circuit 31 which is a CMOS transistor composed of a p-type MOS transistor 32 and an n-type MOS transistor 33.

Hereinafter, a method of manufacturing the inverter circuit 31 will be described by taking the n-type MOS transistor 33 as an example. FIGS. 4A to 4E are cross-sectional views showing a manufacturing process of the n-type MOS transistor 33. In the manufacturing process shown in FIGS. 4A to 4E, a general MOS transistor manufacturing method is used. Therefore, detailed description thereof will be omitted.

In FIG. 4A, the element separation region 101, the gate oxide film 102, the gate electrode 103 made of polysilicon, the low-concentration impurity diffusion region 104, which is the source region and the drain region, are injected into the silicon substrate 100 (semiconductor substrate). The protective film 105 and the sidewall spacer 106 are sequentially formed.

Next, in FIG. 4B, the resist film 107 is formed so as to open the low-concentration impurity diffusion region 104, the gate electrode 103, and the sidewall spacer 106. Fluorine is ion-implanted through the implantation protective film 105 using the resist film 107 as a mask. It is desirable that the ion implantation conditions are such that the implantation energy is 50 keV to 60 keV and the dose amount is in the range of 1 × 10 ¹⁵ / cm ² to 1 × 10 ¹⁶ / cm ^2.

What should be noted here is that the ion implantation conditions are selected from the viewpoint of efficiently accumulating fluorine at the interface between the gate oxide film 102 and the silicon substrate 100. This point will be described below.

FIG. 5 is a graph showing the fluorine concentration profile in the n-type MOS transistor 33 immediately after the fluorine injection and after the final process treatment. The fluorine concentration profile is a SIMS (Secondary Ion Mass Spectrometry) profile. Fluorine ion 19F ⁺ was ion-implanted at an implantation energy of 50 keV and a dose amount of 5 × 10 ¹⁵ / cm ² . The average range (fluorine injection range depth) was about 110 nm. The film thickness of the gate electrode 103 was 200 nm.

The average range means the average value of the range in which each ion travels in the object when a plurality of ions are implanted into the object. The ion-implanted ions eventually become neutral atoms, stop, and are Gaussian-distributed within the ion-implanted object. Therefore, the average range of ions refers to the peak position of the Gaussian distribution of impurities stopped in the object.

As shown in FIG. 5, the peak (maximum value) of the fluorine concentration profile remains near the average flight even after the final manufacturing process of the inverter circuit 31, and is shallower than the average flight ( It is presumed that the fluorine on the gate electrode 103 side as viewed from the gate oxide film 102) diffused outward to the surface side of the gate electrode 103. On the other hand, it was found that fluorine on the side deeper than the average range (on the gate oxide film 102 side when viewed from the gate electrode 103) was accumulated near the interface between the gate oxide film 102 and the silicon substrate 100.

The accumulation of fluorine near the interface between the gate oxide film 102 and the silicon substrate 100 indicates that the dangling bond existing at the interface is terminated by a Si—F bond. The present inventor further confirmed that 1 / f noise was saturated by setting the dose amount in the range of 1 × 10 ¹⁵ / cm ² or more and 1 × 10 ¹⁶ / cm ^{2 or less, and the terminability was improved.} I found that it was done well.

Therefore, by setting the injection energy in the range of 50 keV or more and 60 keV or less, the average flight distance is located closer to the gate oxide film 102 than the intermediate thickness position of the gate electrode 103, and the gate oxide film is located closer to the gate oxide film 102 than the peak of the fluorine concentration profile. Fluorine on the 102 side can be efficiently accumulated near the interface between the gate oxide film 102 and the silicon substrate 100.

However, when the injection energy exceeds 60 keV, the damage at the time of injection affects the gate oxide film 102, and conversely, the noise tends to worsen. Therefore, the injection energy is set so that the average range is in the range from the intermediate thickness position of the gate electrode 103 to the interface between the gate electrode 103 and the gate oxide film 102 according to the film thickness of the gate electrode 103. Is desirable.

Further, as shown in FIG. 4B, the injection of fluorine forms an injection damage layer 108 in the low-concentration impurity diffusion region 104 and the gate electrode 103. It was raised as a concern that the injection damage layer 108 causes a defect-induced leak in the low-concentration impurity diffusion region 104, but the junction leak level in the low-concentration impurity diffusion region 104 is almost constant regardless of the presence or absence of fluorine injection. there were. Therefore, it can be said that no particular problem occurs within the range of the injection conditions of the present embodiment.

Returning to FIG. 4 again, in FIG. 4C, the injection protective film 109 is deposited to form the high-concentration impurity diffusion region 110. In the formation of the high-concentration impurity diffusion region 110, the injected ion species is selected so as to form an n-type region. Needless to say, when manufacturing the p-type MOS transistor 32, the injected ion species is selected so as to form the p-type region. Further, the depth of the injection damage layer 108 from the surface of the silicon substrate 100 is located at a position deeper than the bottom surface of the high-concentration impurity diffusion region 110.

Next, in FIG. 4D, after removing the injection protective film 109, a silicide film 111 is formed on the gate electrode 103, the low-concentration impurity diffusion region 104, and the high-concentration impurity diffusion region 110. After that, the stopper film 112, which serves as an etching stopper when the contact plug 114 is formed, is formed by CVD (Chemical Vapor Deposition). The silicide film 111 is, for example, a titanium silicide film, a cobalt silicide film, or a nickel silicide film. The stopper film 112 is, for example, a silicon nitride film.

Next, in FIG. 4 (e), an interlayer insulating film 113 made of, for example, a silicon oxide film is formed on the stopper film 112. Then, a contact hole is formed through the interlayer insulating film 113 to reach the gate electrode 103, the low-concentration impurity diffusion region 104, and the high-concentration impurity diffusion region 110, and the contact plug 114 is formed so as to embed the contact hole. .. The contact plug 114 can be composed of, for example, a titanium / titanium nitride film formed on the inner wall of the contact hole and a tungsten film in which the contact hole is embedded. A wiring 115 is formed on the interlayer insulating film 113, and the wiring 115 is formed so as to be electrically connected to the contact plug 114. A multilayer wiring structure is formed above the wiring 115, but the description thereof will be omitted.

(Electronics)
The solid-state image sensor 1 uses the solid-state image sensor 1 as an image input device in the image pickup unit, for example, an image input camera such as a digital camera such as a digital video camera or a digital still camera, a surveillance camera, a scanner device, a facsimile device, or a television. It can be applied to electronic devices such as telephone devices and mobile phone devices with cameras.

(Effect of this embodiment)
According to this embodiment, 1 / f noise caused by the ADC circuit unit can be reduced by injecting fluorine into the circuit constituting the ADC circuit unit 12, particularly the inverter circuit included in the Computer 26. This makes it possible to realize an electronic device using a solid-state image sensor, a method for manufacturing the same, and a solid-state image sensor having low noise performance.

(Summary)
The solid-state image sensor 1 according to the first aspect of the present invention includes a pixel region 11 and an analog-to-digital conversion circuit unit 12 for analog-digital conversion of a voltage signal output from pixels 51 arranged in the pixel region 11. The analog-to-digital conversion circuit unit 12 is a MOS transistor (p-type MOS transistor 32 and / or n-type) in which fluorine is integrated in the vicinity of the interface between the silicon substrate 100 and the gate oxide film 102 arranged on the silicon substrate 100. The MOS transistor 33) is included.

According to the above configuration, further performance improvement can be achieved by reducing 1 / f noise caused by the analog-to-digital conversion circuit unit.

In the solid-state image sensor 1 according to the second aspect of the present invention, in the above aspect 1, the MOS transistor (p-type MOS transistor 32 and / or n-type MOS transistor 33) has a dangling bond existing at the interface terminated by fluorine. Is preferable.

The solid-state image sensor 1 according to the third aspect of the present invention is perpendicular to the silicon substrate 100 in the silicon substrate 100, the gate oxide film 102, and the gate electrode 103 arranged on the gate oxide film 102 in the above aspect 1 or 2. It is preferable that the fluorine concentration profile along the above direction has a maximum value in the vicinity of the interface.

In the solid-state imaging device 1 according to the fourth aspect of the present invention, in the above aspect 3, the average flight distance of fluorine by ion implantation along the direction from the gate electrode 103 toward the silicon substrate 100 is the gate electrode inside the gate electrode 103. It is preferably in the range from the intermediate thickness position of 103 to the interface between the gate electrode 103 and the gate oxide film 102.

In the solid-state image sensor 1 according to the fifth aspect of the present invention, in any one of the first to fourth aspects, whether or not the level of the voltage signal output from the pixel 51 of the analog-digital conversion circuit unit 12 reaches the reference value. The comparator 26 includes a comparator 26, and the comparator 26 is an inverter circuit 31 composed of a CMOS transistor including a MOS transistor (p-type MOS transistor 32 and / or n-type MOS transistor 33). Is preferable.

The method for manufacturing the solid-state image sensor 1 according to the sixth aspect of the present invention includes a forming step of forming the gate oxide film 102 and the gate electrode 103 on the silicon substrate 100 in this order in any one of the above aspects 1 to 5. , Including an integration step of accumulating fluorine in the vicinity of the interface between the silicon substrate 100 and the gate oxide film 102.

In the method for manufacturing the solid-state imaging device 1 according to the seventh aspect of the present invention, in the sixth aspect, the fluorine contained in the gate electrode is thermally diffused to the vicinity of the interface between the semiconductor substrate and the gate oxide film in the integration step. It is preferable that the fluorine contained in the gate electrode 103 is terminated by fluorine at the dangling bond existing at the interface.

In the method for manufacturing the solid-state image sensor 1 according to the eighth aspect of the present invention, in the seventh aspect, fluorine is introduced into the gate electrode 103 by ion implantation along the direction from the gate electrode 103 toward the gate oxide film 102 in the integration step. It is preferable to do so.

In the method for manufacturing the solid-state image sensor 1 according to the ninth aspect of the present invention, in the eighth aspect, the dose amount of the ion implantation is 1 × 10 ¹⁵ / cm ² or more and 1 × 10 ¹⁶ / cm ² or less. preferable.

The electronic device according to the tenth aspect of the present invention includes the solid-state image sensor 1 in any one of the above aspects 1 to 5.

As described above, the present invention has been illustrated using the preferred embodiment of the present invention, but the present invention should not be construed as being limited to this embodiment. It is understood that the invention should be construed only by the claims. It will be understood by those skilled in the art that from the description of specific preferred embodiments of the present invention, equivalent ranges can be implemented based on the description of the present invention and common general knowledge. The patents, patent applications and documents cited herein are to be incorporated by reference in their content as they are specifically described herein. Understood.

1 Solid-state image sensor 11 Pixel area 12 Analog-to-digital conversion circuit unit 13 Peripheral circuit unit 22 RAMP
23 Column A / D
24 Gray Code Counter
25 Capacitor
26 Comparator
27 W-Latch
31 Inverter circuit 32 p-type MOS transistor 33 n-type MOS transistor 50 Sensor Array
51 pixels 100 silicon substrate (semiconductor substrate)
101 Element separation area 102 Gate oxide film 103 Gate electrode 104 Low concentration impurity diffusion area 105 Injection protection film 106 Side wall spacer 107 Resist film 108 Injection damage layer 109 Injection protection film 110 High concentration impurity diffusion area 111 EtOAc film 112 Stopper layer 113 Insulation film 114 Contact plug 115 Wiring

Claims (9)

Pixel area and
It is provided with an analog-to-digital conversion circuit unit for analog-digital conversion of a voltage signal output from pixels arranged in the pixel area.
The analog-to-digital conversion circuit unit includes a MOS transistor in which fluorine is integrated in the vicinity of the interface between the semiconductor substrate and the gate oxide film arranged on the semiconductor substrate.
In the semiconductor substrate, the gate oxide film, and the gate electrode arranged on the gate oxide film, the fluorine concentration profile along the direction perpendicular to the semiconductor substrate is the interface between the semiconductor substrate and the gate oxide film. Takes the maximum value in the vicinity of
A solid-state imaging device in which the fluorine concentration profile has a peak in the range from the intermediate thickness position of the gate electrode to the interface between the gate electrode and the gate oxide film. The solid-state image sensor according to claim 1, wherein the MOS transistor is characterized in that a dangling bond existing at an interface between the semiconductor substrate and the gate oxide film is terminated by fluorine. The analog-to-digital conversion circuit unit includes a comparator that determines whether or not the level of the voltage signal output from the pixel has reached a reference value.
The solid-state image sensor according to claim 1 or 2, wherein the comparator is an inverter circuit composed of a CMOS transistor including the MOS transistor. The method for manufacturing a solid-state image sensor according to any one of claims 1 to 3.
A forming step of forming the gate oxide film and the gate electrode on the semiconductor substrate in this order, and
An integration step of accumulating fluorine in the vicinity of the interface between the semiconductor substrate and the gate oxide film by thermally diffusing the fluorine contained in the gate electrode to the vicinity of the interface between the semiconductor substrate and the gate oxide film. Including
The average flight distance of fluorine by ion implantation along the direction from the gate electrode to the semiconductor substrate is from the intermediate thickness position of the gate electrode to the interface between the gate electrode and the gate oxide film inside the gate electrode. A method for manufacturing a solid-state image sensor, which is characterized by being in the range of. In the integration step, fluorine contained in the gate electrode is thermally diffused to the vicinity of the interface between the semiconductor substrate and the gate oxide film, and a dangling bond existing at the interface between the semiconductor substrate and the gate oxide film is present. The method for manufacturing a solid-state imaging device according to claim 4, wherein the image is terminated with fluorine. Pixel area and
It is provided with an analog-to-digital conversion circuit unit for analog-digital conversion of a voltage signal output from pixels arranged in the pixel area.
The analog-to-digital conversion circuit unit includes a MOS transistor in which fluorine is integrated in the vicinity of the interface between the semiconductor substrate and the gate oxide film arranged on the semiconductor substrate.
In the semiconductor substrate, the gate oxide film, and the gate electrode arranged on the gate oxide film, the fluorine concentration profile along the direction perpendicular to the semiconductor substrate is the interface between the semiconductor substrate and the gate oxide film. Takes the maximum value in the vicinity of
The average flight distance of fluorine by ion implantation along the direction from the gate electrode to the semiconductor substrate is from the intermediate thickness position of the gate electrode to the interface between the gate electrode and the gate oxide film inside the gate electrode. It is a method for manufacturing a solid-state image sensor, which is characterized by being in the range of.
A forming step of forming the gate oxide film and the gate electrode on the semiconductor substrate in this order, and
Including an integration step of accumulating fluorine in the vicinity of the interface between the semiconductor substrate and the gate oxide film.
In the integration step, fluorine contained in the gate electrode is thermally diffused to the vicinity of the interface between the semiconductor substrate and the gate oxide film, and a dangling bond existing at the interface between the semiconductor substrate and the gate oxide film is present. A method for manufacturing a solid-state imaging device, which comprises terminating the image with fluorine. The method for manufacturing a solid-state image sensor according to claim 5 or 6, wherein in the integration step, fluorine is introduced into the gate electrode by ion implantation along the direction from the gate electrode toward the gate oxide film. The method for manufacturing a solid-state image sensor according to claim 7, wherein the dose amount of the ion implantation is 1 × 10 ¹⁵ / cm ² or more and 1 × 10 ¹⁶ / cm ^{2 or less.} An electronic device including the solid-state image sensor according to any one of claims 1 to 3.

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