JP2008098255A - Solid-state photographing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state photographing device capable of much more reducing crosstalk between pixels. <P>SOLUTION: An N-type epitaxial layer 52 is arranged on a P-type silicon substrate 51. A P-type epitaxial layer 53 is arranged on the N-type epitaxial layer 52. Respective pixels are provided with a second conductive type charge accumulating unit 55 which accumulates charge converted through photoelectric conversion in accordance with incident light. The charge accumulating units 55 of respective pixels 11 are arranged on the P-type epitaxial layer 53. A carrier or an electron generated in the deep part of the P-type epitaxial layer 53 is diffused toward the N-type epitaxial layer 52 and constituents, which reach the charge accumulating layer 55 of neighbored pixels 11, are decreased extremely. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device.

  In recent years, video cameras and electronic cameras have been widely used. For these cameras, a CCD solid-state imaging device or a CMOS solid-state imaging device (a solid-state imaging device compatible with a CMOS manufacturing process, also called a CMOS image sensor) is used. In a solid-state imaging device, a plurality of pixels each having a photoelectric conversion unit are arranged in a matrix, and signal charges are generated by the photoelectric conversion unit of each pixel.

  The CCD type solid-state imaging device sequentially reads out signal charges generated by a photoelectric conversion unit of each pixel by a vertical CCD and a horizontal CCD.

  On the other hand, in the CMOS type solid-state imaging device, signals output from the pixels are read out to the vertical signal lines for each row and further read out sequentially to the horizontal lines. A CMOS solid-state imaging device is generally configured as an amplification-type solid-state imaging device. In the amplification type solid-state imaging device, each pixel has an amplification unit (pixel amplifier), the signal charge obtained by the photoelectric conversion unit is amplified by the amplification unit, and the amplified signal is output from the pixel. .

  For manufacturing a CMOS type solid-state imaging device, a manufacturing process generally used in a CMOS circuit is used. Therefore, in a CMOS type solid-state imaging device, a processor, a logic circuit, an analog-digital conversion circuit, and the like can be easily provided in the same chip together with a pixel portion including a plurality of pixels. For this reason, CMOS solid-state imaging devices have been attracting attention in recent years.

  An example of such a CMOS type solid-state imaging device is disclosed in Patent Document 1 below. The solid-state imaging device disclosed in Patent Document 1 employs a configuration that reduces crosstalk between pixels that is generated when electrons move between adjacent photoelectric conversion units.

  Here, the solid-state imaging device disclosed in Patent Document 1 will be described with reference to FIGS. 11 and 12. 11 and 12 correspond to FIGS. 2 and 3 of Patent Document 1, respectively.

  FIG. 11 is a cross-sectional view schematically showing a main part of a pixel of this solid-state imaging device. FIG. 12 is a diagram showing an impurity concentration profile in the depth direction of the photodiode portion of the pixel shown in FIG.

In FIG. 11, a P ⁻ layer 128 having a considerably lower impurity concentration than the substrate P ⁺ layer 126 is formed on a substrate P ⁺ layer 126 which is a high concentration P-type semiconductor substrate. P ^- on the layer 128, the substrate ^{P +} and lower impurity concentration than the layer 126 P ^- high impurity concentration P-type layer 127 is formed than layer 128. The P-type layer 127 is provided with an N-type photoelectric conversion region 114 at an upper position thereof. The N-type photoelectric conversion region 114 is a charge storage portion that stores charges photoelectrically converted according to incident light, and is joined to the P-type layer 127 to form a photodiode as a photoelectric conversion portion.

A P ⁺ -type element isolation region 115 and an element isolation oxide film 116 are provided on both ends of the upper surface of the P-type layer 127 in the figure for element isolation. In order to prevent leakage on the surface of the photodiode portion, a surface P ⁺ layer 125 is formed on the surface of the P-type layer 127 and the N-type photoelectric conversion region 114 (excluding the region where the element isolation oxide film 116 is formed). A gate oxide film 117 is formed thereon. An interlayer insulating film 118 is provided on the element isolation oxide film 116 and the gate oxide film 117 so as to cover the entire solid-state imaging device including this pixel. A light shielding film 119 is formed in the interlayer insulating film 118 to prevent light from entering the unnecessary portions.

In this solid-state imaging device, when incident light enters a photodiode including the N-type photoelectric conversion region 114 and the P-type layer 127, the N-type photoelectric conversion region 114 is incident on the incident light during the signal charge accumulation period. In addition, an electron / hole pair is generated in the region of the P-type layer 127 underneath. The generated electrons are accumulated in a depletion layer formed in the N-type photoelectric conversion region 114 and the P-type layer 127 below the N-type photoelectric conversion region 114. At this time, since there is a P ⁻ layer 128 having an impurity concentration lower than that of the P type layer 127 below the P type layer 127, electrons generated in the P type layer 127 are transferred to the P ⁻ layer 128 having a low potential. It becomes easy to diffuse. Since the high-concentration substrate P ⁺ layer is formed, electrons that have once reached the P ⁻ layer 128 are then reliably transferred to the substrate P ⁺ layer 126 before diffusing in the lateral direction (the direction of the adjacent basic cell). Captured and recombined to disappear.

As shown in FIG. 12, the depletion layer that becomes the photoelectric conversion region is a portion indicated by an arrow whose depth direction is approximately halfway between the depth portions of the N-type photoelectric conversion region 114 and the P-type layer 127. . Photoelectrons generated deeper than the middle of the P-type layer 127 are effectively diffused in the direction of the P ⁻ layer 128, and even if diffused in the lateral direction, they do not reach the depletion layer on the surface side again ( Suppression of electron diffusion) and no longer contributes to sensitivity. Furthermore, since electrons that have reached the P ⁻ layer 128 are annihilated by recombination in the substrate P ⁺ layer 126, they do not contribute to the sensitivity here either. Thereby, the diffusion of electrons in the lateral direction is suppressed, and crosstalk between pixels can be reduced.
JP 2002-170945 A

  According to the solid-state imaging device disclosed in Patent Document 1, as described above, crosstalk between pixels can be reduced. However, demands for reducing noise in solid-state imaging devices have become increasingly severe in recent years, and the conventional solid-state imaging device having the configuration disclosed in Patent Document 1 has a limit in reducing crosstalk.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a solid-state imaging device capable of further reducing crosstalk between pixels.

  As a result of further research, the present inventor has found the cause of the limitation in the crosstalk reduction in the solid-state imaging device disclosed in Patent Document 1. The cause will be described below.

As described with reference to FIGS. 11 and 12, the solid-state imaging device disclosed in Patent Document 1, P ^- charges generated in the layer 128 (or, P ^-. Charges reaches the layer 128 charge and is here in component directed to ^{the P +} layer 126 of the electron) is extinguished are recombined in ^{the P +} layer 126. For this reason, since this component does not cause crosstalk between pixels, crosstalk between pixels is reduced accordingly.

However, the component toward the P ⁺ layer 126 as described above is only a part of the charge generated in the P ⁻ layer 128. Most of the charge generated in the P ⁻ layer 128 diffuses not toward the P ⁺ layer 128 but toward the N type layer 114, and a part of the charge reaches the N type layer 114 of the adjacent pixel to cross. Talk.

  Therefore, the solid-state imaging device disclosed in Patent Document 1 has a limit in reducing crosstalk between pixels.

  The present invention has been made based on the results of such cause investigation. That is, in order to solve the above-described problem, a solid-state imaging device according to the first aspect of the present invention includes a first conductive type first semiconductor layer and a second conductive type first semiconductor layer disposed on the first semiconductor layer. Two semiconductor layers, a third semiconductor layer of the first conductivity type disposed on the second semiconductor layer, and a plurality of pixels, each pixel being the second semiconductor in the third semiconductor layer A plurality of pixels that are arranged in a region on the layer and that have the second conductivity type charge accumulating unit that accumulates electric charges photoelectrically converted according to incident light, and that output analog signals according to the electric charges. It is a thing.

  In the solid-state imaging device according to the second aspect of the present invention, in the first aspect, the first semiconductor layer is a substrate layer, the second semiconductor layer is a layer formed by epitaxial growth, and the third semiconductor The layer is a layer formed by epitaxial growth.

  A solid-state imaging device according to a third aspect of the present invention is the solid-state imaging device according to the first or second aspect, wherein the circuit related to the operation of the plurality of pixels and the second semiconductor layer on the first semiconductor layer are provided. A fourth semiconductor layer arranged in a continuous manner, and the third semiconductor layer is formed not only on the second semiconductor layer but also on the fourth semiconductor layer to constitute the circuit. A plurality of semiconductor elements are arranged in a region on the fourth semiconductor layer in the third semiconductor layer.

  A solid-state imaging device according to a fourth aspect of the present invention is the solid-state imaging device according to the third aspect, wherein the second semiconductor layer and the fourth semiconductor layer are layers formed by epitaxial growth performed simultaneously.

  In the solid-state imaging device according to the fifth aspect of the present invention, in the third or fourth aspect, the conductivity type of the fourth semiconductor layer is the first conductivity type, and the third semiconductor layer is the fourth semiconductor. It is electrically connected to the first semiconductor layer through a layer.

  According to a sixth aspect of the present invention, in the first or second aspect, the solid-state imaging device includes a circuit related to the operation of the plurality of pixels, and the plurality of semiconductor elements constituting the circuit are the third semiconductor. Disposed in a region of the layer on the second semiconductor layer.

  The solid-state imaging device according to a seventh aspect of the present invention is the solid-state imaging device according to any one of the third to sixth aspects, wherein the charge storage portions of the plurality of pixels in the third semiconductor layer are disposed, A region where the plurality of semiconductor elements are arranged in the third semiconductor layer is electrically separated.

  In the solid-state imaging device according to the eighth aspect of the present invention, in any one of the third to seventh aspects, the impurity concentration of the third semiconductor layer is lower than the impurity concentration of the first semiconductor layer.

  The solid-state imaging device according to a ninth aspect of the present invention is the solid-state imaging device according to any one of the third to eighth aspects, wherein the circuit processes the analog signals output from the plurality of pixels and responds to the analog signals. And a signal processing circuit for outputting the digital signal to the outside.

  A solid-state imaging device according to a tenth aspect of the present invention, according to any one of the first to ninth aspects, is formed by epitaxial growth between the first semiconductor layer and the second semiconductor layer and the first semiconductor layer. The fifth semiconductor layer of the first conductivity type having a lower impurity concentration than the semiconductor layer is disposed.

  ADVANTAGE OF THE INVENTION According to this invention, the solid-state imaging device which can reduce the crosstalk between pixels more can be provided.

  Hereinafter, a solid-state imaging device according to the present invention will be described with reference to the drawings.

  [First Embodiment]

  FIG. 1 is a schematic configuration diagram showing an overall configuration of a solid-state imaging device 1 according to the first embodiment of the present invention. The solid-state imaging device 1 according to the present embodiment is configured as a CMOS type.

  The solid-state imaging device 1 includes a pixel unit 2 including a plurality of pixels 11 (not shown in FIG. 1, see FIG. 2) arranged two-dimensionally and a peripheral circuit. The peripheral circuit includes a timing generator circuit 3 that generates a timing signal necessary for driving to read out a signal from the pixel 11, a vertical scanning circuit 4 and a horizontal scanning circuit 5 for selecting an output of the pixel 11, and the selected pixel. A CDS circuit 6 that amplifies an analog signal from the CDS circuit 6 and performs a correlated double sampling process, and a digital output circuit 7 that processes an analog signal output from the CDS circuit 6 and outputs it as a digital signal. In the present embodiment, the timing generator circuit 3, the vertical scanning circuit 4, and the horizontal scanning circuit 5 constitute a drive circuit that drives the pixels 11 of the pixel unit 2. In the present embodiment, the CDS circuit 6 and the digital output circuit 7 process an analog signal output from the pixel 11 of the pixel unit 2 and output a digital signal corresponding to the analog signal to the outside. Is configured.

  The digital output circuit 7 includes an A / D conversion unit 8 that performs analog / digital conversion on an input analog signal, a digital signal processing (DSP) unit 9 that converts a digitized signal into a digital image signal, and a digital image signal And an interface (IF) unit 10 for receiving command data from the outside.

  FIG. 2 is a circuit diagram showing a part of the solid-state imaging device 1 shown in FIG. 1 (mainly, the pixel unit 2, the vertical scanning circuit 4, the horizontal scanning circuit 5, and the CDS circuit 6). In FIG. 2, the timing generator circuit 3 and the digital output circuit 7 in FIG. 1 are not shown. In FIG. 2, the pixel unit 2 is illustrated as having 3 × 3 pixels 11, but the number of pixels is not limited thereto.

  As shown in FIG. 2, each pixel 11 includes a photoelectric conversion unit 13, a transfer transistor 14, a pixel amplifier 15, a row selection transistor 16, and a reset transistor 17. Here, the transfer transistor 14, the pixel amplifier 15, the row selection transistor 16, and the reset transistor 17 are all NMOS transistors.

  The transfer transistors 14 have gates commonly connected in the row direction by the drive wiring 21 and operate according to the drive signal φTG (n, n + 1) of the vertical scanning circuit 4. The gates of the row selection transistors 16 are commonly connected in the row direction by the drive wiring 22 and operate according to the drive signal φL (n, n + 1) of the vertical scanning circuit 4. The reset transistors 17 have gates commonly connected in the row direction by the drive wiring 23 and operate in accordance with the drive signal φRS (n, n + 1) of the vertical scanning circuit 4. The drain of the pixel amplifier 15 and the drain of the reset transistor 17 are connected in common to all the pixels, and are connected to the power supply voltage VDD via the wiring 24. The source of the pixel amplifier 15 is connected to the drain of the row selection transistor 16, and the source of the row selection transistor 16 is connected to the vertical signal line 32 in the column direction.

  A constant current source 33 and a vertical signal line reset transistor 34 for resetting the vertical signal line 32 are disposed at one end of each vertical signal line 32. A constant voltage VCS is applied to the constant current source 33, and a constant voltage VRV is applied to the vertical signal line reset transistor. Here, both VCS and VRV are set to the ground potential. A drive signal φRV is applied to the gate of the vertical signal line reset transistor 34, and the vertical signal line 32 is reset in accordance with the drive signal φRV.

  The other end of each vertical signal line 32 is connected to the horizontal signal line 31 via the column amplifier 35, the CDS circuit 6, and the horizontal switch transistor 37. An output amplifier 38 and a horizontal reset transistor 39 are connected to the horizontal signal line 31. The gate of the horizontal switch transistor 37 is connected to the drive wiring 25. The horizontal switch transistor 37 is operated by a drive signal φH from the horizontal scanning circuit 5. The horizontal reset transistor 39 operates with the drive signal φRH, and resets the horizontal signal line 31 to a constant potential VRH. An output signal from the output amplifier 38 is input to the digital output circuit 7 (particularly, the A / D converter 8) in FIG.

  The CDS circuit 6 performs correlated double sampling. The electrical signal output from the pixel amplifier 15 includes a dark level corresponding to fixed pattern noise, reset noise, and the like (hereinafter simply referred to as noise). The dark level changes every time the gate potential of the pixel amplifier 15 is reset. Therefore, first, an electrical signal (dark level) corresponding to noise immediately after reset is output from the pixel 11 and temporarily stored in the CDS circuit 6. Next, the photoelectric charge accumulated in the photoelectric conversion unit 13 is transferred to the gate of the pixel amplifier 15, and an electric signal corresponding to the photoelectric charge superimposed on the noise is output from the pixel to the CDS circuit 6. A corresponding true electric signal is output to the horizontal signal line 31. Here, the CDS circuit 6 includes a clamp capacitor 26 that temporarily accumulates a dark level for each column, and a clamp transistor 27 that sets one electrode of the clamp capacitor 26 to a constant potential VRH. The method of correlated double sampling is a well-known technique, and detailed description thereof is omitted here.

  In the solid-state imaging device 1 according to the present embodiment, the drive signals φTG, φL, and φRS are output at a predetermined timing from the vertical scanning circuit 4 according to the signal from the timing generator circuit 3, and the drive from the horizontal scanning circuit 5. Signal φH is output at a predetermined timing. Further, the drive signals φRV, φRH, and φSH are output from the timing generator circuit 3 at a predetermined timing. As a result, signal read driving is performed.

  Here, the read driving of this signal will be briefly described. After the exposure is started and a predetermined time elapses, the row selection transistor 16 of the selected row is turned on, and the source follower reading is started. At the same time, the reset transistor 17 in the selected row is turned on. As a result, the floating diffusion portion and the gate of the pixel amplifier 15 are reset to the power supply voltage VDD. Next, the reset transistor 17 is turned off, but the floating diffusion portion and the gate of the pixel amplifier 15 hold the potential at the time of reset.

  In parallel with this operation, source follower readout is performed, and a signal (hereinafter referred to as a dark signal) corresponding to the above-described reset potential is output to the vertical signal line 32 from the pixel amplifier 15 via the row selection transistor 16. And held in the CDS circuit 6.

  Next, the transfer transistor 14 is turned on, and charges due to incident light accumulated in the charge storage layer 55 (see FIG. 4) of the photoelectric conversion unit 13 are transferred to the floating diffusion units 41 and 42 (see FIG. 3). . Then, an electric signal (hereinafter referred to as a bright signal) corresponding to the voltage at which the electric charge due to the reset light and the incident light is superimposed is output to the vertical signal line 32 and held in the CDS circuit 6.

  The CDS circuit 6 subtracts the dark signal from the bright signal and outputs a true signal from which noise at the time of reset is removed to the digital output circuit 7.

  Here, the structure of each pixel 11 of the pixel unit 2 of the solid-state imaging device 1 shown in FIG. 1 will be described with reference to FIGS. 3 and 4. FIG. 3 is a schematic plan view schematically showing 2 × 2 pixels 11 of the solid-state imaging device 1 shown in FIG. FIG. 4 is a schematic cross-sectional view taken along the line A-A ′ in FIG. 2. In FIG. 3 and FIG. 4, each wiring electrode etc. is abbreviated. In practice, a color filter and a microlens are disposed above the photoelectric conversion unit 13, but are omitted here.

  In FIG. 3, reference numerals 41, 42, 48, 49, and 50 are N-type impurity diffusion regions that are part of the above-described transistors, and reference numerals 43, 44, 45, and 46 are the respective transistors made of polysilicon. This is the gate (electrode). Reference numeral 48 denotes a power supply diffusion unit to which the power supply voltage VDD is applied, and reference numerals 41 and 42 denote floating diffusion units. The electrodes 43, 44, and 46 are connected to the drive wirings 21, 23, and 22, respectively, and drive signals φTG, φRS, and φL output from the vertical scanning unit 4 are applied thereto.

  The photoelectric conversion unit 13 is a buried photodiode including a charge storage layer 55 and a depletion prevention layer 54. However, the photoelectric conversion unit 13 may be a photodiode without the depletion prevention layer 54 instead of the embedded photodiode.

  The photoelectric conversion unit 13 photoelectrically converts incident light and accumulates the generated charges in the charge accumulation layer 55. The charges accumulated in the charge accumulation layer 55 of the photoelectric conversion unit 13 are transferred to the floating diffusion units 41 and 42 when the transfer transistor 14 is turned on.

  The transfer transistor 14 is a MOS transistor having the charge storage layer 55 of the photoelectric conversion unit 13 as a drain and one floating diffusion unit 41 as a source. The transfer transistor 14 is driven by a drive signal φTG applied to its gate 43 (hereinafter referred to as transfer gate).

  The floating diffusion portions 41 and 42 include a first floating diffusion portion 41 disposed adjacent to the transfer gate 43 and a second floating diffusion portion 42 separated from the first floating diffusion portion 41 by an isolation region 56. They are electrically connected by the wiring electrode 47. The floating diffusion portions 41 and 42 are electrically connected to the gate 45 of the pixel amplifier 15 by the wiring electrode 47.

  The pixel amplifier 15 is a MOS transistor having the power source diffusion portion 48 as a drain and the diffusion region 49 as a source. As described above, the gate 45 of the pixel amplifier 15 is connected to the floating diffusion portions 41 and 42 (the source of the transfer transistor 14). Then, the pixel amplifier 15 outputs an electrical signal corresponding to the voltage of the gate 45. Accordingly, the pixel amplifier 15 outputs an electrical signal corresponding to the amount of charge generated and accumulated in the photoelectric conversion unit 13.

  The row selection transistor 16 is a MOS transistor having the diffusion region 49 as a drain and the diffusion region 50 as a source. The row selection transistor 16 outputs the output of the pixel amplifier 15 to the vertical signal line 32 by being turned on. In other words, the pixel amplifier 15 and the row selection transistor 16 enable reading by the source follower.

  The reset transistor 17 is a MOS transistor having the power supply diffusion portion 48 as a drain and the second floating diffusion portion 42 as a source. The reset transistor 17 resets the electric charge accumulated in the floating diffusion portions 41 and 42 by being turned on.

  In the solid-state imaging device 1 according to the present embodiment, as shown in FIG. 4, an N-type epitaxial layer 52 is disposed on a P-type silicon substrate 51, and further a P-type epitaxial layer 53 is provided thereon. ing.

  In the present embodiment, the P-type epitaxial layer 53 is used as an element formation layer for forming the above-described semiconductor elements (photodiodes and transistors) constituting each pixel 11 of the pixel unit 2. The above-described semiconductor elements constituting the respective pixels 11 are arranged on the surface side of the P-type epitaxial layer 53. That is, in the present embodiment, the N-type charge accumulation layer 55 and the P-type depletion prevention layer 54 of the photoelectric conversion unit 13 of each pixel 11, and the above-described N-type impurity diffusion regions 41 of each pixel 11, 42, 48, 49 and 50 are arranged in the P-type epitaxial layer 53. The charge storage layer 55, the depletion prevention layer 54, and the N-type impurity diffusion regions 41, 42, 48, 49, and 50 are formed by diffusing impurities into the P-type epitaxial layer 53 by ion implantation.

  As shown in FIG. 4, each pixel 11 is separated by a LOCOS oxide film 56. Note that an isolation diffusion portion may be provided under the LOCOS oxide film 56. Further, impurities may be further diffused into the P-type epitaxial layer 53 in order to adjust the impurity concentration as appropriate. That is, the P-type epitaxial layer 53 may be a layer formed simply by epitaxial growth, or may be a layer obtained by further diffusing impurities in the layer formed by epitaxial growth.

  Here, the effect of this configuration will be described with reference to FIG. FIG. 5 is a diagram illustrating an impurity concentration profile and potential in the depth direction of the photoelectric conversion unit 13 of the solid-state imaging device 1. FIG. 5A shows the impurity concentration profile, and FIG. 5B shows the potential.

  Electrons that are carriers generated in the deep portion of the P-type epitaxial layer 53 are diffused. However, electrons diffuse toward the N-type layer. Therefore, when the N-type epitaxial layer 52 is arranged as in the present embodiment, more components diffuse toward this. This is because, as understood from FIG. 5B, the N-type epitaxial layer 52 has a lower potential than the upper and lower P-type layers 51 and 53, and electrons diffuse to the lower potential side. Therefore, the component reaching the charge storage layer 55 of the adjacent pixel 11 is extremely small.

  On the other hand, as in the conventional solid-state imaging device disclosed in Patent Document 1 described above, if the N-type epitaxial layer 52 is not provided, the adjacent pixels 11 among the carriers generated in the deep part of the P-type epitaxial layer 53 will be described. More components reach the charge storage layer 55.

  Therefore, according to this embodiment, crosstalk between pixels can be further reduced as compared with the conventional solid-state imaging device disclosed in Patent Document 1 described above.

  Moreover, according to this Embodiment, the following effect is also acquired. Each pixel 11 is arranged in the P-type epitaxial layer 53. The epitaxial layer can be formed with good thickness control. On the other hand, in the present invention, instead of the P-type epitaxial layer 53, the N-type epitaxial layer 52 may be formed thick in advance and the P-type layer may be provided by impurity diffusion such as ion implantation. However, when a P-type layer replacing the P-type epitaxial layer 53 is formed in this way, it becomes more difficult to control the film thickness than when an epitaxial layer is formed. When the thickness of the P-type layer varies, as will be understood from the above description, variations occur in the characteristics of crosstalk between pixels. For this reason, a difference occurs in noise for each pixel 11. In the present embodiment, since the P-type epitaxial layer 53 is provided, there is also an effect that variations in crosstalk characteristics between pixels hardly occur.

  FIG. 6 is a conceptual cross-sectional view showing the pixel unit 2 and the peripheral circuit unit 62 of the solid-state imaging device 1 according to the present embodiment. The peripheral circuit section 62 is a portion where the above-described peripheral circuits (specifically, the timing generator circuit 3, the vertical scanning circuit 4, the horizontal scanning circuit 5, the CDS circuit 6, and the digital output circuit 7) are arranged. .

  Although the configuration of the pixel unit 2 including the predetermined number of pixels 11 is as described above, only the layers 51, 52, and 53 are shown in FIG. 6, and the other elements of the pixel unit 2 are not shown. An N-type diffusion unit 71 is disposed around the pixel unit 2. The N type diffusion portion 71 is formed by diffusing impurities into the P type epitaxial layer 53. By the N-type diffusion portion 71, the region 53 a of the pixel portion 2 in the epitaxial layer 53 is electrically separated from the region 53 b of the peripheral circuit portion 62 in the epitaxial layer 53. Further, the N-type diffusion portion 71 is diffused so as to reach the N-type epitaxial layer 52 and is electrically connected to the N-type epitaxial layer 52.

  Thereby, the region 53a of the pixel portion 2 in the P-type epitaxial layer 53 is a part of the P-type epitaxial layer 53, but has a structure similar to the P-type well structure. A constant power source (constant potential) is applied to the N-type diffusion unit 71. For this reason, a constant power source is applied to the N-type epitaxial layer 52 via the N-type diffusion portion 71, and the electrons that have reached here are discharged.

  On the other hand, the peripheral circuit portion 62 is electrically separated from the P-type epitaxial layer 53 by the P-type well 72, the N-type well 73, and the N-type well 73 in the region 53b of the P-type epitaxial layer 53, as shown in FIG. And a P-type well 72 provided therein. A CMOS circuit is used as the peripheral circuit, and has a plurality of CMOS transistors (not shown in FIG. 6) as semiconductor elements constituting the peripheral circuit. For this reason, a large number of well structures as described above are provided. As described above, a plurality of semiconductor elements constituting the peripheral circuit are formed in the region 53 b of the peripheral circuit portion 62 in the P-type epitaxial layer 53.

  A region of the peripheral circuit portion 62 in the N-type epitaxial layer 52 is formed as a buried P-type layer 75 by impurity diffusion by ion implantation. Therefore, the buried P-type layer 75 is disposed on the P-type silicon substrate 51 so as to be continuous with the N-type epitaxial layer 52, and the layers 52 and 75 are layers formed by simultaneous epitaxial growth. . By the embedded P-type layer 75, the P-type epitaxial layer 53 and the P-type silicon substrate 51 are electrically connected. Thereby, a potential can be supplied to the P-type epitaxial layer 53 from the P-type silicon substrate 51 side.

  In FIG. 6, for simplicity, the thickness of the N-type epitaxial layer 52 is the same as that of the buried P-type layer 75, and the positions of the upper and lower surfaces are shown to coincide. However, actually, the thickness of the buried P-type layer 75 is thicker. The reason is that the buried P-type layer 75 is formed to have a high concentration and a thick thickness in order to reliably invert the P-type and connect the P-type epitaxial layer 53 and the P-type substrate 51.

  Further, in the present embodiment, the region 53 b of the peripheral circuit portion 62 in the P-type epitaxial layer 53 is not part of it but substantially the entire surface, and is electrically connected to the P-type silicon substrate 51 via the buried P-type layer 75. It is connected to the. For this reason, the potential of the region 53b of the peripheral circuit portion 62 in the P-type epitaxial layer 53 can be made substantially uniform over the entire surface, and accordingly, the operation and characteristics of an element such as a CMOS disposed in the region 53a. Can be made uniform.

  When the potential is applied to the region 53a of the P-type epitaxial layer 53 from the P-type silicon substrate 51 side in this way, the impurity concentration is set such that P-type silicon substrate 51> P-type well 72> P-type epitaxial layer 53. Is preferred. The reason why the impurity concentration of the P-type silicon substrate 51 is increased is to reduce its resistance so that the entire surface can be uniformly applied. The reason why the concentration of the P-type epitaxial layer 53 is lowered is to increase the breakdown voltage with the P-type well 72.

In the present embodiment, for example, the impurity concentration of the P-type silicon substrate 51 is about 1 × 10 ¹⁹ / cm ³ , the impurity concentration of the N-type epitaxial layer 52 is about 1 × 10 ¹⁷ / cm ³ , and the P-type epitaxial layer 53 is. Can be about 1 × 10 ¹⁶ / cm ³ , the impurity concentration of the charge storage layer 55 can be about 1 × 10 ¹⁷ / cm ³ , and the impurity concentration of the depletion prevention layer 54 can be about 1 × 10 ¹⁸ / cm ³ .

  By the way, in the peripheral circuit section 62, the timing generator circuit 3 and the digital output circuit 7 are not disposed, and only the horizontal scanning circuit 5 and the vertical scanning circuit 4 are disposed, as in the CMOS or the like in the peripheral circuit section 62. The embedded P-type layer 75 is not necessarily required if the operation and characteristics of the device of FIG.

  FIG. 7 shows an example in which the first embodiment is modified so that the buried P-type layer 75 is not provided. FIG. 7 is a conceptual cross-sectional view corresponding to FIG. In this case, the region 53 b of the peripheral circuit portion 62 in the epitaxial layer 53 is also disposed on the N-type epitaxial layer 52. In this modification, the potential is supplied to the region 53b of the P-type epitaxial layer 53 through an upper wiring (not shown).

  [Second Embodiment]

  FIG. 8 is a schematic cross-sectional view showing a part of the pixel portion of the solid-state imaging device according to the second embodiment of the present invention, and corresponds to FIG. FIG. 9 is a diagram showing an impurity concentration profile and potential in the depth direction of the photoelectric conversion unit of the solid-state imaging device according to the present embodiment, and corresponds to FIG. FIG. 10 is a conceptual cross-sectional view showing the pixel unit 2 and the peripheral circuit unit 62 of the solid-state imaging device according to the present embodiment, and corresponds to FIG. 8 to 10, the same or corresponding elements as those in FIGS. 4 to 6 are denoted by the same reference numerals, and redundant description thereof is omitted.

  The solid-state imaging device according to the present embodiment differs from the solid-state imaging device 1 according to the first embodiment in that a P-type epitaxial layer 81 is disposed between a P-type silicon substrate 51 and an N-type epitaxial layer 52. It is only a point.

  The impurity concentration of the P-type silicon substrate 51 is relatively high. The impurity concentration of the N type epitaxial layer 52 is set lower than the impurity concentration of the P type silicon substrate 51. This is because if the impurity concentration of the N-type epitaxial layer 52 is too high, the impurities of the N-type epitaxial layer 52 are re-diffused into the P-type epitaxial layer 53 when the P-type epitaxial layer 53 is formed, and photoelectric conversion is performed. This is because the sensitivity of the portion 13 decreases or varies. These points are the same in both the first and second embodiments.

  Therefore, when the N-type epitaxial layer 52 is formed directly on the P-type silicon substrate 51 as in the first embodiment, when the N-type epitaxial layer 52 is formed, impurities in the P-type silicon substrate 51 are N. Re-diffusion into the type epitaxial layer 52 occurs. As a result, it is conceivable that the concentration of the N-type impurity in the N-type epitaxial layer 52 changes from the design value, or the substantial film thickness of the N-type epitaxial layer 52 becomes thinner than the design value.

  When this occurs, the resistance value of the N-type epitaxial layer 52 also increases, and the potential of the N-type epitaxial layer 52 changes accordingly. Further, along with this, the potential of the P-type epitaxial layer 53 changes, thereby affecting the photoelectric conversion characteristics of the photoelectric conversion unit 13 and other elements arranged in the pixel 11. In addition, the effect of reducing crosstalk between pixels is also affected.

  Therefore, in order to avoid such an inconvenience, in the first embodiment, the N-type epitaxial layer 52 is made relatively thick.

  On the other hand, in the present embodiment, since the P-type epitaxial layer 81 is provided between the P-type silicon substrate 51 and the N-type epitaxial layer 52, re-diffusion of impurities from the P-type silicon substrate 51. Is absorbed by the P-type epitaxial layer 81, and the above-described disadvantages are prevented. For this reason, in the present embodiment, the N-type epitaxial layer 52 may be formed relatively thin.

In the present embodiment, for example, the impurity concentration of the P-type silicon substrate 51 is about 1 × 10 ¹⁹ / cm ³ , the impurity concentration of the P-type epitaxial layer 81 is about 1 × 10 ¹⁷ / cm ³ , and the N-type epitaxial layer 52 is, for example. Is about 1 × 10 ¹⁷ / cm ³ , the P-type epitaxial layer 53 is about 1 × 10 ¹⁶ / cm ³ , the impurity concentration of the charge storage layer 55 is about 1 × 10 ¹⁷ / cm ³ , and the depletion prevention layer 54 The impurity concentration of can be about 1 × 10 ¹⁸ / cm ³ .

  As can be understood from FIG. 9, according to the present embodiment in which the P-type epitaxial layer 81 is arranged, the crosstalk between pixels can be further reduced as in the first embodiment.

  As can be seen from FIG. 10, even if the P-type epitaxial layer 81 is disposed, the peripheral circuit portion 62 can be formed in the same manner as in the first embodiment.

  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments.

1 is a schematic configuration diagram illustrating an overall configuration of a solid-state imaging device according to a first embodiment of the present invention. It is a circuit diagram which shows a part of solid-state imaging device shown in FIG. FIG. 3 is a schematic plan view schematically showing 2 × 2 pixels of the solid-state imaging device shown in FIG. It is a schematic sectional drawing in the A-A 'part in FIG. It is a figure which shows the impurity concentration profile and potential of the depth direction of the photoelectric conversion part of the solid-state imaging device shown in FIG. FIG. 2 is a cross-sectional conceptual diagram showing a pixel portion and a peripheral circuit portion of the solid-state imaging device shown in FIG. 1. It is a section conceptual diagram showing the example which changed the solid-state image sensing device by the 1st embodiment. It is a schematic sectional drawing which shows a part of pixel part of the solid-state imaging device by the 2nd Embodiment of this invention. It is a figure which shows the impurity concentration profile and potential of the depth direction of the photoelectric conversion part of the solid-state imaging device by the 2nd Embodiment of this invention. It is a cross-sectional conceptual diagram which shows the pixel part and peripheral circuit part of the solid-state imaging device by the 2nd Embodiment of this invention. It is sectional drawing which shows typically the principal part of the pixel of the conventional solid-state imaging device. It is a figure which shows the impurity concentration profile of the depth direction of the photodiode part of the pixel shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Solid-state imaging device 2 Pixel part 4 Vertical scanning circuit 5 Horizontal scanning circuit 7 Digital output circuit 11 Pixel 13 Photoelectric conversion part 51 P-type silicon substrate (1st semiconductor layer)
52 N-type epitaxial layer (second semiconductor layer)
53 P-type epitaxial layer (third semiconductor layer)
55 Charge Storage Unit 62 Peripheral Circuit Unit 75 Buried P-type Layer (Fourth Semiconductor Layer)
81 P-type epitaxial layer (fifth semiconductor layer)

Claims (10)

A first semiconductor layer of a first conductivity type;
A second semiconductor layer of a second conductivity type disposed on the first semiconductor layer;
A third semiconductor layer of the first conductivity type disposed on the second semiconductor layer;
A plurality of pixels, wherein each pixel is disposed in a region of the third semiconductor layer on the second semiconductor layer and accumulates charges photoelectrically converted according to incident light; A plurality of pixels that output an analog signal corresponding to the charge,
A solid-state imaging device comprising:   The first semiconductor layer is a substrate layer, the second semiconductor layer is a layer formed by epitaxial growth, and the third semiconductor layer is a layer formed by epitaxial growth. Solid-state imaging device. A circuit related to the operation of the plurality of pixels;
A fourth semiconductor layer disposed on the first semiconductor layer so as to be continuous with the second semiconductor layer;
With
The third semiconductor layer is formed not only on the second semiconductor layer but also on the fourth semiconductor layer,
The solid-state imaging device according to claim 1, wherein a plurality of semiconductor elements constituting the circuit are arranged in a region on the fourth semiconductor layer in the third semiconductor layer.   4. The solid-state imaging device according to claim 3, wherein each of the second semiconductor layer and the fourth semiconductor layer is a layer formed by simultaneous epitaxial growth. The conductivity type of the fourth semiconductor layer is the first conductivity type;
5. The solid-state imaging device according to claim 3, wherein the third semiconductor layer is electrically connected to the first semiconductor layer through the fourth semiconductor layer. A circuit related to the operation of the plurality of pixels;
The solid-state imaging device according to claim 1, wherein a plurality of semiconductor elements constituting the circuit are arranged in a region on the second semiconductor layer in the third semiconductor layer.   The region of the third semiconductor layer in which the charge storage portions of the plurality of pixels are disposed is electrically separated from the region of the third semiconductor layer in which the plurality of semiconductor elements are disposed. The solid-state imaging device according to claim 3, wherein:   8. The solid-state imaging device according to claim 3, wherein an impurity concentration of the third semiconductor layer is lower than an impurity concentration of the first semiconductor layer.   9. The signal processing circuit according to claim 3, wherein the circuit includes a signal processing circuit that processes the analog signals output from the plurality of pixels and outputs a digital signal corresponding to the analog signals to the outside. The solid-state imaging device described in 1.   The fifth semiconductor layer of the first conductivity type formed by epitaxial growth and having an impurity concentration lower than that of the first semiconductor layer is disposed between the first semiconductor layer and the second semiconductor layer. The solid-state imaging device according to claim 1.

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