JP4810806B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device used as various image sensors and camera modules.

  When the image sensor is irradiated with excessive light, an excessive charge is generated in the photodiode and leaks to the adjacent photodiode, whereby a signal that does not exist in the original subject is imaged. This phenomenon is generally called blooming.

  As a means for suppressing blooming, a vertical overflow drain (VOD) structure is known. FIG. 7 is a cross-sectional view showing a VOD structure.

  A p-type overflow barrier region 104 is formed between the photodiode 103 made of an n-type region formed in the p-type region 102 in the n-type semiconductor substrate 101 and the n-type semiconductor substrate 101. The p-type overflow barrier region 104 has a p-type impurity concentration defined such that the potential barrier against electrons is lower (potential is higher) than the p-type region 102 surrounding the photodiode 103.

  In the above structure, a high reverse bias voltage is applied between the p-type region 102 and the n-type semiconductor substrate 101. When strong light L enters the photodiode 103, the surplus charge of the photodiode 103 passes over the p-type region 102 and does not leak to the adjacent pixel, but is discarded to the n-type semiconductor substrate 101 through the overflow barrier region 104. It is done.

  The problem with this VOD structure is that it is difficult to form with a general CMOS process because it is necessary to control the impurity concentration of the overflow barrier region 104, which is a relatively deep region. Moreover, the difficulty of the controllability affects the yield as a device. Furthermore, it is necessary to apply a relatively high voltage to the n-type semiconductor substrate 101.

  As another means for suppressing blooming, a lateral overflow drain (LOD) structure is known. FIG. 8 is a cross-sectional view showing the LOD structure.

  An n-type overflow drain region 113 is formed so as to be adjacent to the n-type photodiode 112 formed in the p-type region 111 in a planar manner, and between the photodiode 112 and the overflow drain region 113. A p-type overflow barrier region 114 is formed. The p-type overflow barrier region 114 has a p-type impurity concentration defined such that the potential barrier against electrons is lower (potential is higher) than the p-type region 111 surrounding the photodiode 112.

  In the above structure, when strong light L enters the photodiode 112, the surplus charge of the photodiode 112 does not get over the p-type region 111 and leak to the adjacent pixel, and passes through the overflow barrier region 114 and overflow drain region 113. It is thrown away.

  The problem with this LOD structure is that the area ratio of the photodiode 112 occupying in the pixel decreases because the area is divided by the overflow drain region 113 and the overflow barrier region 114.

  The VOD structure and LOD structure described above are structures mainly employed in CCD type solid-state imaging devices. On the other hand, FIG. 9 shows an overflow drain structure employed in the MOS type solid-state imaging device.

  An n-type floating diffusion 123 is formed so as to be adjacent to the n-type photodiode 122 formed in the p-type region 121 in a plan view. Further, between the photodiode 122 and the floating diffusion 123, a gate electrode 124 of the transistor and a p-type overflow barrier region 125 serving as a channel are formed. The p-type overflow barrier region 125 has a p-type impurity concentration defined such that the potential barrier against electrons is lower (potential is higher) than the p-type region 121 surrounding the photodiode 121.

  In the above structure, when strong light L enters the photodiode 122, the surplus charges of the photodiode 122 do not get over the p-type region 121 and leak to the adjacent pixels, and pass through the overflow barrier region 125 to the floating diffusion 123. It is thrown away. When reading the charge, a voltage is applied to the gate electrode 124, and the charge in the photodiode 122 is read to the floating diffusion 123 and converted into a voltage corresponding to the amount of charge.

  The problem with the overflow drain structure is that the area ratio of the photodiode 122 occupying the pixel is reduced because the area is divided by the floating diffusion 123 and the overflow barrier region 125. Furthermore, since the overflow barrier region 125 also serves as a channel of the transfer transistor, the potential barrier of the overflow barrier region 125 is lowered to discard excess charges, and the potential of the channel is prevented to prevent generation of dark current. There is a trade-off between raising barriers.

Generally, there are problems with the overflow drain structure as described above. In the above solid-state imaging device, light is received from the side on which the transistors and wirings are formed. For this reason, there are problems that the aperture ratio for light reception is reduced by the wiring, and the degree of freedom of the wiring layout is limited. In order to solve such a problem, a back-illuminated fixed imaging device is known in which wiring is formed on the front surface side of a semiconductor layer and light is incident from the back surface side of the semiconductor layer so that imaging can be performed. As back-illuminated solid-state imaging devices, a CCD type (for example, see Patent Document 1) and a MOS type (for example, see Patent Document 2) have been proposed.
JP 2002-151673 A JP 2003-31785 A

  The conventional VOD structure cannot be adopted for the above-described back-illuminated solid-state imaging device. In addition, since the LOD and the structure shown in FIG. 9 have a restriction that an overflow drain must be provided in a portion other than the photodiode, it conflicts with the demand for a backside illumination type solid-state imaging device that wants to make the entire back surface into a photodiode. Will be.

  The present invention has been made in view of the above circumstances, and the purpose thereof is particularly effective when employed in a back-illuminated solid-state imaging device, and without limiting the area of the photodiode. An object of the present invention is to provide a solid-state imaging device having a structure for discharging surplus charges.

In order to achieve the above object, a solid-state imaging device of the present invention has a pixel portion in which a plurality of unit pixels are arranged, and each unit pixel has a second conductivity type region on a first conductivity type substrate. A photodiode that is formed and generates a charge corresponding to the amount of incident light, stores the generated charge, and a plurality of transistors that are formed on the first surface side of the substrate and for reading the charge stored in the photodiode A plurality of read transistors including at least a transfer transistor, and the second conductivity type region of the photodiode and the first surface side are formed so as to overlap in plane, and the photodiode of the photodiode in the first surface side of the substrate at a region and spacing of the second conductivity type, the flow charge in the photodiode by the transfer transistor is transferred Said second conductivity type overflow drain region of which is made form the I ring diffusions, said second conductivity type region and the overflow drain region of the photodiode, with the same first conductivity type as the substrate And an overflow barrier region connected to a semiconductor region having a potential barrier lower than that of the substrate, and having a potential barrier capable of discharging surplus charges in the photodiode to the overflow drain region.
In addition, the solid-state imaging device of the present invention has a pixel portion in which a plurality of unit pixels are arranged, and each unit pixel has a second conductivity type region formed on the first conductivity type substrate, and the incident light amount is reduced. A photodiode that generates a corresponding charge and accumulates the generated charge, and a plurality of transistors that are formed on the first surface side of the substrate and for reading the charge accumulated in the photodiode, and at least transfer A plurality of read transistors including a transistor, an amplifying transistor for amplifying a potential of a floating diffusion to which a charge in the photodiode is transferred by the transfer transistor , the region of the second conductivity type of the photodiode, and the The first surface side is formed to overlap with the second surface, and between the second conductivity type region of the photodiode. In the first surface side of the substrate at a, and the second conductivity type overflow drain region of which is made form the drain region before Symbol amplification transistor, the second conductivity type region of the photodiode And the overflow drain region are connected by a semiconductor region having the same first conductivity type as that of the substrate and having a potential barrier lower than that of the substrate, and surplus charges in the photodiode are transferred to the overflow drain And an overflow barrier region having a potential barrier that can be discharged to the region.

  In the solid-state imaging device of the present invention described above, when light is incident on the substrate, photoelectric conversion is performed by the photodiode, and a charge corresponding to the amount of incident light is generated. The generated charge is accumulated in the photodiode. When intense light hits the photodiode and charges exceeding the limit that can be accumulated in the photodiode are generated, excess charge is discharged to the overflow drain region through the overflow barrier region. Since the overflow drain region from which the excess charge is discharged overlaps the photodiode in a planar manner, the area of the photodiode is not limited. In addition, since the overflow barrier region is formed on the first surface side, that is, in a shallow region from the photodiode, the potential control of the region is facilitated.

  According to the solid-state imaging device of the present invention, a structure for discharging surplus charges in the photodiode is provided without limiting the area of the photodiode. For this reason, the area of the photodiode can be increased, and a solid-state imaging device with reduced blooming can be provided.

  Embodiments of a solid-state imaging device of the present invention will be described below with reference to the drawings. In this embodiment, a backside illuminated CMOS image sensor will be described as an example.

(First embodiment)
FIG. 1 is a schematic configuration diagram of a solid-state imaging apparatus according to the present embodiment.

  The solid-state imaging device includes a pixel unit 11, a vertical selection circuit 12, an S / H (sample / hold) / CDS (Correlated Double Sampling) circuit 13, a horizontal selection circuit 14, and a timing generator (TG). ) 15, an AGC (Automatic Gain Control) circuit 16, an A / D conversion circuit 17, and a digital amplifier 18, which are mounted on the same semiconductor substrate.

  The pixel unit 11 has a configuration in which a large number of unit pixels, which will be described later, are arranged in a matrix, and address lines and the like are arranged in rows and vertical signal lines are arranged in columns.

  The vertical selection circuit 12 sequentially selects the pixels in units of rows, and reads the signal of each pixel to the S / H • CDS circuit 13 for each pixel column through the vertical signal line. The S / H • CDS circuit 13 performs signal processing such as CDS on the pixel signal read from each pixel column.

  The horizontal selection circuit 14 sequentially extracts the pixel signals held in the S / H • CDS circuit 13 and outputs them to the AGC circuit 16. The AGC circuit 16 amplifies the signal input from the horizontal selection circuit 14 with an appropriate gain and outputs the amplified signal to the A / D conversion circuit 17.

  The A / D conversion circuit 17 converts the analog signal input from the AGC circuit 16 into a digital signal and outputs the digital signal to the digital amplifier 18. The digital amplifier 18 appropriately amplifies the digital signal input from the A / D conversion circuit 17 and outputs it from the output terminal.

  The operations of the vertical selection circuit 12, the S / H / CDS circuit 13, the horizontal selection circuit 14, the AGC circuit 16, the A / D conversion circuit 17, and the digital amplifier 18 are based on various timing signals generated by the timing generator 15. Done.

  FIG. 2 is a diagram illustrating an example of a circuit configuration of a unit pixel of the pixel unit 11.

  The unit pixel includes, for example, a photodiode 21 as a photoelectric conversion element, and four readout transistors, that is, a transfer transistor 22, an amplification transistor 23, an address transistor 24, and a reset transistor 25, with respect to the one photodiode 21. As an active element.

  The photodiode 21 photoelectrically converts incident light into charges (here, electrons) in an amount corresponding to the amount of light. The transfer transistor 22 is connected between the photodiode 21 and the floating diffusion FD, and when a drive signal is given to the gate through the drive wiring 26, the electrons photoelectrically converted by the photodiode 21 are transferred to the floating diffusion FD. .

The gate electrode 32 of the amplification transistor 23 is connected to the floating diffusion FD. The amplification transistor 23 is connected to the vertical signal line 27 via the address transistor 24, and constitutes a constant current source I and a source follower outside the pixel portion. When an address signal is applied to the gate of the address transistor 24 through the drive wiring 28 and the address transistor 24 is turned on, the amplifying transistor 23 amplifies the potential of the floating diffusion FD and applies a voltage corresponding to the potential to the vertical signal line 27. Output to. The vertical signal line 27 transmits the voltage output from each pixel to the S / H • CDS circuit 13.

  The reset transistor 25 is connected between the power supply Vdd and the floating diffusion FD, and resets the potential of the floating diffusion FD to the potential of the power supply Vdd when a reset signal is given to the gate through the drive wiring 29. These operations are simultaneously performed for each pixel of one row because the gates of the transfer transistor 22, the address transistor 24, and the reset transistor 25 are wired in units of rows.

  FIG. 3 is a schematic cross-sectional view of the pixel unit 11 of the solid-state imaging device.

  In the semiconductor substrate 30, a plurality of photodiodes 21 constituting unit pixels in the pixel portion 11 are formed and arranged. The semiconductor substrate 30 is composed of, for example, a p-type silicon epitaxial substrate, and the photodiode 21 is composed of an n-type region formed on the substrate. The thickness of the semiconductor substrate 30 depends on the specifications of the solid-state imaging device, but is 4 to 6 μm for visible light and 6 to 10 μm for near infrared.

  The gate electrodes 31 and 32 of the transistor described with reference to FIG. 2 are formed on the surface (first surface) opposite to the surface on which the light L is incident on the semiconductor substrate 30. Note that in regions other than the pixel portion, elements such as transistors constituting the circuits 12 to 18 are formed on the first surface of the semiconductor substrate 30.

  A wiring layer 40 is formed on the first surface of the semiconductor substrate 30. In FIG. 3, a three-layer wiring is illustrated, and the wiring layer 40 includes a wiring 42 embedded in an interlayer insulating film 41. Each wiring 42 corresponds to the driving wiring 26, 28, 29 and the vertical signal line 27 in FIG. 2, respectively.

  A support substrate 50 for reinforcing the strength of the semiconductor substrate 30 is formed on the wiring layer 40. The support substrate 50 is made of, for example, the same silicon as the semiconductor substrate 30 in order to prevent warpage due to a difference in thermal expansion coefficient from the semiconductor substrate 30.

  On the other surface of the semiconductor substrate 30, that is, the light incident surface (second surface), an insulating film 61 made of, for example, a silicon oxide film is formed. A light shielding film 62 made of, for example, aluminum or copper is formed on the insulating film 61. An opening 62 a is formed in the light shielding film 62 so that light can enter the photodiode 21 of the pixel.

  A passivation film 63 made of, for example, a silicon nitride film is formed on the insulating film 61 so as to cover the light shielding film 62. A color filter 64 and an on-chip lens 65 are formed on the passivation film 63.

  FIG. 4 is a cross-sectional view showing an example of the structure of the semiconductor substrate 30. In FIG. 4, the top and bottom are inverted from FIG. 3.

The n-type photodiode 21 is formed on the p-type semiconductor substrate 30. The gate electrode 31 is formed so that the light receiving area increases as going to the light incident surface. The n-type impurity concentration of the photodiode 21 is, for example, about 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁶ cm ⁻³ . The depth d1 of the photodiode 21 is, for example, about 3 to 9 μm, depending on the specifications of the solid-state imaging device.

  On the first surface of the semiconductor substrate 30, the gate electrode 31 of the transfer transistor 22 and the gate electrode 32 of the amplification transistor 23 are formed. Further, an n-type floating diffusion 33, an n-type drain region 34 and an n-type source region 35 of the gate electrode 32 are formed on the first surface side of the photodiode 21 so as to overlap with the photodiode 21 in a plan view. Has been. Thus, in this embodiment, in order to maximize the area of the photodiode 21, the photodiode 21 is formed so as to overlap with the transistors 22 and 23 in plan view.

A p-type overflow barrier region 36 is formed between the floating diffusion 33 and the photodiode 21. The p-type overflow barrier region 36 has a p-type impurity concentration defined such that the potential barrier against electrons is lower (potential is higher) than the p-type semiconductor substrate 30 surrounding the photodiode 21. That is, the p-type impurity concentration of the overflow barrier region 36 is lower than the p-type impurity concentration of the semiconductor substrate 30. For example, the p-type impurity concentration of the semiconductor substrate 30 is 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁵ cm ⁻³ , and the p-type impurity concentration of the overflow barrier region 36 is 1 × 10 ¹⁴ cm ⁻ lower than this. ³ or less. Rather, it may be very thin and inverted to n-type.

  The depth d2 of various semiconductor regions formed so as to overlap the photodiode 21 in a plane, that is, the floating diffusion 33, the drain region 34, and the source region 35 is, for example, 0.5 μm. The impurity profile of the photodiode 21 is controlled so that these regions 33, 34, 35 and the photodiode 21 do not overlap in section. For example, the distance d3 between these regions 33, 34, and 35 and the photodiode 21 is 0.3 μm or more. The interval d3 corresponds to the depth of the overflow barrier region 36.

  The operation of the solid-state imaging device will be described.

  As shown in FIG. 3, the incident light L is collected by the on-chip lens 65 and enters the color filter 64. In the color filter 64, only light in a desired wavelength region passes. The light that has passed through the color filter 64 enters the photodiode 21 formed on the semiconductor substrate 30 through the opening 62 a of the light shielding film 62.

  As shown in FIG. 4, the light L incident on the photodiode 21 of the semiconductor substrate 30 is photoelectrically converted by the photodiode 21, and charges (here, electrons) corresponding to the amount of incident light are generated. The generated light is accumulated in the photodiode 21 for a certain period.

  Here, when strong light is incident on the photodiode 21, charges exceeding the limit that can be accumulated in the photodiode 21 are generated. However, surplus charges do not leak to adjacent pixels, and the potential barrier is higher than that of the semiconductor substrate 30. Through the low overflow barrier region 36 and is discarded into the floating diffusion 33.

For example, during a period other than the charge reading, the reset transistor 25 is always turned on, and the floating diffusion FD is caused to function as an overflow drain. At the time of reading, first, the reset transistor 25 is turned off to complete the reset. Thereafter, a drive signal is given to the gate electrode 31 of the transfer transistor 22, and the electrons photoelectrically converted by the photodiode 21 are transferred to the floating diffusion 33 (FD).

  When electrons are transferred to the floating diffusion 33 (FD), an address signal is applied to the gate of the address transistor 24 through the drive wiring 28, and the address transistor 24 is turned on (see FIG. 2). Then, the potential of the floating diffusion 33 (FD) is amplified by the amplification transistor 23, and a voltage corresponding to the potential is output to the vertical signal line 27.

  As described above, according to the solid-state imaging device according to the present embodiment, the floating diffusion 33 having a planar overlap with the photodiode 21 is formed, and the floating diffusion 33 is overflowed to discard excess charges. By using it as the drain region, the area of the photodiode 21 occupying the pixel is not reduced. For this reason, the area of the photodiode 21 can be increased and blooming can be suppressed.

  Further, since the floating diffusion 33 is used as the overflow drain region, the charge discarding function can be realized only by providing the overflow barrier region 36 immediately below the floating diffusion 33. That is, no extra element is formed for the charge discarding function.

  Further, since the overflow barrier region 36 is formed immediately below the floating diffusion 33, the impurity concentration of the overflow barrier region 36 can be controlled by a general CMOS process. That is, since ion implantation or the like is performed from the surface (first surface) opposite to the light incident surface of the semiconductor substrate 30, it is not necessary to implant ions into a deep region, and a stable overflow barrier region 36 can be formed. .

  In particular, in the backside illumination type solid-state imaging device in which elements such as transistors are formed on the first surface side of the semiconductor substrate 30 and light is incident from the second surface side as in this embodiment, the aperture ratio of the back surface is remarkably high. There are advantages you can do. The overflow function can be operated with a general power supply voltage Vdd (about 3.3 V) specified in a CMOS device.

(Second Embodiment)
In this embodiment, the drain region 34 of the amplification transistor 23 is used as the overflow drain region. The description of FIGS. 1 to 3 is similarly applied to the present embodiment.

  FIG. 5 is a cross-sectional view showing an example of the structure of the semiconductor substrate 30 according to the present embodiment. In addition, the same code | symbol is attached | subjected to the component similar to 1st Embodiment, The description is abbreviate | omitted.

  In the present embodiment, a p-type overflow barrier region 36 is formed between the drain region 34 of the amplification transistor 23 and the photodiode 21. In the p-type overflow barrier region 36, the p-type impurity concentration is defined so that the potential barrier against electrons is lower (potential is higher) than the p-type semiconductor substrate 30 surrounding the photodiode 21. This is the same as in the first embodiment.

  As described above, in this embodiment, the drain region 34 of the amplification transistor 23 is used as an overflow drain region. As described with reference to FIG. 2, the terminal (drain region 34) of the amplification transistor 23 is fixed to the potential of the power supply Vdd.

  The depth d1 of the photodiode 21, the depth d2 of the various regions 33, 34, and 35, and the distance d3 between these regions 33, 34, and 35 and the photodiode 21 are the same as in the first embodiment. .

  The operation of the solid-state imaging device will be described.

  As shown in FIG. 3, the incident light L is collected by the on-chip lens 65 and enters the color filter 64. In the color filter 64, only light in a desired wavelength region passes. The light that has passed through the color filter 64 enters the photodiode 21 formed on the semiconductor substrate 30 through the opening 62 a of the light shielding film 62.

  As shown in FIG. 5, the light L incident on the photodiode 21 of the semiconductor substrate 30 is photoelectrically converted by the photodiode 21 to generate charges (electrons here) corresponding to the amount of incident light. The generated light is accumulated in the photodiode 21 for a certain period.

  Here, when strong light is incident on the photodiode 21, charges exceeding the limit that can be accumulated in the photodiode 21 are generated. However, surplus charges do not leak to adjacent pixels, and the potential barrier is higher than that of the semiconductor substrate 30. Through the low overflow barrier region 36 and drained into the drain region 34.

  When reading out electric charges, a drive signal is given to the gate electrode 31 of the transfer transistor 22, and the electrons photoelectrically converted by the photodiode 21 are transferred to the floating diffusion 33 (FD).

  When electrons are transferred to the floating diffusion 33 (FD), an address signal is applied to the gate of the address transistor 24 through the drive wiring 28, and the address transistor 24 is turned on (see FIG. 2). Then, the potential of the floating diffusion 33 (FD) is amplified by the amplification transistor 23, and a voltage corresponding to the potential is output to the vertical signal line 27.

  As described above, the same effect as that of the first embodiment can be obtained by the solid-state imaging device according to this embodiment.

(Third embodiment)
In this embodiment, the drain region of the transistor constituting the pixel is not used, but an overflow drain region composed of an n-type region is provided separately. The description of FIGS. 1 to 3 is similarly applied to the present embodiment.

  FIG. 6 is a cross-sectional view showing an example of the structure of the semiconductor substrate 30 according to this embodiment. In addition, the same code | symbol is attached | subjected to the component similar to 1st Embodiment, The description is abbreviate | omitted.

  In addition to the n-type floating diffusion 33, an n-type overflow drain region 37 is formed on the first surface side of the photodiode 21 so as to overlap with the photodiode 21 formed on the semiconductor substrate 30 in plan view. The overflow drain region 37 is fixed at the potential of the power supply Vdd. Although not shown, a source region and a drain region of the amplification transistor 23 are also formed.

  A p-type overflow barrier region 36 is formed between the overflow drain region 37 and the photodiode 21. In the p-type overflow barrier region 36, the p-type impurity concentration is defined so that the potential barrier against electrons is lower (potential is higher) than the p-type semiconductor substrate 30 surrounding the photodiode 21. This is the same as in the first embodiment.

  The depths d2 of various regions formed so as to overlap the photodiode 21 in a plane, that is, the floating diffusion 33 and the overflow drain region 37 are, for example, 0.5 μm. The distance d3 between these regions 33 and 37 and the photodiode 21 is the same as that in the first embodiment.

  The operation of the solid-state imaging device will be described.

  As shown in FIG. 3, the incident light L is collected by the on-chip lens 65 and enters the color filter 64. In the color filter 64, only light in a desired wavelength region passes. The light that has passed through the color filter 64 enters the photodiode 21 formed on the semiconductor substrate 30 through the opening 62 a of the light shielding film 62.

  As shown in FIG. 6, the light L incident on the photodiode 21 of the semiconductor substrate 30 is photoelectrically converted by the photodiode 21, and charges (here, electrons) corresponding to the amount of incident light are generated. The generated light is accumulated in the photodiode 21 for a certain period.

  Here, when strong light is incident on the photodiode 21, charges exceeding the limit that can be accumulated in the photodiode 21 are generated. However, surplus charges do not leak to adjacent pixels, and the potential barrier is higher than that of the semiconductor substrate 30. The overflow drain region 37 is discarded through the low overflow barrier region 36.

  When reading out electric charges, a drive signal is given to the gate electrode 31 of the transfer transistor 22, and the electrons photoelectrically converted by the photodiode 21 are transferred to the floating diffusion 33 (FD).

  When electrons are transferred to the floating diffusion 33 (FD), an address signal is applied to the gate of the address transistor 24 through the drive wiring 28, and the address transistor 24 is turned on (see FIG. 2). Then, the potential of the floating diffusion 33 (FD) is amplified by the amplification transistor 23, and a voltage corresponding to the potential is output to the vertical signal line 27.

  As described above, the same effect as that of the first embodiment can be obtained by the solid-state imaging device according to this embodiment. In the present embodiment, a separate overflow drain region 37 is provided, but the light receiving area of the photodiode 21 is not limited because it is arranged so as to overlap the photodiode 21 in a plan view.

The present invention is not limited to the description of the above embodiment.
For example, in the second embodiment, the example in which the drain region 34 of the amplifying transistor 23 is used as the overflow drain region among the transistors configuring the pixel has been described. It is also possible to use the drain region of this transistor or an n-type region other than the transistor.

  In this embodiment, an example in which electrons are used as signal charges has been described. However, when holes are used, the polarities of various regions are reversed. For example, the photodiode 21, the floating diffusion 33, the drain region 34, and the overflow drain region 37 are p-type, and the semiconductor substrate 30 and the overflow barrier region 36 are n-type. In this case, the n-type impurity concentration of the overflow barrier region 36 is defined so that the potential barrier against holes is lower (potential is lower) than the n-type semiconductor substrate 30 surrounding the photodiode 21. The overflow drain region 37 and the drain region 34 used as the overflow drain region are fixed to the ground potential. The floating diffusion 33 used as the overflow drain region is reset to the ground potential.

  In addition, various modifications can be made without departing from the scope of the present invention.

It is a schematic block diagram of the solid-state imaging device concerning this embodiment. It is a figure which shows an example of the circuit structure of the unit pixel of a pixel part. It is a schematic sectional drawing of the pixel part of a solid-state imaging device. It is sectional drawing which shows an example of the structure of the semiconductor substrate which concerns on 1st Embodiment. It is sectional drawing which shows an example of the structure of the semiconductor substrate which concerns on 2nd Embodiment. It is sectional drawing which shows an example of the structure of the semiconductor substrate which concerns on 3rd Embodiment. It is sectional drawing which shows the conventional VOD structure. It is sectional drawing which shows the conventional LOD structure. It is sectional drawing which shows the overflow drain structure employ | adopted with the conventional MOS type solid-state imaging device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Pixel part, 12 ... Vertical selection circuit, 13 ... S / H / CDS circuit, 14 ... Horizontal selection circuit, 15 ... Timing generator, 16 ... AGC circuit, 17 ... A / D conversion circuit, 18 ... Digital amplifier, 21 DESCRIPTION OF SYMBOLS ... Photodiode, 22 ... Transfer transistor, 23 ... Amplification transistor, 24 ... Address transistor, 25 ... Reset transistor, 26, 28, 29 ... Drive wiring, 27 ... Vertical signal line, 30 ... Semiconductor substrate, 31 ... Gate electrode, 32 DESCRIPTION OF SYMBOLS ... Gate electrode, 33 ... Floating diffusion, 34 ... Drain region, 35 ... Source region, 36 ... Overflow barrier region, 37 ... Overflow drain region, 40 ... Wiring layer, 41 ... Interlayer insulating film, 42 ... Wiring, 50 ... Support substrate 61 ... Insulating film, 62 ... Light shielding film, 62a ... Opening, 63 ... Passivation Membrane, 64 ... color filter, 65 ... on-chip lens, 101 ... n-type semiconductor substrate, 102 ... p-type region, 103 ... photodiode, 104 ... overflow barrier region, 111 ... p-type region, 112 ... photodiode, 113 ... Overflow drain region, 114 ... overflow barrier region, 121 ... p-type region, 122 ... photodiode, 123 ... floating diffusion, 124 ... gate electrode, 125 ... overflow barrier region

Claims (13)

While having a pixel portion in which a plurality of unit pixels are arranged,
Each unit pixel is
A photodiode having a second conductivity type region formed on the first conductivity type substrate, generating a charge corresponding to the amount of incident light, and storing the generated charge;
A plurality of transistors for reading charges formed on the first surface side of the substrate and accumulated by the photodiodes, and a plurality of transistors for reading including at least a transfer transistor ;
The first conductivity type region of the photodiode is formed to overlap the second conductivity type region of the photodiode on the first surface side, and is spaced apart from the second conductivity type region of the photodiode. in the surface side, and the second conductivity type overflow drain region of charge in the photodiode is made form the floating diffusion which is transferred by the transfer transistor,
The region of the second conductivity type of the photodiode and the overflow drain region are connected by a semiconductor region having the same first conductivity type as the substrate and having a potential barrier lower than the potential barrier of the substrate. And an overflow barrier region having a potential barrier capable of discharging surplus charges in the photodiode to the overflow drain region. The solid-state imaging device according to claim 1, wherein light is irradiated to the photodiode from the second surface side of the substrate. The solid-state imaging device according to claim 2, wherein the photodiode is formed so that a light receiving area increases from the first surface side toward the second surface side. The solid-state imaging device according to claim 3, wherein the photodiode is formed so as to overlap with at least the transfer transistor in a planar manner among the plurality of readout transistors. The solid-state imaging device according to claim 1, wherein the first conductivity type substrate is formed of a P-type semiconductor, and the second conductivity type region is formed of an N-type semiconductor. 6. The P-type impurity concentration of the substrate is 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁵ cm ⁻³ , and the P-type impurity concentration of the overflow barrier region is 1 × 10 ¹⁴ cm ⁻³ or less. The solid-state imaging device described. The solid-state imaging device according to claim 6, wherein the overflow barrier region is inverted to an N type. The plurality of read transistors further include an amplification transistor,
Wherein as the transfer transistor and the amplifier transistor and said photodiode are not overlapped in the cross-sectionally, claim opening said drain region and the source region of the floating diffusion and the amplifying transistor, an interval more than a predetermined distance between the photodiode The solid-state imaging device according to 1. The solid-state imaging device according to claim 1, wherein the overflow barrier region is formed by ion implantation from the first surface side. The solid-state imaging device according to claim 1, wherein a support substrate is formed on the wiring on the first surface side through an interlayer insulating film in order to reinforce the strength of the substrate. While having a pixel portion in which a plurality of unit pixels are arranged,
Each unit pixel is
A photodiode having a second conductivity type region formed on the first conductivity type substrate, generating a charge corresponding to the amount of incident light, and storing the generated charge;
A plurality of transistors for reading charges accumulated in the photodiode formed on the first surface side of the substrate , at least a transfer transistor, and a floating in which the charge in the photodiode is transferred by the transfer transistor A plurality of readout transistors including an amplification transistor for amplifying the potential of the diffusion ;
The first conductivity type region of the photodiode is formed to overlap the second conductivity type region of the photodiode on the first surface side, and is spaced apart from the second conductivity type region of the photodiode. in the surface side, and the second conductivity type overflow drain region of which is made form the drain region before Symbol amplification transistor,
The region of the second conductivity type of the photodiode and the overflow drain region are connected by a semiconductor region having the same first conductivity type as the substrate and having a potential barrier lower than the potential barrier of the substrate. And an overflow barrier region having a potential barrier capable of discharging surplus charges in the photodiode to the overflow drain region. The solid-state imaging device according to claim 11, wherein the photodiode is formed such that a light receiving area increases from the first surface side toward a second surface side irradiated with light from the substrate. The solid-state imaging device according to claim 11, wherein the photodiode is formed so as to overlap with at least the amplification transistor in a planar manner among the plurality of readout transistors .

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