JP2019029399A - Imaging apparatus - Google Patents

Abstract

To provide an imaging apparatus capable of reducing the possibility of occurrence of streaking more than before.SOLUTION: In an imaging apparatus 71 including a semiconductor substrate, and a pixel array 72 where pixels 14 are arranged in m rows and n columns (m, n are positive integers), each pixel 14 includes a photoelectric conversion part 10 located above the semiconductor substrate, and converting light into charges, the semiconductor substrate includes a first region 31B containing first conductivity type impurities, a second region 31A located above the first region 31B, and containing the first conductivity type impurities at a concentration lower than that of the first region 31B, and a charge storage region 44 located in the second region 31A, while containing second conductivity type impurities different from the first conductivity type, and storing charges, the pixel arrays 72 include a first pixel located at one end of the k row (k is n integer of 1-m), and a second pixel located at the other end of the k row, and the combined resistance between the charge storage region 44 of the first pixel and the charge storage region 44 of the second pixel is 1 kΩ or less.SELECTED DRAWING: Figure 10A

Description

  The present invention relates to an imaging apparatus.

  2. Description of the Related Art Conventionally, as described in Patent Document 1, for example, an imaging apparatus that captures an image is known.

Japanese Patent No. 5971565

  There is a need for an imaging device with reduced pixel output non-uniformity.

  An imaging device according to the present disclosure is an imaging device including a semiconductor substrate and a pixel array in which pixels are arranged in m rows and n columns (m and n are positive integers), and each of the pixels includes A photoelectric conversion unit is provided above the semiconductor substrate and converts light into electric charges. The semiconductor substrate is disposed above the first region, the first region containing a first conductivity type impurity, and the first region. A second region containing impurities of the first conductivity type at a concentration lower than one region; and a second conductivity type impurity located in the second region and different from the first conductivity type; A charge accumulation region for accumulation, wherein the pixel array includes a first pixel located at one end of k rows (k is an integer of 1 to m), a second pixel located at the other end of the k rows, The charge storage region of the first pixel; and the charge storage region of the second pixel; The combined resistance value between the is 1kΩ or less.

  In the present disclosure, an imaging apparatus with reduced pixel output non-uniformity is provided.

FIG. 1 is a schematic diagram showing an equivalent circuit of a pixel array. FIG. 2 is a block diagram showing an overall configuration of the imaging apparatus according to Embodiments 1 and 2. As shown in FIG. FIG. 3A is a cross-sectional view of the outer edge portion of the pixel array according to Embodiment 1 and its periphery. FIG. 3B is a plan view of the pixel array according to Embodiment 1 and its periphery. FIG. 4A is a cross-sectional view of pixels constituting the pixel array according to Embodiment 1. FIG. 4B is a plan view of pixels constituting the pixel array according to Embodiment 1. FIG. 5A is a schematic diagram showing the connection from the peripheral region to the external pad. FIG. 5B is a schematic diagram showing connections from the peripheral region to the external pads. FIG. 6 is a schematic diagram showing an equivalent circuit of substrate resistance when there is a connection region. FIG. 7A is a graph showing the relationship between the resistance of the connection region and the combined resistance. FIG. 7B is a graph showing the relationship between the resistivity of the support substrate and the combined resistance. FIG. 8 is a graph showing the relationship between the number of implantations and the impurity concentration in the impurity region. FIG. 9A is a cross-sectional view of the outer edge portion of the pixel array according to the second embodiment and the periphery thereof. FIG. 9B is a plan view of the pixel array according to Embodiment 2 and the periphery thereof. FIG. 10A is a cross-sectional view of the pixels constituting the pixel array according to Embodiment 2. FIG. 10B is a plan view of pixels constituting the pixel array according to Embodiment 2.

(Background to obtaining one embodiment of the present invention)
In recent years, high-definition imaging devices are required for applications such as single-lens reflex cameras, high-end compact cameras, and broadcast cameras. In such an imaging apparatus, the pixel size is generally 2 to 6 μm, and the number of pixels is generally about FHD (Full High Definition) to 8K4K.

  The inventor has discovered a problem that pixel output non-uniformity is likely to occur due to parasitic resistance and parasitic capacitance of a semiconductor substrate as the size of the imaging device increases while developing the imaging device.

  Then, as a result of trial manufacture to solve the problem, the inventor has come up with an imaging device in which the parasitic resistance and parasitic capacitance of the semiconductor substrate are reduced. In such an imaging apparatus, for example, nonuniformity in pixel output is reduced. Thereby, for example, streaking and shading can be suppressed.

  Hereinafter, this imaging device will be disclosed.

(Study on streaking)
First, I will describe the considerations for streaking and the knowledge gained during development.

(1) Streaking Occurrence Mechanism FIG. 1 is a schematic diagram showing an equivalent circuit of a pixel array in which pixels are arranged in a matrix. In the figure, horizontal resistance and capacitance are described as parasitic components between pixels. Hereinafter, the generation process of streaking will be described with reference to FIG. In FIG. 1, pixel 1 and pixel 2 are located in the same row and are connected by a horizontal common line 200. The pixel 1 is a pixel that is irradiated with light, and the pixel 2 is a pixel that is not irradiated with light.

  Each of the pixel 1 and the pixel 2 includes a photoelectric conversion unit (not shown) that converts light into electric charge, and an FD (floating diffusion, FD61 in the pixel 1, and FD62 in the pixel 2) that accumulates electric charge. The amplification transistor 63 and the amplification transistor 64 output signals corresponding to the charges accumulated in the FD 61 and FD 62 to the vertical signal line 65 and the vertical signal line 66, respectively. In the process of reading the pixel signal of the pixel 1, the voltage of the FD 61 varies. This voltage fluctuation propagates to the pixel 2 through the horizontal common line 200. In other words, the voltage of the FD 62 of the pixel 2 varies according to the coupling capacitance between the horizontal common line 200 and the FD 61 of the pixel 1 and the capacitance of the FD 62 of the pixel 2. Therefore, even if the signal output of the pixel 2 is originally zero, a false signal may be output from the pixel 2 due to the voltage fluctuation in the pixel 1. As described above, this false signal propagates in the horizontal direction of the pixel 1 irradiated with light. Therefore, it becomes a horizontal band noise. In the present disclosure, this horizontal band noise is referred to as streaking.

(2) Streaking Formulation When the potential change (V) in the FD of the pixel 1 is ΔV _sig and the signal output of the pixel 2 is V _o (V), the relationship between V _o and ΔV _sig is formulated as follows: it can.

Here, C _FD-Line is the _FD- horizontal common line capacitance [fF / μm] of the pixel 1, C _Line is the horizontal common line capacitance [fF / μm], and R _Line is the horizontal common line resistance [Ω / μm]. ], _CFD is the FD capacity [fF / μm] of the pixel 1, T is the readout period [sec] of the source follower in the pixel, and L is the horizontal size [mm] of the imaging device.

V _o can also be expressed as:

q is the elementary charge (1.602 × 10 ⁻¹⁹ C), and N _sig is the number of streaking electrons.

Substituting Equations (2) and (3) into Equation (1) and transforming the horizontal common line resistance (R _Line ) results in the following.

Here, it is assumed that the FDs of the pixel 1 and the pixel 2 are located in the well of the semiconductor substrate. In that case, the well can be regarded as a horizontal common line. The combined resistance from the FD of the pixel 1 to the next adjacent pixel is R _sub (Ω / μm), and the total capacitance between the substrate and the configuration connected to the substrate per pixel is C _sub (fF / μm). , the capacitance between FD substrate and pixel _{1 C FD-sub (fF /} μm) and then, _C sub to _{C Line} of formula _(4), and substituting _{C FD-sub} to _{C FD-Line,} formula (5) It becomes.

From the equations so far, it can be seen that if the combined resistance Rsub is small, the number of streaking electrons is small. This is because even if the potential change of the FD propagates to adjacent pixels, the change converges immediately if the combined resistance is small. Next, using this equation, the combined resistance of the P well necessary for reducing streaking is obtained. As a precondition, the target number of streaking electrons is set to one electron or less from the viewpoint that streaking electrons are not visually recognized or streaking correction can be performed. Further, since the resistance value in the horizontal direction increases as the size of the imaging device increases, it is assumed that the imaging format of the imaging device is a full size that is the maximum in the camera standard. Note that in the full-size imaging device, the horizontal size is L = 36 mm. As an imaging condition, a worst case is assumed in which the pixel 1 is irradiated with light that becomes a saturation signal. Specifically, it is assumed that after the pixel 2 is irradiated with light that becomes a saturation signal and the voltage of the FD 61 of the pixel 1 rises to 3 V, the voltage of the FD 61 is reset to 0.5 V in order to discharge the signal charge. To do. In that case, the voltage difference of the FD 61 of the pixel 1 is ΔV _sig = 2.5V.

C _sub , which is the total capacity of the P well, is determined by the diffusion layer capacity and is about 2 fF / um regardless of the pixel pitch.

C _FD-sub depends on the diffusion layer area of the FD. The area of the FD is about 0.07 μm ² and the capacity is about 0.3 fF.

  T is the readout period of the source follower in the pixel. T is generally about 1 to 3 μsec, but 2 μsec is used for the calculation. By substituting each of the numerical values described above into Equation (5), the well resistance required for the full-size imaging device can be calculated. As a result of the calculation, the value of the well resistance was 1 kΩ.

  Therefore, it is considered that streaking can be suppressed to 1 electron or less in a general imaging format if the combined resistance between the FDs of the pixels at the left and right ends of the pixel array in the horizontal direction is set to 1 kΩ or less.

(Embodiment 1)
[1-1. Constitution]
FIG. 2 shows the overall configuration of the imaging apparatus 71A according to the first embodiment.

  As shown in the figure, the imaging device 71A includes a pixel array 72 in which pixels are arranged in m rows and n columns (m and n are positive integers), a peripheral circuit 73 including a readout circuit, and a vertical scanning circuit. 74.

  3A is a cross-sectional view of the outer edge portion of the pixel array 72A and its periphery, and FIG. 3B is a plan view of the pixel array 72A and its periphery.

  As shown in FIG. 3B, the periphery of the pixel array 72A is surrounded by a peripheral region 76A. Here, the peripheral region 76A is a region where a contact connecting the support substrate 31B and an external circuit is electrically connected to the support substrate 31B.

  As shown in FIG. 3A, a P-type region 31A is disposed on the support substrate 31B in the pixel array 72A and its peripheral portion. Further, an N-type region 31C is disposed between the support substrate 31B and the P-type region 31A in the pixel array 72A and its periphery. In the pixel array 72A, an FD is formed in the P-type region 31A.

A peripheral region 76A is arranged around the pixel array 72A, and the peripheral region 76A and the pixel array 72A are separated by STI (Shallow Trench Isolation). A P-type region 32 having a P-type impurity concentration higher than that of the P-type region 31A is formed in a part of the pixel array 72A and a part of the peripheral region 76A. The impurity concentration of the P-type region 32 is, for example, 5 × 10 ¹⁶ / cm ³ or more. The P-type region 32 connects the surface layer portion of the P-type region 31A and the support substrate 31B with a low resistance.

  4A is a sectional view of each pixel 14A constituting the pixel array 72A, and FIG. 4B is a plan view of the pixel 14A. FIG. 4A is a cross-sectional view taken along the line CC ′ in FIG. 4B.

  As shown in FIG. 4A, the pixel 14A includes a support substrate 31B, a P-type region 31A, a P well 35, interlayer insulating films 43A, 43B, and 43C, and the photoelectric conversion unit 10.

  The photoelectric conversion unit 10 includes a pixel electrode 50 disposed on the interlayer insulating film 43 </ b> C, a photoelectric conversion film 51 disposed on the pixel electrode 50, and a transparent electrode 52 disposed on the photoelectric conversion film 51. The photoelectric conversion unit 10 converts light applied to the photoelectric conversion film 51 into electric charges. One charge among the electron-hole pairs generated by the photoelectric conversion is collected in the pixel electrode 50.

  The P-type region 31A is disposed above the support substrate 31B and contains P-type impurities at a lower concentration than the support substrate 31B.

  In the P-type region 31A, an FD 44, which is a charge storage region containing an N conductivity type impurity, is disposed. The FD 44 is connected to the pixel electrode 50 via the contact plug 45, the wiring 46A, the plug 47A, the wiring 46B, the plug 47B, the wiring 46C, and the plug 47C, and accumulates the charges collected by the pixel electrode 50.

  The P well 35 is disposed in the P type region 31A, and contains a P-conductivity type impurity at a concentration lower than that of the support substrate 31B and higher than that of the P type region 31A.

  The pixel 14A includes a source follower transistor 11, a reset transistor 12, and a selection transistor 13. The source follower transistor 11 includes a gate electrode 39B. The source follower transistor 11 includes an N-type region 41B and an N-type region 41C as a source and a drain. The reset transistor 12 includes a gate electrode 39A. The reset transistor 12 includes an N-type region 41A and an FD 44 as a source and a drain. The selection transistor 13 includes a gate electrode 39C. The selection transistor 13 includes an N-type region 41C and an N-type region 41D as a source and a drain. The gate electrode 39A, the gate electrode 39B, and the gate electrode 39C are disposed on the P well 35. The N-type region 41A, the N-type region 41B, and the N-type region 41C are arranged in the P well 35.

  Gate oxide films 38A, 38B, and 38C are disposed between the P well 35 and the gate electrodes 39A, 39B, and 39C.

  In addition, the pixel 14A includes fifth regions 42B and 42C that electrically separate the pixel 14A and adjacent pixels adjacent to the pixel 14A. The fifth regions 42B and 42C are formed by, for example, STI (Shallow Trench Isolation).

  As shown in FIG. 4A, the pixel 14A includes a first region (supporting substrate 31B) containing a P-type impurity, and a P-type impurity at a lower concentration than the first region. A second region (P-type region 31A) that includes the photoelectric conversion unit 10 that is located above the second region and converts light into electric charge, and is located in the second region, includes an N-type impurity, Charge accumulation region (FD44) for accumulation. The pixel 14A is disposed between the first region (support substrate 31B) and the second region (P-type region 31A), and is a fourth region (N-type) containing impurities of the second conductivity type (N-conductivity type). Region 31C). As shown in FIG. 4A, the P-type region 32 is disposed at a position overlapping the fifth region (STI 42C) when the imaging device 71A is viewed in plan. The P-type region 32 is disposed between the support substrate 31B and the P-type region 31A, and electrically connects the support substrate 31B and the P-type region 31A.

  The pixel array 72A includes a first pixel located at one end of k rows (k is an integer of 1 to m) and a second pixel located at the other end of the k rows. The combined resistance value between the charge accumulation region (FD44) of the first pixel and the charge accumulation region (FD44) of the second pixel is 1 kΩ or less.

  Also, as shown in FIG. 3A, the peripheral region 76 is disposed above the first peripheral region (support substrate 31B) containing the first conductive type (P conductive type) impurity and the first region. And a second peripheral region (P-type region 31A) containing a first conductivity type impurity at a lower concentration than the region.

  5A and 5B are schematic views showing connections from the peripheral region 76 to the external pads 5A to 5D.

  As shown in FIG. 5A, the external pads 5 </ b> A to 5 </ b> D are arranged outside the peripheral region 76 along the row direction of the pixel array 72.

  In order to suppress streaking, it is important to supply a voltage to the well with a low resistance. The voltage supply to the well is performed from the external pads 5A to 5D through the metal wiring, and the resistance of this path is required to be kept low. As shown in FIG. 5B, the imaging device 71A includes a plurality of stacked wiring layers made of metal. The use of the uppermost (uppermost) metal wiring layer (first wiring layer) 100 for supplying voltage to the well is effective in reducing the resistance. This is because the wiring can be thickened in the uppermost metal wiring layer, so that the resistance value can be lowered as compared with the other metal wiring layers (second wiring layers) 101A to 101C.

  The inventors examined the resistivity of the semiconductor substrate and the resistance value of the P-type region 32 necessary for suppressing streaking in this configuration. At that time, examination was performed using the equivalent circuit of FIG.

  FIG. 7A shows a combined resistance (vertical) between the resistance of the P-type region 32 (horizontal axis) and the FD 44 of the pixel 14A at the horizontal left and right ends of the pixel array 72A when the resistivity of the support substrate 31B is fixed to 0.01 Ωcm. It is a graph which shows the relationship with an axis | shaft. Table 1 shows the relationship between the resistance Rz of the P-type region 32 and the combined resistance R at this time.

7B shows the combined resistance between the resistivity (horizontal axis) of the support substrate 31B and the FD 44 of the pixel 14A at the left and right ends of the pixel array 72A when the resistance of the P-type region 32 is fixed at 2.3 kΩ. It is a graph which shows the relationship with a vertical axis | shaft. The relationship between the resistivity R _sub of the support substrate 31B and the combined resistance R at this time is shown in the following table.

As a result of the examination, for example, when the resistance of the P-type region 32 is 2.3 kΩ, the resistivity of the support substrate 31B is 10 Ωcm or less, for example, when the resistivity of the support substrate 31B is 0.01 Ωcm, the P-type region 32 It was found that the combined resistance between the FDs 44 of the pixels 14A at the left and right ends in the horizontal direction of the pixel array 72A would be 1 kΩ or less if the resistance value of 5 kΩ or less was satisfied. In order to set the resistivity of the support substrate 31B to 0.01 Ωcm or less, the impurity concentration of the semiconductor substrate may be set to 1 × 10 ¹⁸ / cm ³ or more. In order to set the resistance value of the P-type region 32 to 5 kΩ or less, the impurity concentration of the P-type region 32 may be set to 5 × 10 ¹⁶ / cm ³ or more. When the P-type region 31A is formed deep and the distance from the surface of the semiconductor substrate to the surface of the support substrate 31B is long, it is difficult to reduce the resistance of the P-type region 32 to 5 kΩ or less by one impurity implantation. There is. In that case, the impurity implantation for forming the P-type region 32 may be performed a plurality of times. FIG. 8 shows changes in the impurity concentration of the P-type region 32 when the number of implantations is changed. When impurity implantation is performed once, there is one impurity concentration peak, but the impurity concentration in the portion where the substrate depth is large from that peak is one digit or more smaller. When the impurity implantation is performed twice, there are two impurity concentration peaks, and when the impurity implantation is performed three times, there are three impurity concentration peaks. It can also be seen that as the number of impurity implantations is increased, the impurity concentration is maintained without decreasing even between the peak impurity concentrations.

[1-2. effect]
In conventional imaging devices, N-type transistors are generally used. This is because the mobility in the silicon substrate is higher for electrons than for holes, so that an N-type transistor using electrons as carriers has a higher driving force than a P-type transistor using holes as carriers. In order to use an N-type transistor, it is necessary to form a P-type well in the substrate.

  An imaging device using a photodiode as a photoelectric conversion element is generally used. In an imaging device using a photodiode, color mixing between pixels is generally likely to occur. This is because the area ratio of the photodiode with respect to the area of the pixel is large, so that the charge easily moves to the FD of the adjacent pixel. In general, the photodiode is formed up to a relatively deep position in the substrate. In a deep position of the photodiode, the distance to the FD of its own pixel and the distance to the FD of an adjacent pixel may be approximately the same. For this reason, electric charges generated by photoelectric conversion at a deep position of the photodiode may move to the FD of an adjacent pixel. Since the absorption wavelength and the depth of the substrate where photoelectric conversion occurs are in a proportional relationship, charges generated by photoelectric conversion of red light having a long wavelength are particularly likely to move to adjacent pixels. Therefore, red color mixture tends to occur.

  However, in the configuration in which the P-type well is formed on the N-type substrate and the N-type diffusion layer is formed, the charge existing near the well in the photodiode is discharged by applying a voltage to the N-type substrate. Can do. With this configuration, color mixing between pixels can be suppressed in an imaging device using a photodiode. That is, in order to use both the photodiode and the N-type transistor in the imaging device, a P-type well is formed in the N-type substrate, an N-type diffusion layer is formed in the well, and the photodiode and the N-type transistor are diffused. Need to be layered.

  In order to form a P-type well in an N-type substrate, it is generally performed by implanting P-type ions. However, implanting P-type ions having a reverse polarity with respect to the N-type substrate increases the number of crystal defects in the N-type substrate.

  Therefore, when a photodiode is used as the photoelectric conversion unit and an N-type transistor is used, the problem of color mixing cannot be solved if a P-type substrate is used, and if an N-type substrate is used, an increase in crystal defects may occur. There is.

  On the other hand, in the imaging device in which the photoelectric conversion unit is located on the semiconductor substrate as in the present disclosure, no photodiode is formed on the semiconductor substrate. Therefore, there is a low possibility of color mixing in the semiconductor substrate. Therefore, a support substrate having the same conductivity type as the well (P type) can be used. For this reason, it is not necessary to implant ions of opposite polarity into the substrate, so that the crystal defects of the wells that have occurred by ion implantation are reduced.

  Further, a support substrate 31B having a low resistance value is connected to the P well. The resistivity of the support substrate 31B is as low as about 10 Ωcm. The resistance of the surface of the P well is about several kΩ, but by connecting the P well to the low-resistance support substrate 31B described above, the combined resistance between the FDs 44 of the pixels 14 at the horizontal left and right ends of the pixel array 72 is 1 kΩ or less. Can be. As a result, for example, streaking is suppressed.

  Further, in order to reduce the well resistance, the conventional imaging device generally takes the following configuration. A substrate contact connected to the metal wiring and the well is disposed on the substrate surface of each pixel. The potential of the well is fixed by applying a voltage through the metal wiring. However, in order to arrange the substrate contact in each pixel, it is necessary to reduce the size of the transistor in the pixel. If the size of the transistor is reduced, the driving capability is reduced correspondingly, which may affect the performance of the imaging device. On the other hand, in the present embodiment, an external pad, which is a substrate contact electrically connected to the P-type region 32, is disposed in the peripheral region of the pixel portion. By applying a voltage from the external pad, the potential of the well of the pixel portion can be fixed through the support substrate.

  Further, the support substrate 31B is electrically connected to the contact plug connected to the external pads 5A to 5D in the peripheral region 76 through the P-type region 32 with a low resistance.

  As described above, the cause of streaking is that a voltage change of a pixel to which light is irradiated (Bright pixel) propagates through the horizontal common line 200 to a pixel (Dark pixel) to which light is not irradiated. In the present embodiment, the well voltage application path from the external pads 5A to 5D is the vertical direction of the pixel array 72, and the propagation path in the horizontal direction is eliminated. Thereby, for example, streaking is suppressed.

  In the present embodiment, an N-type region 31C is arranged in each pixel. By applying a bias voltage to the N-type region 31C, excess charges can be collected by the N-type region 31C before reaching the FD and discharged to the power source. Thereby, the dark current in each pixel cell can be effectively reduced.

  In the imaging device 71A according to the first embodiment, the third region (P-type region 32) is arranged at a position overlapping the fifth region (STI 42C) when the imaging device 71A is viewed in plan. In other words, the P-type region 32 is not disposed at a position overlapping the transistor in the pixel when viewed in plan. In a transistor in a pixel, an impurity may be implanted into a channel in order to adjust a threshold value. In that case, if another impurity region exists below the transistor in the pixel, the threshold value of the transistor may be affected. In the present embodiment, since the P-type region 32 is disposed at a position overlapping the STI 42C, the threshold value of the transistor in the pixel is hardly affected. Therefore, the threshold value of the transistor in the pixel can be easily set. For this reason, the imaging device 71A can be mass-produced while the characteristics of the pixel 14A are stable.

(Embodiment 2)
Here, with respect to the imaging apparatus 71 according to the second embodiment, a part of which is changed from the imaging apparatus 71A according to the first embodiment, mainly the differences from the imaging apparatus 71A according to the first embodiment are mainly described. Explained.

[2-1. Constitution]
In the imaging device 71, the pixel array 72A is changed to the pixel array 72 from the imaging device 71A according to the first embodiment.

  9A is a cross-sectional view of the outer edge portion of the pixel array 72 and its periphery, and FIG. 9B is a plan view of the pixel array 72 and its periphery.

  As shown in FIGS. 9A and 9B, the imaging device 71 includes a support substrate 31 </ b> B and a P-type region 31 </ b> A at the point where the P-type region 32 is arranged only in the peripheral region 76 and the pixel array 72 and its periphery. Is different from the imaging device 71A according to the first embodiment in that the N-type region 31C is not disposed between the imaging device 71A and the imaging device 71A.

  FIG. 10A is a cross-sectional view of each pixel 14 constituting the pixel array 72, and FIG. 10B is a plan view of the pixel 14. FIG. 10A is a cross-sectional view on the line connecting CC ′ in FIG. 10B.

  As shown in FIG. 10A, the pixel 14 has a P-type region 32 disposed in the pixel 14 in addition to the point that the N-type region 31C is not disposed between the support substrate 31B and the P-type region 31A. This is different from the pixel 14A according to the first embodiment in that it is not.

  The P-type region 32 is disposed between the support substrate 31B and the P-type region 31A, and electrically connects the support substrate 31B and the P-type region 31A.

  Thus, the pixel 14 includes the first region (support substrate 31B) and the second region (P-type region 31A). The pixel 14 includes three regions (P-type regions 32) that are in contact with the first region and the second region and contain impurities of the first conductivity type (P conductivity type) at a higher concentration than the second region.

[2-2. effect]
Also in the present embodiment, the same effect as in the first embodiment can be obtained.

  In the present embodiment, the N-type region 31C is not disposed between the support substrate 31B and the P-type region 31A. Therefore, since the number of impurity implantations can be reduced as compared with Embodiment Mode 1, it can be manufactured at lower cost.

(Supplement)
As described above, Embodiment 1 and Embodiment 2 have been described as examples of the technology disclosed in the present application. However, the technology according to the present disclosure is not limited to these, and can also be applied to embodiments in which changes, replacements, additions, omissions, and the like are appropriately performed. In the first and second embodiments, the example in which the P-type region 31A is formed on the support substrate 31B containing P-type impurities and the source and drain of the transistor in the pixel are N-type regions has been described. These conductivity types may be reversed.

  The imaging device according to the present disclosure can be used for a digital camera, a digital video camera, a camera-equipped mobile phone, a medical camera such as an electronic endoscope, an in-vehicle camera, a robot camera, and the like.

5A, 5B, 5C, 5D External pad 10 Photoelectric conversion unit 14, 14A Pixel 31A P-type region (second region, second peripheral region)
31B Support substrate (first region, first peripheral region)
31C N-type region (fourth region)
32 P-type region (third region)
42C STI (5th area)
44 Charge Storage Area 71, 71A Imaging Device 72, 72A Pixel Array 76 Peripheral Area 100 Uppermost Metal Wiring Layer (First Wiring Layer)
101A, 101B, 101C Other metal wiring layer (second wiring layer)

Claims (13)

An imaging apparatus comprising a semiconductor substrate and a pixel array in which pixels are arranged in m rows and n columns (m and n are positive integers),
Each of the pixels
A photoelectric conversion unit that is located above the semiconductor substrate and converts light into charges,
The semiconductor substrate is
A first region containing a first conductivity type impurity;
A second region disposed above the first region and including the first conductivity type impurity at a lower concentration than the first region;
A charge storage region that is located in the second region and includes an impurity of a second conductivity type different from the first conductivity type, and stores the charge;
With
The pixel array is
a first pixel located at one end of k rows (k is an integer from 1 to m);
a second pixel located at the other end of the k rows,
A combined resistance value between the charge accumulation region of the first pixel and the charge accumulation region of the second pixel is 1 kΩ or less;
Imaging device. The semiconductor substrate is
A third region in contact with the first region and the second region and including the first conductivity type impurity at a higher concentration than the second region;
The imaging device according to claim 1. The semiconductor substrate is
A fourth region that is disposed between the first region and the second region and includes the impurity of the second conductivity type.
The imaging device according to claim 2. Comprising a peripheral region located around the pixel array;
The third region is located in the peripheral region;
The imaging device according to claim 2. The third region is located in the pixel array;
The imaging device according to claim 2. Comprising a peripheral region located around the pixel array;
A plurality of the third regions;
At least one of the third regions is located in the peripheral region;
At least one of the third regions is located in the pixel array;
The imaging device according to claim 2. The pixel includes a fifth region that is located in the second region and electrically separates the pixel and an adjacent pixel adjacent to the pixel,
When the imaging device is viewed in plan, the third region located in the pixel array overlaps the fifth region.
The imaging device according to claim 4 or 6. The resistivity of the first region is 10 Ωcm or less,
The resistance value of the third region is 2.3 kΩ or less,
The imaging device according to any one of claims 2 to 7. The resistivity of the first region is 0.01 Ω · cm or less,
The resistance value of the third region is 5 kΩ or less,
The imaging device according to any one of claims 2 to 7. The concentration of the first conductivity type impurity in the first region is 1 × 10 ¹⁸ / cm ³ or more,
The resistance value of the third region is 5 kΩ or less,
The imaging device according to any one of claims 2 to 7. The resistivity of the first region is 0.01 Ωcm or less,
The concentration of the first conductivity type impurity in the third region is 5 × 10 ¹⁶ / cm ³ or more.
The imaging device according to any one of claims 2 to 7. When the imaging device is viewed in plan, a peripheral region located around the pixel array;
When the imaging device is viewed in plan, an external pad located outside the peripheral region and along the row direction of the pixel array;
When the imaging device is viewed in plan, a wiring region that is located between the peripheral region and the external pad and includes a plurality of wiring layers,
In the peripheral region, the semiconductor substrate is
A first peripheral region containing an impurity of the first conductivity type;
A second peripheral region disposed above the first peripheral region and including the first conductivity type impurity at a concentration lower than that of the first peripheral region;
The plurality of wiring layers are:
A first wiring layer made of metal;
A second wiring layer located below the first wiring layer,
The second peripheral region and the external pad are connected via the first wiring layer.
The imaging device according to any one of claims 1 to 11. The first wiring layer is located on the top of the plurality of wiring layers;
The imaging device according to claim 12.

Images