JP2012004255A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stably suppress noise propagation from a digital circuit to other circuits even if properties of a semiconductor substrate vary.SOLUTION: A separation part 30 is formed between a digital circuit 41 and a semiconductor circuit 42 which are formed on a semiconductor substrate 10, so as to separate the digital circuit 41 from the semiconductor circuit 42. In the separation part 30, an Nlayer 3N, silicon 11, and a Player 3P are arranged alongside in this order in the X-direction.

Description

  The present invention relates to a semiconductor device for suppressing noise propagation between two circuits.

  RF (Radio Frequency) analog mixed system LSI (Large Scale Integration) has been developed in order to meet the demand for price reduction and downsizing of digital equipment represented by digital television. Here, the RF analog mixed system LSI is an LSI in which a high frequency (RF) circuit and an analog circuit are mixedly mounted on a large-scale digital circuit (system LSI) formed by a complementary metal oxide semiconductor (Si-CMOS) process.

  In an RF analog mixed system LSI, high-frequency noise generated by a digital circuit that operates at high speed propagates to an RF circuit or analog circuit that is susceptible to noise through a substrate or a well. Therefore, the operation of the RF circuit and the analog circuit is hindered.

  By adopting a layout in which the distance from the digital circuit, which is a noise source, to the RF circuit or the analog circuit is increased, it is possible to reduce noise transmitted to the RF circuit or the analog circuit. However, in this case, the chip area of the LSI increases or the circuit layout in the LSI is restricted.

  In an RF analog mixed system LSI, it is important to suppress noise generated by a digital circuit in order to realize high performance of an RF circuit or an analog circuit and reduce a chip area. Hereinafter, noise generated by a digital circuit is also referred to as digital noise.

  Patent Documents 1 and 2 disclose a technique for suppressing noise generated by a digital circuit by forming a high-resistance region between the digital circuit and the analog circuit.

  For example, in Patent Document 1, by using a high-resistance P-type silicon substrate having a low boron concentration, the area between the digital circuit area and the analog circuit area is made high resistance. Thereby, the propagation of noise from the digital circuit to the analog circuit is suppressed.

  FIG. 12 is a diagram illustrating an example of a configuration of a conventional semiconductor device 600 disclosed in Patent Document 1. In FIG.

  FIG. 12A is a plan view of a conventional semiconductor device 600. FIG. FIG. 12B is a cross-sectional view of the semiconductor device 600 taken along line X11-X11 ′ in FIG.

  The semiconductor device 600 includes a P-type silicon substrate 110. A first N well 121 is formed near the surface of the P-type silicon substrate 110. A digital circuit 141 is formed in the first N well 121.

  A second N well 122 is further formed in the vicinity of the surface of the P-type silicon substrate 110. An analog circuit 142 is formed in the second N well 122.

  In the semiconductor device 600 configured as described above, a region between the first N well 121 and the second N well 122 is a noise isolation region that suppresses noise generated by the digital circuit 141 from propagating to the analog circuit 142. Acts as 130.

  The width of the noise isolation region 130 is determined by the performance required for the semiconductor device. The width of the noise isolation region 130 is generally about several tens of μm. The higher the noise propagation suppression effect, the narrower the noise separation region, so that the chip area can be reduced.

  In particular, by using a high-resistance P-type silicon substrate having a low boron concentration as the P-type silicon substrate 110, the noise isolation region 130 can be increased in resistance, so that noise propagation from the digital circuit 141 to the analog circuit 142 is achieved. Can be effectively suppressed. If the noise propagation level is the same, the chip area can be reduced.

FIG. 13 is a diagram illustrating the frequency dependence of the noise entry level.
Specifically, FIG. 13 is a diagram showing the noise entry level with respect to frequency obtained by simulation when the resistance of the P-type silicon substrate 110 is 0.01 Ωcm and 500 Ωcm. The noise entry level is the magnitude of noise (digital noise) generated by the digital circuit that enters the analog circuit.

  A characteristic line L120 indicates the characteristic when the resistance of the P-type silicon substrate 110 is 0.01 Ωcm. A characteristic line L121 indicates the characteristic when the resistance of the P-type silicon substrate 110 is 10 Ωcm. In this way, noise propagation can be suppressed by using a silicon substrate having a high resistance.

JP 2001-345428 A JP 2007-059511 A

  However, the conventional technique using a high-resistance P-type silicon substrate has the following problems.

  Usually, a silicon substrate contains supersaturated oxygen, and this oxygen forms an oxygen donor in a heat treatment step during the manufacturing process, thereby causing a situation in which the resistance of the silicon substrate fluctuates after the manufacturing process. The oxygen donor acts as an N-type impurity in the silicon substrate.

  In a silicon substrate having a resistivity of about 0.01 to 10 Ωcm used in a general Si-CMOS process, the influence of oxygen donors on the resistance of the silicon substrate is negligible.

  However, when the resistance of the silicon substrate becomes high, the amount of oxygen donors generated cannot be ignored with respect to the boron concentration which is an impurity, and the influence of the oxygen donors on the resistance of the silicon substrate becomes obvious.

  In particular, when a large amount of oxygen donors are generated by heat treatment during the manufacturing process, a situation occurs in which the conductivity type of the silicon substrate is inverted (changed) from P-type to N-type. Oxygen donors are particularly likely to be generated by heat treatment at about 400 ° C. to 500 ° C., and thus are generated in large quantities in a multilayer wiring process such as hydrogen sintering. In particular, in the recent fine CMOS, the number of wiring layers is increased and the number of heat treatments is increased, so that oxygen donors are more easily generated than in the past.

FIG. 14 is a diagram showing the relationship of the noise entry level to the oxygen donor production amount.
In FIG. 14, a characteristic line L10 is a line indicating the characteristics of the conventional semiconductor device 600. Here, the noise entry level is the magnitude of noise (digital noise) generated by the digital circuit that enters the analog circuit. The amount of donor production is the amount of oxygen donor production. The region R110 is a region where the conductivity type (conductivity type) of the silicon substrate is inverted from the P type to the N type.

  The generation of oxygen donors varies the resistance of the noise isolation region, resulting in variations in the level of suppression of noise propagation from the digital circuit to the analog circuit. Furthermore, when the conductivity type is reversed (N-type), there is a problem that the noise suppression effect is greatly reduced. Furthermore, in the region R110, when the conductivity type of the silicon substrate is inverted (N-type), there is a problem that the noise suppression effect is greatly reduced.

  The present invention has been made to solve the above-described problems, and its purpose is to stably suppress noise propagation from a digital circuit to another circuit even if the characteristics of the semiconductor substrate change. Is to provide a simple semiconductor device.

  In order to solve the above-described problem, a digital circuit and a semiconductor circuit are mixedly mounted in a semiconductor device according to an aspect of the present invention. The semiconductor device includes a semiconductor substrate formed of a first conductivity type material, and the digital circuit and the semiconductor circuit are formed to be aligned in a first direction on the semiconductor substrate, and are formed on the semiconductor substrate. A separation portion is formed between the digital circuit and the semiconductor circuit so as to separate the digital circuit and the semiconductor circuit, and the separation portion includes a first conductive layer that is a first conductivity type layer. One or more of each of the mold layer and the second conductivity type layer that is a layer of the second conductivity type are formed, and the separation portion includes the second conductivity type layer, the first conductivity type material, and the first conductivity type. The layers are arranged side by side in the first direction in this order.

  That is, a separation unit is formed between the digital circuit and the semiconductor circuit formed on the semiconductor substrate so as to separate the digital circuit and the semiconductor circuit. In the separation portion, the second conductivity type layer, the first conductivity type material, and the first conductivity type layer are arranged in this order in the first direction.

  Therefore, even if the conductivity type of the material of the first conductivity type is changed from the first conductivity type to the second conductivity type, the separation portion includes the second conductivity type layer and the second conductivity type. The material and the first conductivity type layer are arranged side by side in the first direction in this order. That is, even in this case, two types of conductive components, that is, the second conductive material and the first conductive layer are arranged in the first direction in the separation portion.

  Therefore, even if the conductivity type of the first conductivity type material (conductivity type of the semiconductor substrate) is changed from the first conductivity type to the second conductivity type, it is formed between the digital circuit and the semiconductor circuit. The separating unit can suppress noise propagation from the digital circuit to the semiconductor circuit.

  That is, even if the characteristics of the semiconductor substrate change, noise propagation from the digital circuit to the semiconductor circuit as another circuit can be stably suppressed.

  Preferably, a second conductivity type first well and a second well are independently formed on the semiconductor substrate, the digital circuit is formed in the first well, and the second well is formed in the second well. The semiconductor circuit is formed.

  Preferably, the thickness of each of the first conductivity type layer and the second conductivity type layer is larger than the thickness of the second well.

  Preferably, each of the first conductivity type layer and the second conductivity type layer is formed so as to surround the second well.

  Thereby, noise propagation from the digital circuit to the semiconductor circuit formed in the second well can be significantly suppressed.

  Preferably, each of the first conductivity type layer and the second conductivity type layer extends along a second direction orthogonal to the first direction.

  Preferably, a plurality of each of the first conductivity type layer and the second conductivity type layer are formed in the separation part, and the separation part includes the second conductivity type layer and the first conductivity type. The material and the first conductivity type layer are arranged side by side in this order in the first direction and the second direction orthogonal to the first direction.

Thereby, the noise suppression effect of a isolation | separation part can be improved.
Preferably, the first conductivity type is P type, the second conductivity type is N type, and the first conductivity type material and the second conductivity type layer are formed to be joined, A reverse bias is applied to a PN junction that is a junction between the first conductivity type material and the second conductivity type layer.

  Thereby, a depletion layer is formed around the PN junction, and noise propagation from the digital circuit to the semiconductor circuit can be suppressed.

Preferably, the resistance of the first conductivity type material is 100 Ωcm or more.
Preferably, the oxygen concentration in the semiconductor substrate is 1.0 × 10 ¹⁸ cm ⁻³ or more.

Preferably, the oxygen concentration in the semiconductor substrate is 1.7 × 10 ¹⁸ cm ⁻³ or less.

  Preferably, the semiconductor circuit is an RF (Radio Frequency) circuit or an analog circuit.

  Preferably, the semiconductor circuit is a circuit including at least one of an RF (Radio Frequency) circuit and an analog circuit.

  According to the present invention, it is possible to stably suppress noise propagation from a digital circuit to another circuit even if the characteristics of the semiconductor substrate change.

1 is a diagram illustrating a structure of a semiconductor device according to a first embodiment. It is an enlarged view of a separation part. It is sectional drawing of a separation part vicinity. It is sectional drawing for demonstrating the manufacturing method of a semiconductor device. It is a figure for demonstrating the depletion layer formed in a isolation | separation part. It is a figure which shows the relationship of the noise approach level with respect to oxygen donor production amount. It is a figure which shows the frequency dependence of a noise approach level. It is a figure which shows an example of a structure of a isolation | separation part. It is a figure which shows an example of a structure of a isolation | separation part. It is a top view of the isolation | separation part which concerns on the modification of 1st Embodiment. It is a figure which shows an example of a structure of a isolation | separation part. It is a figure which shows an example of a structure of the conventional semiconductor device. It is a figure which shows the frequency dependence of a noise approach level. It is a figure which shows the relationship of the noise approach level with respect to oxygen donor production amount.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
In the semiconductor device according to the first embodiment of the present invention, a digital circuit and a semiconductor circuit are mixedly mounted. The semiconductor device includes a semiconductor substrate formed of a first conductivity type material, and the digital circuit and the semiconductor circuit are formed to be aligned in a first direction on the semiconductor substrate, and are formed on the semiconductor substrate. A separation portion is formed between the digital circuit and the semiconductor circuit so as to separate the digital circuit and the semiconductor circuit, and the separation portion includes a first conductive layer that is a first conductivity type layer. One or more of each of the mold layer and the second conductivity type layer that is a layer of the second conductivity type are formed, and the separation portion includes the second conductivity type layer, the first conductivity type material, and the first conductivity type. The layers are arranged side by side in the first direction in this order.

FIG. 1 is a diagram showing a structure of a semiconductor device 1000 according to the first embodiment.
FIG. 1A is a plan view of the semiconductor device 1000. In FIG. 1A, the Y direction and the X direction are orthogonal to each other.

  FIG. 1B is a cross-sectional view of the semiconductor device 1000. Specifically, FIG. 1B is a cross-sectional view of the semiconductor device 1000 taken along line X1-X1 ′ of FIG.

  The semiconductor device 1000 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of P-type silicon 11. That is, the conductivity type (conduction type) of the silicon 11 is P type. The silicon 11 is P-silicon. That is, the semiconductor substrate 10 is a substrate formed of a first conductivity type (P-type) material.

  The silicon 11 is high resistance silicon. That is, the semiconductor substrate 10 formed of silicon 11 is a high resistance P-type substrate.

  The resistance of the silicon 11 as the first conductivity type material is 100 Ωcm or more. That is, the resistance of the semiconductor substrate 10 formed of the silicon 11 is 100 Ωcm or more.

  Here, the resistance of the silicon 11 is, for example, 500 Ωcm. That is, the resistance of the semiconductor substrate 10 formed of silicon 11 is 500 Ωcm.

Further, the oxygen concentration in the semiconductor substrate 10 formed of the silicon 11 is preferably 1.0 × 10 ¹⁸ cm ⁻³ or more from the viewpoint of securing the mechanical strength of the semiconductor substrate 10. Therefore, the oxygen concentration in the semiconductor substrate 10 is 1.0 × 10 ¹⁸ cm ⁻³ or more. Here, the oxygen concentration in the semiconductor substrate 10 is, for example, 1.3 × 10 ¹⁸ cm ⁻³ .

  Although an insulating film layer 50 (not shown) is formed on the semiconductor substrate 10, the insulating film layer 50 is not shown in FIG. 1A to show the state of the surface of the semiconductor substrate 10.

  A first N well 21 and a second N well 22 are independently formed near the surface of the semiconductor substrate 10. That is, a first conductivity type (N type) first well and a second well are independently formed in the semiconductor substrate 10.

  A digital circuit 41 is formed in the first N well 21. Hereinafter, an area where the digital circuit 41 is formed is referred to as a digital circuit area.

  A semiconductor circuit 42 is formed in the second N well 22. The semiconductor circuit is an RF (Radio Frequency) circuit or an analog circuit.

  The digital circuit 41 and the semiconductor circuit 42 are formed to be aligned in the X direction as the first direction in the semiconductor substrate 10.

  The semiconductor circuit 42 may be a circuit including both an RF circuit and an analog circuit. The semiconductor circuit 42 may be a circuit including an RF circuit or an analog circuit. That is, the semiconductor circuit 42 is a circuit including at least one of an RF circuit and an analog circuit. Hereinafter, a region where the semiconductor circuit 42 is formed is referred to as a semiconductor circuit region.

  A separation portion 30 as a noise separation region is formed between the first N well 21 and the second N well 22 so as to separate the first N well 21 and the second N well 22. That is, the separation unit 30 is formed between the digital circuit 41 and the semiconductor circuit 42 formed on the semiconductor substrate 10 so as to separate the digital circuit 41 and the semiconductor circuit 42.

  The separation unit 30 includes a silicon 11 as a P-silicon layer, a plurality of N + layers 3N, and a plurality of P + layers 3P. In FIG. 1A, for simplification of the drawing, three N + layers 3N and two P + layers 3P are shown. The number of each of the N + layers 3N and the P + layers 3P is as follows. It is not limited.

  The P + layer 3P is a layer formed by doping the semiconductor substrate 10 with a P-type impurity. The P + layer 3P is a first conductivity type (P type) layer (hereinafter also referred to as a first conductivity type layer).

  The N + layer 3N is a layer formed by doping the semiconductor substrate 10 with an N-type impurity. The N + layer 3N is a second conductivity type (N type) layer (hereinafter also referred to as a second conductivity type layer).

  That is, at least one of the first conductivity type layer and the second conductivity type layer is formed in the separation part 30.

  In the X direction, the N + layers 3N and the P + layers 3P are alternately arranged. Each N + layer 3N is formed in contact with the P-type silicon 11. Each P + layer 3P is formed in contact with the P-type silicon 11.

  Specifically, the separation unit 30 includes a second conductivity type layer (N + layer 3N), a first conductivity type material (silicon 11), and a first conductivity type layer (P + layer 3P) in this order. Arranged side by side in one direction (X direction).

  Each of N + layer 3N and P + layer 3P extends along the Y direction. That is, each of the first conductivity type layer and the second conductivity type layer extends along a second direction (Y direction) orthogonal to the first direction.

That is, the N + layer 3N and the P + layer 3P are formed in a striped pattern in the separation unit 30.
FIG. 2 is an enlarged view of the separation unit 30.

  Referring to FIG. 2, each of N + layer 3N and P + layer 3P is provided with a contact portion C40.

  As described above, each N + layer 3 </ b> N and each P + layer 3 </ b> P is formed in contact with the P-type silicon 11.

  That is, the silicon 11 as the first conductivity type material and the N + layer 3N as the second conductivity type layer are formed to be joined. A diode is formed by the silicon 11 and the N + layer 3N. A reverse bias is applied to a PN junction, which is a junction between the silicon 11 as the first conductivity type material and the N + layer 3N as the second conductivity type layer, by a power supply circuit (not shown). As a result, a depletion layer is formed around the PN junction.

  Further, even when the conductivity type of the silicon 11 is changed from P-type to N-type as will be described later, a depletion layer is formed around the PN junction which is a junction between the N-type silicon 11 and the P + layer 3P. A reverse bias is applied to the PN junction by a power supply circuit (not shown) or the like. That is, when the conductivity type of the silicon 11 is N-type, the silicon 11 and the P + layer 3P have a power supply (not shown) so that a reverse bias is applied to the PN junction that is the junction between the silicon 11 and the P + layer 3P. A voltage is applied by a circuit or the like.

  As a result, even when the conductivity type of the silicon 11 is changed from P-type to N-type as will be described later, a depletion layer is formed around the PN junction which is the junction between the silicon 11 and the P + layer 3P. Is done.

  FIG. 3 is a cross-sectional view of the vicinity of the separation unit 30. FIG. 3A is a cross-sectional view of the vicinity of the separation unit 30 along the line X2-X2 'of FIG. FIG. 3B is a cross-sectional view of the vicinity of the separation unit 30 along the line Y1-Y1 'of FIG.

  An insulating film layer 50 is formed on the separation portion 30, that is, on the semiconductor substrate 10. Further, the peak concentration of impurity concentration, the width in the X direction, and the depth (thickness in the Z direction) in each of the N + layer 3N and the P + layer 3P are set as follows, for example.

<N + layer 3N>
Peak concentration: 1.0 × 10 ¹⁹ cm ⁻³ , width d1: 0.2 μm, depth (thickness): 1.0 μm
<P + layer 3P>
Peak concentration: 1.0 × 10 ¹⁹ cm ⁻³ , width d2: 0.2 μm, depth (thickness): 1.0 μm

  Further, the width d3 in the X direction of the silicon 11 (P-silicon layer) in the separation unit 30 is, for example, 5.0 μm.

  The thickness of each of the N + layer 3N (first conductivity type layer) and the P + layer 3P (second conductivity type layer) is larger than the thickness of the second well 22.

  In the example structure shown here, a reverse bias (for example, a voltage of about 3 V) is applied to a PN junction that is a junction between the silicon 11 and the N + layer 3N. Thereby, a depletion layer can be formed in the isolation part 30 in the silicon 11.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device 1000 according to the first embodiment will be described.

FIG. 4 is a cross-sectional view for explaining the method for manufacturing the semiconductor device 1000.
In addition, since each process demonstrated below can be implemented using a well-known process technique, detailed description, such as process conditions, is abbreviate | omitted suitably. The materials and processes described below are only one typical example, and do not limit the semiconductor device 1000 of the present invention and the manufacturing method thereof. Substitutions of other materials and processes of known suitability are also included in the present invention.

  First, as shown in FIG. 4A, a resist RG1 is patterned on the semiconductor substrate 10 (silicon 11).

  Then, an N-type impurity is doped in a region for forming the first N well 21 and the second N well 22 by ion implantation of phosphorus or the like. Thereby, the first N well 21 and the second N well 22 shown in FIG. 4B are formed.

  Next, the resist RG1 is removed by ashing and cleaning. Then, as shown in FIG. 4B, the resist RG2 is newly patterned.

  Then, an N-type impurity is doped in a region for forming the N + layer 3N by ion implantation of phosphorus or the like. Thereby, the N + layer 3N shown in FIG. 4C is formed.

  Next, the resist RG2 is removed by ashing and cleaning. Then, as shown in FIG. 4C, the resist RG3 is newly patterned.

  Then, a P-type impurity is doped in a region for forming the P + layer 3P by ion implantation of boron or the like. Thereby, the P + layer 3P shown in FIG. 4D is formed. As a result, the separation part 30 is formed.

Next, the resist RG3 is removed by ashing and cleaning.
Then, an RTA (Rapid Thermal Annealing) process is performed under the condition that the temperature is 1000 ° C. and the time is about 15 seconds, thereby activating the impurities.

  Next, as shown in FIG. 4E, a digital circuit 41 (digital circuit region) is formed in the first N well 21. A semiconductor circuit 42 (semiconductor circuit region) is formed in the second N well 22.

  Thereafter, a wiring layer (insulating film layer 50) is formed by lithography, dry etching, and a film forming technique, whereby the semiconductor device 1000 in which the digital circuit 41 and the semiconductor circuit 42 are mounted together is formed.

  Next, in the semiconductor device 1000 according to the present embodiment, the N + layer 3N, the silicon 11 and the P + layer 3P are arranged in this order in the X direction in the separation unit 30, and at the PN junction. The effect obtained by applying the reverse bias will be described.

FIG. 5 is a diagram for explaining a depletion layer formed in the separation unit 30.
First, as shown in FIG. 5A, when the amount of oxygen donors generated is small and the conductivity type (conductivity type) of the silicon 11 is maintained at the P type, as described above, the PN junction in the separation unit 30 By applying a reverse bias to the part, the depletion layer 60 is formed (see FIG. 5B).

  The depletion layer 60 is formed in a portion including at least the separation part 30. The depletion layer 60 is formed so as to separate the first N well 21 and the second N well 22. That is, the depletion layer 60 is formed so as to separate the digital circuit 41 and the semiconductor circuit 42.

  In other words, the depletion layer 60 blocks a path through which noise (digital noise) generated in the digital circuit propagates to the semiconductor circuit 42, so that a large suppression effect of noise propagation can be obtained.

  Next, a case will be described in which the amount of oxygen donor generation is increased by the heat treatment during the manufacturing process of the semiconductor device 1000 and the conductivity type (conductivity type) of the silicon 11 is inverted (changed) from the P type to the N type.

  In addition, it is not limited to the heat processing in a manufacturing process, For example, when high heat | fever is added with respect to the silicon | silicone 11 (semiconductor substrate 10) of the semiconductor device 1000 after manufacture, the conductivity type (conductivity type) of the silicon | silicone 11 is P type. There is also a possibility of inversion (change) from N to N type.

  In this case, the P-type silicon 11 in FIG. 5A is changed to the N-type silicon 11N in FIG.

  FIG. 5C is a diagram showing a state where the conductivity type (conductivity type) of silicon is inverted (changed) from the P-type to the N-type.

  Also in the configuration of FIG. 5C, by applying a reverse bias to the PN junction that is the junction between the P + layer 3P and the N-type silicon 11N, as shown in FIG. Is formed.

  That is, in the semiconductor device 1000 according to the present embodiment, even if the characteristics of the semiconductor substrate 10 (silicon 11) change due to the formation of the depletion layer 60N, the semiconductor circuit as another circuit is changed from the digital circuit 41. Noise propagation to 42 can be stably suppressed.

FIG. 6 is a diagram showing the relationship of the noise entry level to the oxygen donor production amount.
The noise entry level is the magnitude of noise (digital noise) generated by the digital circuit 41 that enters the semiconductor circuit 42. The amount of donor production is the amount of oxygen donor production.

  In FIG. 6, a characteristic line L <b> 10 is a line indicating the characteristics of the conventional semiconductor device 600. The characteristic line L11 is a line indicating the characteristics of the semiconductor device 1000 according to the present embodiment. The region R10 is a region where the conductivity type (conductivity type) of silicon constituting the semiconductor substrate is inverted from P type to N type. The characteristic line L10J will be described later.

  As shown in FIG. 6, the semiconductor according to the present embodiment even when the conductivity type (conductivity type) of silicon constituting the semiconductor substrate is changed from the P type to the N type as a result of the increase in the amount of oxygen donor generation. The device 1000 does not increase noise as in the conventional semiconductor device 600, and can continue to maintain a high noise propagation suppression effect.

  That is, according to this embodiment, even if the resistance of the semiconductor substrate 10 fluctuates due to the generation of oxygen donors, it is possible to realize the semiconductor device 1000 that has a high effect of suppressing noise propagation and has little variation.

  In particular, the generation of oxygen donors is difficult to control because it is sensitive to variations in the heat treatment temperature and oxygen variations in the substrate during the device manufacturing process, and varies greatly within the wafer plane, between wafers, and between lots.

  However, in this embodiment, it is possible to suppress fluctuations in the noise propagation suppression effect due to an increase in the amount of oxygen donor generated. As a result, it is possible to realize a semiconductor device that is highly effective in suppressing noise propagation within a wafer surface, between wafers, and between lots, and has little variation.

  At the same time, by setting the oxygen concentration in the substrate appropriately, it is possible to achieve both a high noise propagation suppressing effect and the mechanical strength of the substrate.

FIG. 7 is a diagram showing the frequency dependence of the noise entry level.
Specifically, FIG. 7 is a diagram showing a noise entry level with respect to frequency obtained by a simulation in which the resistance of the semiconductor substrate 10 is changed from 0.01 Ωcm to 500 Ωcm.

  A characteristic line L20 indicates characteristics when the resistance of the semiconductor substrate 10 is 0.01 Ωcm. A characteristic line L21 indicates characteristics when the resistance of the semiconductor substrate 10 is 10 Ωcm. A characteristic line L22 indicates characteristics when the resistance of the semiconductor substrate 10 is 500 Ωcm. When the resistance of the semiconductor substrate 10 is 500 Ωcm, it is assumed that there is no influence from the oxygen donor.

  A characteristic line L23 indicates characteristics when the resistance of the semiconductor substrate 10 is 500 Ωcm and the separation part 30 is formed on the semiconductor substrate 10. That is, the characteristic line L23 indicates the characteristic of the semiconductor device 1000 according to the present embodiment.

  As shown in FIG. 7, the semiconductor device 1000 according to the present embodiment can obtain a high noise propagation suppressing effect due to the synergistic effect of increasing the resistance of the semiconductor substrate and forming a depletion layer.

  In the present embodiment, the separation unit 30 has a structure in which the N + layer 3N, the P-type silicon 11 and the P + layer 3P are arranged in this order in the X direction. Therefore, even when the conductivity type (conduction type) of the silicon 11 is inverted (changed) from the P type to the N type, the depletion layer can be stably formed. As a result, a higher noise propagation suppression effect can be maintained.

  However, in the separation unit 30, if the P + layer 3P is not provided and the N + layer and the P-type silicon 11 are arranged in this order in the X direction, Such an effect cannot be obtained. That is, in the structure in which the N + layers and the P-type silicon are alternately arranged in the X direction of the separation part 30 (hereinafter referred to as the structure J1), the effect as in the present embodiment cannot be obtained.

  The characteristic of the noise entry level with respect to the oxygen donor production amount in the structure J1 is the characteristic indicated by the characteristic line L10J in FIG.

  As shown by the characteristic line L10J, in the structure J1, the effect of suppressing noise propagation is suddenly reduced as soon as the oxygen donor generation amount exceeds a certain value (the conductivity type is reversed). That is, in the structure J1, the effect as in the present embodiment cannot be obtained.

  This is because when the conductivity type (conduction type) of the silicon 11 is inverted (changed) from the P type to the N type, the conductivity type of the entire region in the isolation portion 30 becomes the N type, so that a depletion layer is formed. This is because it cannot be done.

  In the present embodiment, the depth (thickness) of each of the N + layer 3N and the P + layer 3P is 1.0 μm as an example, but is not limited thereto. The depth (thickness) of each of the N + layer 3N and the P + layer 3P may be set in consideration of the depth (thickness) of the second N well 22 where the semiconductor circuit 42 that is susceptible to noise propagation is formed. desirable. Specifically, the depth (thickness) of each of the N + layer 3N and the P + layer 3P may be set to be deeper than the depth (thickness) of the second N well 22 where the semiconductor circuit 42 is formed. desirable.

  As described above, the thickness of each of the N + layer 3N (first conductivity type layer) and the P + layer 3P (second conductivity type layer) is larger than the thickness of the second well 22.

  Generally, in a fine Si-CMOS process, a well layer having a depth (thickness) of about 0.5 μm is used. Therefore, if it is equal to or greater than this depth (thickness), noise propagation can be effectively suppressed.

  Here, an example has been described in which the separation unit 30 as a noise separation region is formed in a straight line between the digital circuit 41 and the semiconductor circuit 42, but is not limited thereto. For example, as shown in FIG. 8, even if each of the N + layer 3N and the P + layer 3P is formed in a comb shape in the separation unit 30, the same effect as in the present embodiment can be obtained.

  In particular, in the RF analog mixed system LSI, since a large-scale digital circuit occupies most of the chip, the semiconductor circuit 42 is easily affected by noise.

  Therefore, for example, as shown in FIG. 9, each of the P + layer 3P and the N + layer 3N may be formed so as to surround the second N well 22 in which the semiconductor circuit 42 is formed.

  That is, each of the first conductivity type layer (P + layer 3P) and the second conductivity type layer (N + layer 3N) is formed so as to surround the second well 22. That is, each of the first conductivity type layer (P + layer 3P) and the second conductivity type layer (N + layer 3N) is formed so as to surround the semiconductor circuit 42.

  With this configuration, noise propagation in which noise (digital noise) generated by the digital circuit propagates to the semiconductor circuit 42 can be further suppressed as compared to the configuration of FIG.

  According to the semiconductor device 1000 according to the present embodiment, the resistance of the semiconductor substrate 10 due to the oxygen concentration in the semiconductor substrate 10 and the influence of the conductivity type inversion are affected without reducing the mechanical strength of the semiconductor substrate 10. It can be made not to receive. As a result, manufacturing variation is small and a high noise propagation suppressing effect can be obtained.

<Modification of the first embodiment>
Note that the separation unit 30 of the first embodiment may have the following structure of the separation unit 30A.

  FIG. 10 is a plan view of a separation unit 30A according to a modification of the first embodiment. The cross-sectional view of the separation part 30A is the same as the cross-sectional view of the separation part 30 in FIG.

  As shown in FIG. 10, in the separation unit 30A, a plurality of N + layers 3N and P + layers 3P are arranged in a matrix.

  Specifically, in the separation part 30A, the second conductivity type layer (N + layer 3N), the first conductivity type material (silicon 11), and the first conductivity type layer (P + layer 3P) are arranged in this order. Arranged side by side in one direction (X direction).

  Further, in the separation portion 30A, the second conductivity type layer (N + layer 3N), the first conductivity type material (silicon 11), and the first conductivity type layer (P + layer 3P) are arranged in this order in the second direction ( Are arranged side by side in the Y direction).

  Each of the plurality of N + layers 3N arranged in the separation part 30A is provided with a contact part C40. Further, each of the plurality of P + layers 3P arranged in the separation part 30A is provided with a contact part C40.

  Similarly to the first embodiment, a PN junction portion, which is a junction portion between the silicon 11 as the first conductivity type material and the N + layer 3N as the second conductivity type layer, is connected to a power supply circuit (not shown). A reverse bias is applied. As a result, a depletion layer is formed in the separation unit 30A, similar to the separation unit 30 of the first embodiment.

  The width d11 of the N + layer 3N in the Y direction (X direction) is 0.2 μm. The width d12 of the P + layer 3P in the Y direction (X direction) is 0.2 μm.

  The peak concentration and depth (thickness in the Z direction) of the impurity concentration in each of the N + layer 3N and the P + layer 3P are the same as those in the first embodiment.

  In addition, the width d13 in the Y direction (X direction) of the silicon 11 (P− silicon layer) between the adjacent N + layer 3N and the P + layer 3P in the separation unit 30A is, for example, 5.0 μm.

  In the example structure shown here, a reverse bias (for example, a voltage of about 3 V) is applied to a PN junction that is a junction between the silicon 11 and the N + layer 3N. Thereby, a depletion layer can be formed in the isolation | separation part 30A in the silicon | silicone 11 similarly to 1st Embodiment.

  When the N + layer 3N, the silicon 11, and the P + layer 3P are arranged as in the separation unit 30 of the first embodiment, the depletion layer extends in two directions. The two directions are two directions parallel to the X direction.

  However, in the separation unit 30A according to the modification of the first embodiment, the direction in which the depletion layer extends is four directions. That is, the depletion layer can be extended in all directions from the N + layer 3N or the P + layer 3P.

  Therefore, a depletion layer equivalent to that of the first embodiment is formed while making the areas of the high concentration (low resistance) N + layer 3N and P + layer 3P occupying the separation part 30A smaller than the separation part 30. Can do.

That is, it is possible to reduce the size of the semiconductor device using the separation unit 30A.
For this reason, the semiconductor device using the separation unit 30A according to the modified example of the first embodiment exhibits an effect equal to or higher than that of the first embodiment with respect to the malfunction due to the generation of oxygen donors. As compared with the first embodiment, an even higher noise propagation suppression effect can be realized.

  In addition, as illustrated in FIG. 11, the separation unit 30A may have a structure in which the N + layers 3N and the P + layers 3P arranged in a matrix are surrounded by the N + layers 31N. With this structure, a more stable depleted region can be formed in the separation portion 30A.

  As described above, the resistance of the semiconductor substrate 10 formed of the P-type silicon 11 is 100 Ωcm or more. If the resistance of the semiconductor substrate 10 is 100 Ωcm or more, the effect of the present invention that the effect of suppressing noise propagation is improved by the synergistic effect of increasing the resistance of the depletion layer and the semiconductor substrate 10 without being affected by oxygen donors. It can be demonstrated.

As described above, the oxygen concentration in the semiconductor substrate 10 is 1.0 × 10 ¹⁸ cm ⁻³ or more.
Further, according to the present invention, it is possible to make it less susceptible to the influence of oxygen donors, but it is desirable that the oxygen concentration be low if the mechanical strength can be secured. For this reason, the oxygen concentration in the semiconductor substrate 10 is desirably 1.7 × 10 ¹⁸ cm ⁻³ or less.

That is, the oxygen concentration in the semiconductor substrate 10 is set to 1.0 × 10 ¹⁸ cm ⁻³ or more and 1.7 × 10 ¹⁸ cm ⁻³ or less.

  In the separation part 30A, the noise suppression effect can be improved as the proportion of the high resistance silicon 11 increases. Therefore, it is preferable that the width d13 of the silicon 11 in the X direction (Y direction) is as large as possible in a range where depletion can be achieved by applying a reverse bias.

  Also in the separation unit 30 of the first embodiment, it is preferable that the width d3 of the silicon 11 in the X direction is as large as possible so that depletion can be achieved by applying a reverse bias.

  In the embodiment of the present invention, a reverse bias is applied to the PN junction, but the present invention is not limited to this. That is, the reverse bias does not have to be applied to the PN junction.

  Since the semiconductor substrate 10 in the present embodiment has a high resistance (impurity concentration is small), the substrate resistance (impurity concentration) of the semiconductor substrate 10 and the concentrations and widths of the N + layer 3N, the P + layer 3P, and the silicon 11 are optimized. By setting the value, a sufficiently large depletion layer can be formed even if no reverse bias is applied to the PN junction, and the noise suppression effect can be improved.

  With the increase in scale and performance of system LSIs, it is necessary to increase the operating frequency of digital circuits. As the operating frequency of the digital circuit increases, the frequency of noise generated increases, and the frequency is reaching several GHz level. The higher the frequency is, the more effective the present invention is because the path through which noise propagates due to the skin effect is concentrated on the substrate surface.

  The N + layer 3N and the P + layer 3P in the present embodiment can be formed simultaneously with the well layers of the P-type and N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In this case, the effect of the present invention can be obtained without adding a process.

  The present invention may be used simultaneously with oxide film separation such as STI. By using in combination with oxide film separation, the effect of noise suppression improvement can be exhibited.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention can be used as a semiconductor device that can stably suppress noise propagation from a digital circuit to another circuit even if the characteristics of the semiconductor substrate change.

C40 contact part 3N, 31N N + layer 3P P + layer 10 semiconductor substrate 11 silicon 21 first N well 22 second N well 30, 30A separation part 41 digital circuit 42 semiconductor circuit 50 insulating film layer 60, 60N depletion layer 1000 semiconductor device

Claims (12)

A semiconductor device in which a digital circuit and a semiconductor circuit are mixedly mounted,
A semiconductor substrate formed of a first conductivity type material;
The digital circuit and the semiconductor circuit are formed to be aligned in a first direction on the semiconductor substrate,
A separation unit is formed between the digital circuit and the semiconductor circuit formed on the semiconductor substrate so as to separate the digital circuit and the semiconductor circuit,
Each of the separation portions is formed with one or more of a first conductivity type layer that is a first conductivity type layer and a second conductivity type layer that is a second conductivity type layer,
The second conductive type layer, the first conductive type material, and the first conductive type layer are arranged in this order in the first direction in the separation unit. Semiconductor device. A first well and a second well of the second conductivity type are independently formed on the semiconductor substrate,
The digital circuit is formed in the first well,
The semiconductor device according to claim 1, wherein the semiconductor circuit is formed in the second well. The semiconductor device according to claim 2, wherein each of the first conductivity type layer and the second conductivity type layer has a thickness greater than that of the second well. The semiconductor device according to claim 2, wherein each of the first conductivity type layer and the second conductivity type layer is formed so as to surround the second well. 5. The semiconductor device according to claim 1, wherein each of the first conductivity type layer and the second conductivity type layer extends along a second direction orthogonal to the first direction. A plurality of each of the first conductivity type layer and the second conductivity type layer are formed in the separation portion,
In the separation portion, the second conductivity type layer, the first conductivity type material, and the first conductivity type layer are arranged in this order in the first direction and the second direction orthogonal to the first direction. The semiconductor device according to claim 1, which is disposed by: The first conductivity type is P type,
The second conductivity type is N-type,
The first conductivity type material and the second conductivity type layer are formed so as to be joined,
The semiconductor device according to claim 1, wherein a reverse bias is applied to a PN junction that is a junction between the first conductivity type material and the second conductivity type layer. The semiconductor device according to claim 1, wherein the resistance of the first conductivity type material is 100 Ωcm or more. The semiconductor device according to claim 1, wherein an oxygen concentration in the semiconductor substrate is 1.0 × 10 ¹⁸ cm ⁻³ or more. The semiconductor device according to claim 1, wherein an oxygen concentration in the semiconductor substrate is 1.7 × 10 ¹⁸ cm ⁻³ or less. The semiconductor device according to claim 1, wherein the semiconductor circuit is an RF (Radio Frequency) circuit or an analog circuit. The semiconductor device according to claim 1, wherein the semiconductor circuit is a circuit including at least one of an RF (Radio Frequency) circuit and an analog circuit.

Images