JP6406585B2 - Imaging device - Google Patents

Description

  The present application relates to an imaging apparatus having a photoelectric conversion film.

  As a MOS (Metal Oxide Semiconductor) type imaging device, a stacked type imaging device has been proposed. In a stacked imaging device, a photoelectric conversion film is stacked on the outermost surface of a semiconductor substrate. Charges generated in the photoelectric conversion film by photoelectric conversion are accumulated in a charge accumulation region (floating diffusion: FD). The stacked imaging device reads out the accumulated electric charge using a CCD (Charge Coupled Device) circuit or a CMOS (Complementary MOS) circuit in a semiconductor substrate. For example, Patent Document 1 discloses a multilayer imaging device.

JP 2009-164604 A

  In the multilayer image sensor described above, it is desired to develop a technique for further reducing the leakage current (hereinafter sometimes referred to as “dark current”). One non-limiting exemplary embodiment of the present application provides a stacked imaging apparatus capable of performing imaging with high image quality while suppressing the influence of dark current.

  In order to solve the above-described problem, an imaging device according to an aspect of the present disclosure includes a plurality of unit pixel cells arranged one-dimensionally or two-dimensionally, and each of the plurality of unit pixel cells includes a first conductivity type first. A first conductivity type region; a second conductivity type first impurity region provided in the first conductivity type region; and a second conductivity type second impurity region provided in the first conductivity type region. A first transistor comprising: a semiconductor substrate; a photoelectric conversion portion located above the semiconductor substrate; a first gate electrode; and at least a part of a second impurity region as one of a source and a drain The first impurity region is partially located on the surface of the semiconductor substrate and is electrically connected to the photoelectric conversion unit, and the second impurity region is photoelectrically converted via the first impurity region. And the impurity concentration of the first impurity region. Have also small impurity concentration, when viewed in a direction perpendicular to the surface of the semiconductor substrate, a first portion of the second impurity region overlaps the second portion of the first gate electrode.

  The comprehensive or specific aspect may be realized by an element, a device, a system, an integrated circuit, and a manufacturing method. A comprehensive or specific aspect may be realized by any combination of an element, a device, a system, an integrated circuit, and a manufacturing method.

  Additional effects and advantages of the disclosed embodiments will become apparent from the specification and drawings. The effects and / or advantages are individually provided by the various embodiments and features disclosed in the specification and drawings, and not all are required to obtain one or more of these.

  According to one embodiment of the present disclosure, it is possible to provide a stacked imaging apparatus capable of performing imaging with high image quality while suppressing the influence of dark current.

1 is a schematic diagram illustrating a circuit configuration of an imaging apparatus 1 according to an exemplary first embodiment. 2 is a schematic cross-sectional view of a unit pixel cell 14 of the imaging device 1 according to the exemplary first embodiment. FIG. 3 is a schematic cross-sectional view in which the vicinity of a reset transistor 12 of a unit pixel cell 14 is enlarged. FIG. It is a graph which shows an example of the profile of the depth direction of the impurity concentration of the semiconductor substrate 31 along the A-A 'line and B-B' line shown to FIG. 3A. FIG. 3 is a top view of a unit pixel cell 14 shown in FIG. 2. 5 is a schematic top view of a unit pixel cell 14 in the manufacturing process of the imaging device 1 according to the exemplary first embodiment. FIG. It is typical sectional drawing along the C-C 'line | wire shown to FIG. 5A. 5 is a schematic top view of a unit pixel cell 14 in the manufacturing process of the imaging device 1 according to the exemplary first embodiment. FIG. FIG. 6B is a schematic sectional view taken along line C-C ′ shown in FIG. 6A. It is a typical sectional view of unit pixel cell 14A of imaging device 1 concerning an exemplary 2nd embodiment. It is a typical sectional view of unit pixel cell 14B of imaging device 1 concerning an exemplary 3rd embodiment. It is a typical sectional view of unit pixel cell 14C of imaging device 1 concerning an exemplary 4th embodiment. It is a schematic diagram which shows the circuit structure of the imaging device 1 which concerns on exemplary 5th Embodiment. It is the typical sectional view which expanded the neighborhood of transfer transistor 70 of unit pixel cell 14D of image pick-up device 1 concerning an exemplary 5th embodiment. It is the typical top view to which the vicinity of FD section and gate electrode 39A of unit pixel cell 14 concerning other exemplary embodiments was expanded. It is a schematic top view showing a layout example of the gate electrode 39A. It is a schematic top view showing a layout example of the gate electrode 39A. It is a schematic top view showing a layout example of the gate electrode 39A. It is a schematic top view showing a layout example of the gate electrode 39A.

  A stacked image sensor requires a contact for transmitting signal charges generated in a photoelectric conversion film by photoelectric conversion to a drive circuit portion provided on a semiconductor substrate. Various pn junctions are formed around the contacts in the semiconductor substrate. Leakage current is generated at these pn junctions. The charge due to the leakage current is indistinguishable from the signal charge generated by the photoelectric conversion, and can be noise. As a result, the performance of the image sensor is degraded.

  In view of such problems, the inventor of the present application has come up with an imaging apparatus having a novel structure.

  Hereinafter, embodiments according to the present disclosure will be described with reference to the drawings. Note that the present disclosure is not limited to the following embodiments. Moreover, it can change suitably in the range which does not deviate from the range which has the effect of this invention. Furthermore, it is possible to combine one embodiment with another embodiment. In the following description, the same or similar components are denoted by the same reference numerals. In addition, overlapping description may be omitted.

(First embodiment)
The structure and function of the imaging apparatus 1 according to the present embodiment will be described with reference to FIGS. 1 to 4.

(Structure of the imaging device 1)
FIG. 1 schematically shows a circuit configuration of an imaging apparatus 1 according to the first embodiment.

  The imaging device 1 is a stacked imaging device. The imaging device 1 includes a plurality of unit pixel cells 14, a drive circuit unit, a photoelectric conversion film control line 16, a plurality of vertical signal lines 17, a power supply wiring 21, and a plurality of feedback lines 23. The plurality of unit pixel cells 14 are two-dimensionally arranged on the semiconductor substrate, that is, in the row direction and the column direction to form a photosensitive region (pixel region). The drive circuit unit sequentially drives the plurality of unit pixel cells 14 and reads signal charges generated by photoelectric conversion. Note that the imaging device 1 may be a line sensor. In that case, the plurality of unit pixel cells 14 are arranged one-dimensionally.

  The drive circuit unit typically includes a vertical scanning unit 15, a horizontal signal reading unit 20, a plurality of column signal processing units 19, a plurality of load units 18, and a plurality of differential amplifiers 22. The vertical scanning unit 15 is also referred to as a row scanning circuit. The horizontal signal reading unit 20 is also referred to as a column scanning circuit. The column signal processing unit 19 is also referred to as a row signal storage unit. The differential amplifier 22 is also referred to as a feedback amplifier.

  Each unit pixel cell 14 includes a photoelectric conversion unit 10, an amplification transistor 11, a reset transistor 12, and an address transistor (row selection transistor) 13. As shown in FIG. 1, the unit pixel cell 14 may further include a burn-in prevention transistor 60. The configuration of the unit pixel cell including the burn-in prevention transistor 60 will be described in Embodiment 3.

  A power supply wiring (source follower power supply) 21 supplies a predetermined power supply voltage to each unit pixel cell 14. The vertical scanning unit 15 is electrically connected to the unit pixel cells 14 arranged in each row via a signal line corresponding to each row. The horizontal signal readout unit 20 is electrically connected to the plurality of column signal processing units 19. The column signal processing unit 19 is electrically connected to the unit pixel cells 14 arranged in each column via the vertical signal line 17 corresponding to each column. The load unit 18 is electrically connected to each vertical signal line 17.

  The plurality of differential amplifiers 22 are provided corresponding to each column. The negative input terminal of the differential amplifier 22 is connected to the corresponding vertical signal line 17. The output terminal of the differential amplifier 22 is connected to the unit pixel cell 14 via a feedback line 23 corresponding to each column.

  The photoelectric conversion unit 10 is electrically connected to the drain electrode of the reset transistor 12 and the gate electrode of the amplification transistor 11 and converts light (incident light) incident on the unit pixel cell 14 into electric charge. The photoelectric conversion unit 10 generates a signal charge corresponding to the amount of incident light.

  The amplification transistor 11 outputs a signal voltage corresponding to the amount of signal charge generated in the photoelectric conversion unit 10. The reset transistor 12 resets (initializes) the signal charge generated by the photoelectric conversion unit 10. In other words, the reset transistor 12 resets the potential of the gate electrode of the amplification transistor 11. More specifically, a reset voltage is applied to the gate electrode of the amplification transistor 11 through the reset transistor 12. The address transistor 13 selectively outputs a signal voltage from the unit pixel cell 14 to the vertical signal line 17. Thus, the output voltage of the amplification transistor 11 is read from the vertical signal line 17 via the address transistor 13.

  The vertical scanning unit 15 applies a row selection signal for controlling on / off of the address transistor 13 to the gate electrode of the address transistor 13. Thereby, the row to be read is scanned in the vertical direction (column direction), and the row to be read is selected. A signal voltage is read out from the unit pixel cell 14 of the selected row to the vertical signal line 17. Further, the vertical scanning unit 15 applies a reset signal for controlling on and off of the reset transistor 12 to the gate electrode of the reset transistor 12. As a result, the row of the unit pixel cell 14 to be reset is selected.

  The photoelectric conversion unit control line 16 is commonly connected to all the unit pixel cells 14. The same positive constant voltage is applied to all the photoelectric conversion units 10 in the imaging apparatus 1 by the photoelectric conversion unit control line 16.

  The vertical signal line 17 is provided corresponding to each column of the unit pixel cells 14. The vertical signal line 17 is connected to the source electrode of the address transistor 13 in the unit pixel cell 14 of the corresponding column. The vertical signal line 17 transmits the signal voltage read from the unit pixel cell 14 in the column direction (vertical direction).

  The load unit 18 is connected to each vertical signal line 17. The load unit 18 and the amplification transistor 11 form a source follower circuit.

  The column signal processing unit 19 performs noise suppression signal processing represented by correlated double sampling, analog-digital conversion (AD conversion), and the like. The column signal processing unit 19 is connected to the vertical signal line 17 corresponding to each column. Thus, the plurality of column signal processing units 19 are arranged in the horizontal direction (row direction).

  The horizontal signal reading unit 20 sequentially reads signals from a plurality of column signal processing units 19 to a horizontal common signal line (not shown).

  The power supply line 21 is connected to the drain electrode of the amplification transistor 11. The power supply wiring 21 is wired in the vertical direction of the unit pixel cell 14 in the photosensitive region (perpendicular to the paper surface of FIG. 1). This is due to the following reason. The unit pixel cell 14 is addressed for each row. For this reason, if the power supply wiring 21 is wired in the row direction, all the pixel drive currents in one row flow through one wiring and the voltage drop increases. A common source follower power supply voltage is applied to the amplification transistors 11 of all the unit pixel cells 14 by the power supply wiring 21.

  The differential amplifier 22 is provided corresponding to each column of the unit pixel cells 14. The output terminal of the differential amplifier 22 is connected to the drain electrode of the reset transistor 12 via the feedback line 23. Therefore, the differential amplifier 22 receives the output value of the address transistor 13 at the negative terminal when the address transistor 13 and the reset transistor 12 are in a conductive state. The differential amplifier 22 performs a feedback operation so that the gate potential of the amplification transistor 11 becomes a predetermined feedback voltage. At this time, the output voltage value of the differential amplifier 22 is 0V or a positive voltage near 0V. The feedback voltage means the output voltage of the differential amplifier 22.

  In the imaging device 1, the unit pixel cells 14 for one row selected by the vertical scanning unit 15 are selected. The signal charge generated by the photoelectric conversion in the photoelectric conversion unit 10 in the selected unit pixel cell 14 is amplified by the amplification transistor 11. The amplified signal is output to the vertical signal line 17 via the address transistor 13.

  The output signal charges are accumulated as electrical signals in the column signal processing unit 19. Thereafter, the accumulated signal charges are selected and output by the horizontal signal reading unit 20. The signal charge in the unit pixel cell 14 is discharged by turning on the reset transistor 12. At that time, a large thermal noise called kTC noise is generated from the reset transistor 12. This thermal noise remains even when the reset transistor 12 is turned off and signal charge accumulation is started.

  In order to suppress this thermal noise, the vertical signal line 17 is connected to the negative input terminal of the differential amplifier 22. The voltage value of the vertical signal line 17, that is, the voltage value to the negative input terminal is inverted and amplified by the differential amplifier 22. The inverted and amplified signal is fed back to the drain electrode of the reset transistor 12 via the feedback line 23. Thereby, thermal noise generated in the reset transistor 12 can be suppressed by negative feedback control. Note that the AC component of thermal noise is fed back to the drain electrode of the reset transistor 12. The direct current component is a positive voltage in the vicinity of 0V as described above.

(Structure of unit pixel cell 14)
FIG. 2 schematically shows a cross section of the unit pixel cell 14 in the imaging apparatus 1 according to the present embodiment. FIG. 2 differs from the actual structure. In FIG. 2, three transistors are shown in one cross section from the viewpoint of simplifying the description.

  The unit pixel cell 14 includes a semiconductor substrate 31, a pixel circuit, an element isolation region 42, interlayer insulating films 43A, 43B, and 43C, and a photoelectric conversion unit 10.

  The semiconductor substrate 31 has a p-type region on the surface. The semiconductor substrate 31 is, for example, a p-type silicon (Si) substrate. The semiconductor substrate 31 may be, for example, an n-type silicon substrate having a p-type well region formed on the surface. The pixel circuit includes an address transistor 13, an amplification transistor 11, and a reset transistor 12 formed on the semiconductor substrate 31. The interlayer insulating films 43A, 43B, and 43C are stacked on the semiconductor substrate 31 in this order. The photoelectric conversion unit 10 includes a pixel electrode 50 formed on the interlayer insulating film 43C, a photoelectric conversion film 51 formed on the pixel electrode 50, and a transparent electrode 52 formed on the photoelectric conversion film 51. . Hereinafter, a structural example using a p-type silicon substrate as the semiconductor substrate 31 will be described.

First, the relationship of the impurity concentration of each p-type impurity region in the semiconductor substrate 31 of the unit pixel cell 14 will be described. The impurity concentration of the p ⁻ -type impurity region 31 a is the lowest among the semiconductor substrates 31. The impurity concentration of the p-type impurity regions 33 and 35 is higher than the impurity concentration of the p ⁻ -type impurity region 31a. The impurity concentrations of the p-type impurity region 33 and the p-type impurity region 35 are approximately the same. The impurity concentration of the p-type impurity region 34 is higher than the impurity concentration of the p-type impurity regions 33 and 35. The impurity concentration of the p-type impurity region 40 is higher than the impurity concentration of the p-type impurity region 34. The impurity concentration of the p-type impurity region 40 is the highest among the above-described p-type impurity regions.

The semiconductor substrate 31 is made of p-type silicon. A p-type impurity region 35 is formed on the surface of the semiconductor substrate 31 except for the p ⁻ -type impurity region 31 a on the drain side of the reset transistor 12. The p-type impurity region 35 functions as a p-well layer.

  A p-type impurity region 33 is formed under the p-type impurity region 35 over the entire surface of the substrate so as to be in contact with the p-type impurity region 35. Under the p-type impurity region 33, an n-type impurity region 32 is formed over the entire surface of the substrate.

  A p-type impurity region 34 is formed in a part of the n-type impurity region 32. The p-type impurity region 34 electrically connects the lowermost layer region 31 b of the semiconductor substrate 31 and the p-type impurity region 33.

  The n-type impurity region 32 prevents minority carriers from flowing from the lowermost layer region 31b of the semiconductor substrate 31 into a floating diffusion (FD) portion (see 24 in FIG. 1) that accumulates signal charges. The potential of the n-type impurity region 32 is controlled through a well contact (not shown) formed in the periphery of the pixel.

  The potentials of the lowermost layer region 31b and the p-type impurity region 33 of the semiconductor substrate 31 are controlled through a substrate contact (not shown) formed in the periphery of the pixel.

  The p-type impurity region 35 is in contact with the p-type impurity region 33 as described above. Therefore, the potential of the p-type impurity region 35 is controlled through the p-type impurity region 33. With such a well structure, it is not necessary to form an in-pixel well around the FD portion. Therefore, the impurity concentration around the FD portion can be lowered. As a result, the pn junction electric field at the boundary of the FD portion can be relaxed. Therefore, an increase in leakage current due to the pn junction electric field strength can be suppressed.

The reset transistor 12 includes a gate insulating film 38A, a gate electrode 39A, a source region, and a drain region. N-type impurity regions 36, 37 and 44 are formed in p ⁻ -type impurity region 31 a and function as the drain region of reset transistor 12. When viewed from a direction perpendicular to the surface of the semiconductor substrate 31, the second n-type impurity region 36 may not overlap with the p-type impurity region 35. An n-type impurity region 41A is formed in the p-type impurity region 35. The n-type impurity region 41A functions as the source region of the reset transistor 12. The impurity concentration of the n-type impurity region 41A is higher than that of the n-type impurity region 36. More specifically, for example, the impurity concentration of the n-type impurity region 41A is 1 × 10 ¹⁸ / cm ³ to 1 × 10 ¹⁹ / cm ³ . The impurity concentration of the n-type impurity region 36 is, for example, 1 × 10 ¹⁷ / cm ³ to 1 × 10 ¹⁸ / cm ³ .

A pn junction is formed between the n-type impurity regions 36, 37, and 44 connected to the pixel electrode 50 and the p ⁻ -type impurity region 31a. The pn junction forms a parasitic diode (storage diode) that stores signal charges. The capacitance of various wirings connected to the storage diode and the pixel electrode 50 is generally called an FD portion.

  The unit pixel cell 14 is provided with a contact plug 45. The contact plug 45 electrically connects the photoelectric conversion unit 10 and the charge storage region (FD unit). The contact plug 45 also accumulates part of the signal charge generated in the photoelectric conversion unit.

  Similar to the reset transistor 12, the amplification transistor 11 includes a gate insulating film 38B, a gate electrode 39B, a source region, and a drain region. The address transistor 13 includes a gate insulating film 38C, a gate electrode 39C, a source region, and a drain region. In the p-type impurity region 35 provided with the amplification transistor 11 and the address transistor 13, n-type impurity regions 41B, 41C, and 41D are formed. The n-type impurity region 41B functions as the drain region of the amplification transistor 11. The n-type impurity region 41 </ b> C functions as the source region of the amplification transistor 11 and the drain region of the address transistor 13. The n-type impurity region 41D functions as the source region of the address transistor 13. In the imaging device 1 of the present embodiment, holes are used as signal charges. In the case of a sensor using electrons as signal charges, the source region and the drain region are reversed.

  The element isolation region 42 insulates and isolates the amplification transistor 11 and the address transistor 13 from the reset transistor 12. The element isolation region 42 is a p-type impurity region. For example, the element isolation region 42 is formed near the surface of the semiconductor substrate 31 and between the amplification transistor 11 and the reset transistor 12. The element isolation region 42 may be formed near the surface of the semiconductor substrate 31 and around the unit pixel cell 14. Further, when viewed from the direction perpendicular to the surface of the semiconductor substrate 31, the element isolation region 42 does not have to overlap the second n-type impurity region 36.

  The n-type impurity region 44 is formed near the surface of the semiconductor substrate 31 and below the contact plug 45. The n-type impurity region 44 includes a high concentration of n-type impurities. Thereby, the spread of the depletion layer formed around the contact surface between the contact plug 45 and the semiconductor substrate 31 is suppressed. By suppressing the spread (depletion) of the depletion layer, it is possible to suppress leakage current caused by lattice defects at the interface between the contact plug 45 and the semiconductor substrate 31. Further, the contact resistance can be reduced.

When viewed from the normal direction of the semiconductor substrate 31, the p-type impurity region 40 is formed on the surface of the semiconductor substrate 31 so that a part of the p ⁻ -type impurity region 31 a on the drain side of the reset transistor 12 enters under the gate. Is formed. However, the p-type impurity region 40 is not necessarily formed depending on design specifications and the like.

  The p-type impurity region 40 suppresses leakage current caused by lattice defects on the surface of the semiconductor substrate 31. Further, when a gate off bias is applied to the reset transistor 12 during signal charge accumulation, the difference in surface potential between the p-type impurity region 40 and the substrate potential can be reduced. Furthermore, it is possible to suppress the concentration of the electric field near the end of the gate electrode 39A on the n-type impurity region 36 side in the vicinity of the surface of the semiconductor substrate 31. As a result, leakage current from the FD portion can be suppressed.

  The n-type impurity region 36 is formed below the p-type impurity region 40 and the n-type impurity region 44 in the depth direction of the semiconductor substrate 31 (normal direction of the semiconductor substrate). The n-type impurity region 36 is formed so as not to be in direct contact with the p-type impurity region 35 in a direction (lateral direction) orthogonal to the depth direction of the semiconductor substrate 31. Thus, the ion implantation depth (range: Rp) of the n-type impurity region 36 and the ion implantation depth of the p-type impurity region 40 are separated from each other in the depth direction. Thereby, the pn junction electric field between the region 36 and the region 40 is relaxed, and the leakage current is suppressed.

  The n-type impurity region 44 is formed near the surface of the semiconductor substrate 31. The n-type impurity region 36 is formed at a deep position below the p-type impurity region 40 and the n-type impurity region 44. As a result, the n-type impurity region 44 and the n-type impurity region 36 are separated from each other, so that the n-type impurity concentration in the region located between the two regions decreases. Therefore, an n-type impurity region 37 is formed. As a result, the n-type impurity region 44 and the n-type impurity region 36 are electrically connected, and the decrease in the n-type impurity concentration in the region between the two regions is suppressed. Further, the n-type impurity region 37 allows the n-type impurity region 36 to be formed at a deeper position from the surface of the semiconductor substrate 31.

  The n-type impurity region 44 and the p-type impurity region 40 under the gate electrode 39A are formed at a distance from each other. Thereby, the pn junction electric field between both regions is relaxed, and the leakage current is suppressed.

  FIG. 3A shows a cross section of the imaging apparatus 1 in which the vicinity of the reset transistor 12 is enlarged. FIG. 3B shows an example of an impurity concentration profile in the depth direction along the cross-section A-A ′ line and the cross-section B-B ′ line of the drain region shown in FIG. 3A.

  The horizontal axis in FIG. 3B indicates the distance in the depth direction of the substrate, and the vertical axis indicates the impurity concentration. The range Rp means the depth at which the peak value of the impurity concentration is obtained. In the direction along the section A-A ′ line, Rp is confirmed from the surface of the semiconductor substrate 31 in the order of the n-type impurity region 44, the n-type impurity region 37, and the n-type impurity region 36. The depth at which the peak value of the impurity concentration of the n-type impurity region 36 is obtained is deeper than the depth at which the peak value of the impurity concentration of the n-type impurity regions 37 and 44 is obtained.

  In the direction along the line B-B ′, Rp is confirmed from the surface of the semiconductor substrate 31 in the order of the p-type impurity region 40 and the n-type impurity region 36. The depth at which the peak value of the impurity concentration of the n-type impurity region 36 is obtained is deeper than the depth at which the peak value of the impurity concentration of the p-type impurity region 40 is obtained. Thus, the positions where the peak value of the impurity concentration is obtained between the p-type impurity region 40 and the n-type impurity region 36, that is, Rp are separated from each other. Thereby, the impurity concentration (hereinafter referred to as “junction concentration”) at the position (depth) where the waveform indicating the impurity concentration of the p-type impurity region 40 and the waveform indicating the impurity concentration of the n-type impurity region 36 intersect. Can be lowered. Thereby, leakage current can be suppressed.

In the impurity profile, the peak value of the impurity concentration of the n-type impurity region 44 is larger than the peak value of the impurity concentration of the n-type impurity region 36, and the peak value of the impurity concentration of the n-type impurity region 44 is n It is larger than the peak value of the impurity concentration of the type impurity region 37. For example, the peak value of the impurity concentration of the n-type impurity region 44 is 6 × 10 ¹⁸ / cm ³ . The peak value of the impurity concentration of the p-type impurity region 40 is 2 × 10 ¹⁷ / cm ³ . The peak value of the impurity concentration of the n-type impurity region 36 is 3 × 10 ¹⁷ / cm ³ . The peak value of the impurity concentration of the n-type impurity region 37 is 5 × 10 ¹⁷ / cm ³ . The junction concentration between the p-type impurity region 40 and the n-type impurity region 36 is desirably 1.0 × 10 ¹⁷ / cm ³ or less.

In FIG. 3A, a region where a predetermined impurity concentration is obtained is conceptually shown as a rectangular region as an n-type impurity region 36 on the basis of the depth at which the peak value of the impurity concentration is obtained. However, actually, as shown in FIG. 3B, the n-type impurity region 36 is also formed on the surface of the semiconductor substrate 31, although the impurity concentration is lower than that near the center of the semiconductor substrate 31. Therefore, in this embodiment, two pn junctions are formed on the surface of the semiconductor substrate 31 on the drain side under the gate electrode 39A of the reset transistor 12. In the drain-side region under the gate electrode 39A, it is confirmed that the conductivity type is pnp in the order of the p-type impurity region 40, the n-type impurity region 36, and the p ⁻ -type impurity region 31a in the lateral impurity concentration profile. Is done. Thus, the gate oxide film 38A and the pn junction are in contact with each other. Thereby, leakage current can be suppressed.

Note that the n-type impurity region 36 may not be formed up to the surface of the semiconductor substrate 31. That is, as shown in FIG. 3A, the n-type impurity region 36 and the gate electrode 39A may be separated in the depth direction with the gate insulating film 38A and the p ⁻ -type impurity region interposed therebetween. As a result, the pn junction (depletion region) formed between the n-type impurity region 36 and the p-type impurity region 40 can be prevented from being exposed to the substrate surface, and the leakage current caused by the interface state can be reduced. Increase can be suppressed.

  Reference is again made to FIG. The amplification transistor 11 has a gate electrode 39B connected to the pixel electrode 50 through a contact plug 45. The amplification transistor 11 outputs a signal voltage corresponding to the potential of the pixel electrode 50.

  The reset transistor 12 is connected to the pixel electrode 50 via the contact plug 45. The reset transistor 12 resets the potential of the gate electrode 39B of the amplification transistor 11 to a reset voltage, that is, a feedback voltage.

  The address transistor 13 is provided between the amplification transistor 11 and a vertical signal line 17 (not shown). The address transistor 13 outputs a signal voltage from the unit pixel cell 14 to the vertical signal line 17. In the present embodiment, the address transistor 13 is inserted between the source region of the amplification transistor 11 and the vertical signal line 17. However, the present disclosure is not limited to this, and the address transistor 13 may be inserted between the drain region of the amplification transistor 11 and the power supply wiring 21.

  The gate electrode 39B of the amplification transistor 11 and the pixel electrode 50 are connected via a contact plug 45, a wiring 46A, a plug 47A, a wiring 46B, a plug 47B, a wiring 46C, and a plug 47C. Similarly, the drain region (n-type impurity regions 44, 37 and 36) of the reset transistor 12 and the pixel electrode 50 are connected via a contact plug 45, a wiring 46A, a plug 47A, a wiring 46B, a plug 47B, a wiring 46C and a plug 47C. Connected.

  In FIG. 2, contact plugs connected to the source-side n-type impurity region 41D of the address transistor 13 and the source-side n-type impurity region 41A are omitted. Actually, the n-type impurity region 41D is connected to the vertical signal line 17 through a contact plug and a wiring. The n-type impurity region 41A is connected to the feedback line 23 through a contact plug and a wiring.

  The photoelectric conversion film 51 can be formed of, for example, an organic material or amorphous silicon. The photoelectric conversion film 51 is stacked above the semiconductor substrate 31. The photoelectric conversion film 51 converts incident light from the outside into signal charges. The pixel electrode 50 is formed in contact with the surface of the photoelectric conversion film 51 on the semiconductor substrate 31 side. The pixel electrode 50 collects signal charges generated in the photoelectric conversion film 51. The transparent electrode 52 is formed in contact with the surface of the photoelectric conversion film 51 that faces the pixel electrode 50. A positive constant voltage is applied to the transparent electrode 52 via the photoelectric conversion unit control line 16. Thereby, the signal charges generated in the photoelectric conversion film 51 can be read out to the pixel electrode 50.

  FIG. 4 is a top view of the unit pixel cell 14 shown in FIG. FIG. 2 schematically shows a cross section of the unit pixel cell 14 along the line C-C ′ in FIG. 4.

  By separating the end of the n-type impurity region 36 from the p-type impurity region 35 in the lateral direction, the pn junction electric field between the two regions is relaxed and the leakage current is suppressed.

  As described above, in order to suppress electric field concentration, the p-type impurity region 40 overlaps with a part of the region where the n-type impurity region 36 and the gate electrode 39A overlap when viewed from the normal direction of the substrate. Forming. On the other hand, the drivability of the reset transistor 12 may be reduced due to the influence of the p-type impurity region 40 disposed between the gate electrode 39A and the n-type impurity region 36. Therefore, in order to ensure the driving power of the reset transistor 12, the n-type impurity region 36 is a region where a part of the n-type impurity region 36 overlaps the gate electrode 39A without passing through the p-type impurity region 40 when viewed from the normal direction of the substrate. Is ensured. With such a configuration, the junction electric field around the FD portion can be relaxed. Furthermore, since the on-current (reset operation) of the reset transistor 12 can be secured, it is possible to prevent the saturation signal amount from being lowered due to a reset failure. As described above, both reduction of the leakage current and securing of the on-current of the reset transistor 12 can be achieved.

(Manufacturing method of the imaging device 1)
An example of a method for manufacturing the imaging device 1 will be described with reference to FIGS. 5A, 5B, 6A, and 6B. Note that the imaging device 1 can be manufactured by widely using various methods used in the conventional method for manufacturing a stacked imaging device. Hereinafter, detailed descriptions of known methods are omitted.

  5A and 6A are schematic top views of one unit pixel cell 14. FIG. 5B is a schematic cross-sectional view taken along line C-C ′ in FIG. 5A. 6B is a schematic cross-sectional view taken along line C-C ′ in FIG. 6A.

  First, as shown in FIGS. 5A and 5B, for example, a resist is applied to the surface of a semiconductor substrate 31 of p-type silicon. A pixel region is formed on the semiconductor substrate 31 by a lithography method using a mask that opens the pixel region (not shown). An n-type impurity region 32 is formed by ion-implanting n-type impurity ions into the pixel region under predetermined implantation conditions.

  Subsequently, p-type impurity regions 33 are formed by ion implantation of p-type impurity ions. Next, p-type impurity regions 34 are formed by ion-implanting p-type impurity ions using a resist pattern opening a part of the pixel region as a mask. As a result, a part of the n-type impurity region 32 is inverted to the p-type region, and the lowermost layer region 31 b of the semiconductor substrate 31 and the p-type impurity region 33 are connected by the p-type impurity region 34. Here, the p-type impurity ion concentration for forming the p-type impurity region 34 is set to be higher than the n-type impurity ion concentration for forming the n-type impurity region 32.

  Next, p-type impurity ions are ion-implanted into the opening region using the resist pattern opening the region excluding the FD portion as a mask. Thereby, the p-type impurity region 35 is formed. At that time, the upper surface of the p-type impurity region 33 and the lower surface of the p-type impurity region 35 are in contact with each other. As a result, the potential of the p-type impurity region 35 is the same as the potential applied to the lowermost layer region 31 b of the semiconductor substrate 31.

  Next, n-type impurity ions are ion-implanted into the opening region using a resist pattern opening a part of the pixel region as a mask. Thereby, an n-type impurity region 36 to be an FD portion is formed. Subsequently, n-type impurity ions are ion-implanted into the opening region using a resist pattern opening a part of the pixel region as a mask. Thereby, an n-type impurity region 37 is formed. At this time, Rp of the n-type impurity region 36 is set to be shallower than Rp of the p-type impurity region 33. By forming the n-type impurity region 36 and the p-type impurity region 33 apart from each other, the pn junction electric field formed by the n-type impurity region 36 and the p-type impurity region 33 is relaxed. Further, the Rp of the n-type impurity region 37 is set to be shallower than that of the n-type impurity region 36.

  As described above, the n-type impurity region 36 to be the FD portion is formed away from the p-type impurity region 33 in the depth direction of the substrate. Further, the n-type impurity region 36 is formed away from the p-type impurity region 35 in the lateral direction. Thereby, the pn junction electric field around the FD portion is relaxed, and the leakage current can be reduced.

  Next, a resist pattern (not shown) that opens the channel regions of the transistors 11, 12, and 13 of the pixel circuit is formed by lithography. Thereafter, each channel region is formed by ion-implanting p-type or n-type impurity ions under predetermined implantation conditions (not shown). Thereby, a desired threshold voltage can be obtained for each transistor of the pixel circuit. A channel region is a region between a source region and a drain region and is covered with a gate electrode.

  Next, as shown in FIG. 6B, the surface of the semiconductor substrate 31 is oxidized by, for example, an ISSG (In Situ Steam Generation) method. Thereby, an insulating film (not shown) made of silicon oxide is formed. Subsequently, a film made of, for example, polysilicon is formed on the insulating film by chemical vapor deposition (CVD). Thereafter, a resist pattern for forming a gate electrode is formed on the polysilicon film by lithography.

  Subsequently, using the resist pattern as a mask, the insulating film made of silicon oxide and the film made of polysilicon are dry-etched. Thereby, gate electrodes 39A, 39B, 39C and gate insulating films 38A, 38B, 38C are formed.

  Next, a resist pattern for masking the source / drain regions of each transistor in the pixel circuit is formed by lithography, and thereafter, p-type impurity ions are implanted into regions other than the source / drain regions under predetermined implantation conditions. Thereby, the element isolation region 42 is formed. At this time, p-type impurity ions are not implanted immediately below the gate electrodes 39A, 39B, and 39C. Therefore, the element isolation region 42 is provided so as to surround the source / drain region and the channel region.

  Next, as shown in FIG. 6A, a resist pattern is formed to open the region 40 including the drain side end of the gate electrode 39A. Using this resist pattern as a mask, p-type impurity ions are implanted under predetermined implantation conditions. Thereby, the p-type impurity region 40 is formed.

  As shown in FIG. 3B, the Rp of the p-type impurity region 40 is set to be shallower than the Rp of the n-type impurity region 36. The p-type impurity region 40 is also formed below the gate insulating film 38A by the diffusion of the implanted p-type impurity ions. When implanting p-type impurity ions, so-called angular implantation may be performed so as to form a predetermined angle with respect to the substrate surface. By this angle implantation, the size of the p-type impurity region formed below the gate insulating film 38A may be controlled.

  Next, a resist pattern that opens the source formation region and the drain formation region of each transistor of the pixel circuit is formed by lithography. Through this resist pattern, n-type impurity ions are implanted under predetermined implantation conditions. Thereby, n-type impurity regions 41A, 41B, 41C, and 41D are formed, respectively. At this time, so-called gate implantation in which n-type impurity ions are implanted also into each of the gate electrodes 39A, 39B, and 39C may be performed.

  Next, as shown in FIG. 2, an interlayer insulating film made of, for example, silicon oxide is laminated on the semiconductor substrate 31 so as to cover the gate electrodes 39A, 39B, and 39C by the CVD method. Thereafter, a resist pattern for forming a contact hole is formed on the interlayer insulating film by lithography. Dry etching is performed using the formed resist pattern as a mask. As a result, contact holes connected to the gate electrodes 39A, 39B, 39C and the n-type impurity regions 41A, 41B, 41D, 37 are formed.

Subsequently, n-type impurity ions are implanted through the formed contact holes. As a result, an n ⁺ -type impurity region 44 is formed above the n-type impurity region 37. Further, n ⁺ -type impurity regions are also formed on the gate electrodes 39A, 39B, 39C and the n-type impurity regions 41A, 41B, 41D exposed from the contact holes (not shown).

Subsequently, annealing for activating the implanted impurity ions is performed to reduce the resistance of each. Then, a polysilicon film containing n ⁺ -type impurities is deposited on the interlayer insulating film so as to bury each contact hole by CVD or the like. Thereafter, the deposited polysilicon film is etched back or polished by a chemical mechanical polishing (CMP) method. Thereby, each contact plug 45 is formed (the contact plugs 45 on the gate electrodes 39A, 39C and the n-type impurity regions 41A, 41B, 41D are not shown).

  Next, the wiring 46A, the contact plug 47A, the wiring 46B, the contact plug 47B, the wiring 46C, and the contact plug 47C are stacked above the semiconductor substrate 31 while the interlayer insulating films 43A, 43B, and 43C are stacked. Sequentially formed. The contact plug 45 is connected to the wiring 46A. The wiring 46A is connected to the contact plug 47A. The contact plug 47A is connected to the wiring 46B. The wiring 46B is connected to the contact plug 47B. The contact plug 47B is connected to the wiring 46C. The wiring 46C is connected to the contact plug 47C. The contact plug 47C is connected to the pixel electrode 50.

  Next, a pixel electrode 50, a photoelectric conversion film 51, a transparent electrode 52, a protective film (not shown), a color filter (not shown) and a lens (not shown) connected to the contact plug 47C are formed on the interlayer insulating film 43C. Form in order.

  Through the above steps, the imaging device 1 shown in FIG. 1 is manufactured. As the n-type impurity, for example, phosphorus, arsenic, antimony, or the like can be used. For example, boron and indium can be used as the p-type impurity. In addition, as a material for each electrode and each wiring of the unit pixel cell 14, a material generally used for manufacturing a silicon semiconductor device can be widely used.

In the present embodiment, the p ⁻ type impurity region 31a exemplifies a first conductivity type region. The n-type impurity region 44 exemplifies a first impurity region. The n-type impurity region 36 exemplifies the second impurity region. The reset transistor 12 illustrates a first transistor.

(Second Embodiment)
The imaging device 1 according to the present embodiment will be described with reference to FIG. The imaging apparatus 1 according to the present embodiment includes a unit pixel cell 14A illustrated in FIG. 7 instead of the unit pixel cell 14 illustrated in FIG. The unit pixel cell 14A is different from the unit pixel cell 14 shown in FIG. 2 in that a p-type impurity region 40A is formed in the surface region of the semiconductor substrate 31. The following description will focus on differences from the first embodiment, and a detailed description of common points will be omitted.

  FIG. 7 schematically shows a cross section of the unit pixel cell 14A in the imaging apparatus 1 according to the present embodiment.

  Near the surface of the semiconductor substrate 31, a p-type impurity region 40 </ b> A is formed around the n-type impurity region 44 so as to be adjacent to the p-type impurity region 40. The impurity concentration of the p-type impurity region 40 </ b> A is a concentration that prevents depletion of the surface of the semiconductor substrate 31, and is lower than the impurity concentration of the p-type impurity region 40.

  In the present embodiment, a p-type impurity region 40A is formed near the surface of the semiconductor substrate 31 in the FD portion. Thereby, the leakage current resulting from lattice defects on the surface of the semiconductor substrate 31 can be more efficiently suppressed. In the present embodiment, the p-type impurity region 40A is formed away from the high-concentration n-type impurity region 44 below the contact plug 45. Therefore, the pn junction electric field formed by n type impurity region 44 and p type impurity region 40A can be relaxed, and the leakage current can be suppressed.

  Note that the difference in the manufacturing method between the imaging device of the present embodiment and the imaging device of the first embodiment is that the lithography method and the ion implantation method are used before or after the p-type impurity region 40 is formed. This is a point of forming a type impurity region 40A. The other steps are the same as those in the manufacturing method described in the first embodiment.

(Third embodiment)
The imaging device 1 according to the present embodiment will be described with reference to FIG. The imaging device 1 according to the present embodiment includes a unit pixel cell 14B illustrated in FIG. 8 instead of the unit pixel cell 14 illustrated in FIG. The unit pixel cell 14B is different from the unit pixel cell 14 in that the burn-in prevention transistor 60 is formed on the semiconductor substrate 31. The following description will focus on differences from the first embodiment, and a detailed description of common points will be omitted.

  FIG. 8 schematically shows a cross section of the unit pixel cell 14B in the imaging apparatus 1 according to the present embodiment.

  A burn-in prevention transistor 60 is formed on the semiconductor substrate 31. The burn-in prevention transistor 60 includes a gate electrode 39D, a source region, and a drain region. As shown in FIGS. 1 and 8, the FD portion functions as a drain region of the burn-in prevention transistor 60. The FD portion also functions as the drain region of the reset transistor 12. Thus, in both transistors, the n-type impurity regions 36, 37 and 44 are shared as the drain region. The gate electrode 39D of the burn-in prevention transistor 60 is formed on the semiconductor substrate 31 via the gate insulating film 38D. The n-type impurity region 41E is formed on the surface of the semiconductor substrate 31. The n-type impurity region 41E functions as a source region of the burn-in prevention transistor 60.

  Similar to the p-type impurity region 40, the p-type impurity region 61 is formed in a region on the drain side of the burn-in prevention transistor 60 (a region where the n-type impurity region 36 is formed). The p-type impurity region 61 is formed on the surface of the semiconductor substrate 31 so that a part thereof enters under the gate electrode 39D. As described above, by providing the p-type impurity region 61 at the end of the gate electrode 39D on the n-type impurity region 36 side, leakage current due to lattice defects on the surface of the semiconductor substrate 31 can be suppressed.

  Similar to the reset transistor 12, the n-type impurity region 36 and the p-type impurity region 35 are laterally separated in the region under the gate electrode 39 </ b> D of the burn-in prevention transistor 60. Thereby, the pn junction electric field between both regions is relaxed, and the leakage current is suppressed. Further, the depth of ion implantation of the n-type impurity region 36 and the depth of ion implantation of the p-type impurity region 61 are separated in the depth direction. Thereby, the pn junction electric field between both regions is relaxed, and the leakage current is suppressed. Further, a part of the gate electrode 39 </ b> D may overlap with a part of the n-type impurity region 36 when viewed from the normal direction of the semiconductor substrate 31.

  When excessive light is incident on the photoelectric conversion film 51, the potential of the FD portion rises to the same level as the bias voltage applied to the transparent electrode 52. When such an overvoltage is applied to the FD portion, the FD portion or the gate insulating film 38B of the amplification transistor 11 may be destroyed. When the FD portion or the gate insulating film 38B is destroyed, a failure such as burn-in occurs.

  As described above, the drain region and the gate region of the burn-in prevention transistor 60 are connected to the FD portion. As shown in FIG. 1, the source region is connected to the VDD wiring or the power line 62 dedicated to the burn-in prevention transistor 60. It is assumed that light enters the photoelectric conversion film 51 and the potential of the FD portion exceeds VDD. In that case, by setting a threshold value so that the burn-in prevention transistor 60 is turned on, excess charge can be released to the power supply line 62. As a result, failures such as burn-in can be prevented.

  According to this embodiment, dark current can be suppressed, and failure of each transistor can be prevented even when excessive light is incident.

(Fourth embodiment)
The imaging device 1 according to the present embodiment will be described with reference to FIG. The imaging apparatus 1 according to the present embodiment includes a unit pixel cell 14C illustrated in FIG. 9 instead of the unit pixel cell 14 illustrated in FIG. The unit pixel cell 14C is different from the unit pixel cell 14 in that the drain side structure of the reset transistor 12 is also applied to the source side. The following description will focus on differences from the first embodiment, and a detailed description of common points will be omitted.

  FIG. 9 schematically shows a cross section of the unit pixel cell 14C in the imaging apparatus 1 according to the present embodiment.

  In the region on the source side of the reset transistor 12, instead of the p-type impurity region 35 and the n-type impurity region 41A, a p-type impurity region 31a, a p-type impurity region 40, and n-type impurity regions 36, 37, and 44 are formed. Has been. The impurity profile of each impurity region in the source side region can be the same as that of each impurity region in the drain side region described above.

  According to the present embodiment, the same effect as that of the drain side region can be obtained also in the source side region. Further, the low leak structure can be applied to the source side region without increasing the number of manufacturing steps. Thereby, development to various drive methods and circuit configurations becomes possible.

(Fifth embodiment)
The imaging device 1 according to the present embodiment will be described with reference to FIGS. 10 and 11. The unit pixel cell 14D of the imaging device 1 according to the present embodiment is different from the unit pixel cell 14 in that the unit pixel cell 14D includes a transistor (hereinafter referred to as “transfer transistor 70”) connected in series to the reset transistor 12. Is different. The following description will focus on differences from the first embodiment, and a detailed description of common points will be omitted.

  FIG. 10 schematically shows a circuit configuration of the imaging apparatus 1 according to the fifth embodiment. In the unit pixel cell 14D, the transfer transistor 70 is disposed between the FD unit 24 and the reset transistor 12. The drain electrode of the transfer transistor 70 is electrically connected to the gate electrode of the amplification transistor 11. The source electrode of the transfer transistor 70 is electrically connected to the drain electrode of the reset transistor 12. Thus, a reset circuit can be realized by the reset transistor 12 and the transfer transistor 70. The vertical scanning unit 15 controls the gate voltage of the transfer transistor 70 via the control line.

FIG. 11 schematically shows a cross section of the unit pixel cell 14D with the vicinity of the transfer transistor 70 enlarged. The n-type impurity regions 36, 37 and 44 function as the drain region of the transfer transistor 70. The relationship between the position of each impurity region and the impurity concentration in the p ⁻ -type impurity region 31a on the drain side of the transfer transistor 70 is as described in the first embodiment.

  According to the present embodiment, since the reset operation and the charge accumulation operation can be separated by the transfer transistor 70, the reset operation can be stabilized and speeded up.

(Other embodiments)
A layout example of the gate electrode 39A of the reset transistor 12 different from the layout shown in FIG. 4 will be described with reference to FIGS. 12A to 12E.

  FIG. 12A is a top view of the unit pixel cell 14 in which the vicinity of the FD portion and the gate electrode 39A is enlarged from the normal direction of the semiconductor substrate 31. FIG. Note that the illustrated FD portion is mainly the n-type impurity region 36. For simplification, the p-type impurity region 40 is not shown. In this layout example, when viewed from the normal direction of the semiconductor substrate 31, the width W1 of the gate electrode 39A is equal to the width W2 of the FD portion in the direction that defines the gate width of the reset transistor 12 (x-axis direction in the figure). Bigger than. For example, as shown in the drawing, the gate electrode 39A can be arranged so that a part thereof overlaps with the p-type impurity region 35. As a result, the width W1 of the electrode 39A is sufficiently larger than the width W2 of the FD portion. Further, as described above, the end portion of the FD portion is spaced apart from the p-type impurity region 35 in the lateral direction.

  Conventionally, when the FD portion is depleted, a so-called narrow channel effect is manifested in the reset transistor 12, and it has been difficult to ensure the operation of the transistor. In addition, there is a problem that the accuracy of the feedback operation is reduced due to the parasitic capacitance between the FD portion and the p-type impurity region 35.

According to this layout example, the following effects are specifically obtained.
(1) Depletion of the FD portion is suppressed, and as a result, the narrow channel effect can be significantly suppressed.
(2) The parasitic resistance of the FD portion is reduced, and it is possible to suppress a decrease in the driving force of the reset transistor 12.
(3) The depletion layer around the FD portion expands to a region between the FD portion and the p-type impurity region 35 (that is, the p ⁻ -type impurity region 31a). Current is suppressed.
(4) The parasitic capacitance around the FD portion can be reduced, and the coupling capacitance between the gate electrode 39A of the reset transistor 12 and the FD portion is enhanced, so that the accuracy of the feedback operation can be improved.

  12B to 12E show variations of the layout of the gate electrode 39A. 12B to 12E also show the n-type impurity region 41A on the source side of the reset transistor 12. As described above, as long as the gate width W1 of the gate electrode 39A on the FD portion side is sufficiently larger than the width W2 of the FD portion in the same direction as the gate width W1, the gate electrode 39A can have various shapes. For example, the gate electrode 39A may have a notch shape.

The source side of the reset transistor 12 is not limited to the n-type impurity region 41A, and an FD portion may be disposed as illustrated in FIG. In this case, any or all of the concentration, the width of the FD portion, and the length of the FD portion (the length in the y-axis direction in FIG. 12A) between the FD portions on the drain side and the source side of the reset transistor 12 It may be different. Further, layouts in which the distance between the end of the FD portion in the p ⁻ -type impurity region 31a and the p-type impurity region 35 is different may be combined.

  The present disclosure further includes the following imaging device and manufacturing method.

[Item 1]
When viewed from the normal direction of the semiconductor substrate, the width of the gate electrode may be larger than the width of the second impurity region in the direction defining the gate width of the reset transistor.
Thereby, the narrow channel effect can be significantly suppressed. In addition, it is possible to suppress a decrease in the driving power of the reset transistor.
[Item 2]
When viewed from the normal direction of the semiconductor substrate, the gate electrode may be formed so as to at least partially overlap the pixel well region of the first conductivity type.
Thereby, variations of the gate electrode can be provided.
[Item 3]
When viewed from the normal direction of the semiconductor substrate, the gate electrode may have a notch shape.
Thereby, variations of the gate electrode can be provided.
[Item 4]
Implanting a second conductivity type impurity into the first conductivity type semiconductor substrate to form a second conductivity type second impurity region;
Forming a gate electrode of a reset transistor on a semiconductor substrate;
Forming a third impurity region of the first conductivity type on the surface of the semiconductor substrate so as to overlap at least part of a region where the gate electrode and the second impurity region overlap after forming the gate electrode;
Forming a first impurity region of the second conductivity type on the surface of the semiconductor substrate so as not to overlap with the third impurity region when viewed from the normal direction of the semiconductor substrate. It may be.
According to this manufacturing method, it is possible to provide an imaging apparatus that can perform imaging with high image quality while suppressing the influence of dark current.
[Item 5]
In the above manufacturing method, before the gate electrode is formed, the second conductivity type impurity is implanted to electrically connect the first impurity region and the second impurity region. The method may further include forming a fourth impurity region.
Accordingly, since the second impurity region can be formed at a deeper position of the semiconductor substrate, it is possible to provide an imaging device in which the pn junction electric field is relaxed and the leakage current is suppressed.

  An imaging device and a manufacturing method thereof according to the present disclosure are useful for an image sensor used in an imaging device typified by a digital camera and the manufacturing thereof.

DESCRIPTION OF SYMBOLS 1 Imaging device 10 Photoelectric conversion part 11 Amplification transistor 12 Reset transistor 13 Address transistor 14, 14A, 14B, 14C Unit pixel cell 15 Vertical scanning part 16 Photoelectric conversion film control line 17 Vertical signal line 18 Load part 19 Column signal processing part 20 Horizontal Signal readout section 21 Power supply wiring 22 Differential amplifier 23 Feedback line 24 Floating diffusion 31 Semiconductor substrate 32 n-type impurity region 33 p-type impurity region 34 p-type impurity region 35 p-type impurity region 36 n-type impurity region 37 n-type impurity region 38A , 38B, 38C, 38D Gate insulating film 39A, 39B, 39C, 39D Gate electrode 40 p-type impurity region 40A p-type impurity region 41A, 41B, 41C, 41D, 41E n-type impurity region 42 element isolation region 43A , 43B, 43C Interlayer insulating film 44 n-type impurity region 45 contact plug 46A, 46B, 46C wiring 47A, 47B, 47C plug 50 pixel electrode 51 photoelectric conversion film 52 transparent electrode 60 burn-in prevention transistor 61 p-type impurity region 62 power supply line 70 Transfer transistor

Claims (18)

Comprising a plurality of unit pixel cells arranged in one or two dimensions,
Each of the plurality of unit pixel cells is
A first conductivity type region of a first conductivity type; a first region adjacent to the first conductivity type region and containing a first conductivity type impurity having a concentration higher than that of the first conductivity type region; A semiconductor substrate comprising: a first impurity region of a second conductivity type provided in the first conductivity type region; and a second impurity region of a second conductivity type provided in the first conductivity type region; ,
A photoelectric conversion unit located above the semiconductor substrate;
A first transistor including a first gate electrode and at least a portion of the second impurity region as one of a source or a drain;
With
A part of the first impurity region is located on the surface of the semiconductor substrate, and is electrically connected to the photoelectric conversion unit,
The second impurity region is electrically connected to the photoelectric conversion unit via the first impurity region, and has an impurity concentration lower than the impurity concentration of the first impurity region,
When viewed from a direction perpendicular to the surface of the semiconductor substrate, the first portion of the second impurity region overlaps the second portion of the first gate electrode ;
The imaging device , wherein when viewed from the direction, at least a part of the first region overlaps the first gate electrode .   The imaging device according to claim 1, wherein the first portion and the second portion are separated in the direction with the first conductivity type region interposed therebetween. Through the first transistor, a reset voltage to initialize the photoelectric conversion unit, the applied to the photoelectric conversion unit, an imaging apparatus according to claim 1 or 2. The first transistor is a reset transistor;
The imaging device according to any one of claims 1 to 3 . The semiconductor substrate further includes a third impurity region of the first conductivity type, a part of which is located on a surface of the semiconductor substrate,
When viewed from the direction , the third portion of the third impurity region overlaps with the end of the first gate electrode on the second impurity region side,
The imaging device according to claim 1, wherein an impurity concentration of the third impurity region is higher than an impurity concentration of the first region . In the profile of the impurity concentration in the depth direction from the surface of the semiconductor substrate, the second depth at which the impurity concentration of the second impurity region is maximized is the first concentration at which the impurity concentration of the third impurity region is maximized. The imaging device according to claim 5, wherein the imaging device is deeper than three. The imaging device according to claim 6 , wherein in the profile, the second depth is deeper than the first depth at which the impurity concentration of the first impurity region is maximized. The semiconductor substrate further includes a fourth impurity region of the second conductivity type provided in the first conductivity type region, which electrically connects the first impurity region and the second impurity region. The imaging device according to claim 6 or 7 . In the profile, the peak value of the impurity concentration of the first impurity region is larger than the maximum value of the impurity concentration of the second impurity region,
The imaging device according to claim 8 , wherein a maximum value of the impurity concentration of the first impurity region is larger than a maximum value of the impurity concentration of the fourth impurity region. When viewed from the direction, the third portion of the third impurity region is overlapped with at least a portion of said second portion of said first gate electrode, any one of claims 5 to 9 The imaging device described in 1. 11. The imaging device according to claim 1, wherein the semiconductor substrate further includes an isolation region of the first conductivity type that does not overlap with the second impurity region when viewed from the direction. When viewed from the front SL direction, the first region has a overlap the second impurity region, an imaging apparatus according to claim 1. The semiconductor substrate is
Said first located under conductivity type region and the first region, the first conductivity type region and the contact with the first region, the fifth impurity region of the first conductivity type,
A sixth impurity region of the second conductivity type located under the fifth impurity region and in contact with the fifth impurity region;
A seventh impurity region of the first conductivity type located under the sixth impurity region and in contact with the sixth impurity region;
The eighth impurity of the first conductivity type, located between the fifth impurity region and the seventh impurity region, and electrically connecting the fifth impurity region and the seventh impurity region; An impurity region;
The imaging device according to any one of claims 1 to 12 , further comprising: The third impurity region, the second impurity region, and the first conductivity type region are adjacent to each other on the surface of the semiconductor substrate under the first gate electrode, and two pn junctions are formed. Item 11. The imaging device according to any one of Items 5 to 10 . Each of the plurality of unit pixel cells is
A second transistor including a second gate electrode and at least a part of the second impurity region as one of a source and a drain;
The second gate electrode is electrically connected to the first impurity region;
The imaging according to any one of claims 1 to 14 , wherein when viewed from the direction, the fourth portion of the second impurity region overlaps with the fifth portion of the second gate electrode. apparatus. The imaging device according to claim 15 , wherein the second transistor is in a conductive state when light of a predetermined level or more enters the photoelectric conversion unit. The semiconductor substrate is provided in the first conductivity type region that is adjacent to the third impurity region on the surface of the semiconductor substrate and located between the first impurity region and the third impurity region. And further including a ninth impurity region of the first conductivity type,
The imaging device according to claim 5 , wherein an impurity concentration of the ninth impurity region is smaller than an impurity concentration of the third impurity region. Comprising a plurality of unit pixel cells arranged in one or two dimensions,
Each of the plurality of unit pixel cells is
A first conductivity type semiconductor substrate;
A photoelectric conversion unit that is located above the semiconductor substrate of the first conductivity type and converts incident light into signal charges;
A reset transistor provided on the semiconductor substrate;
A first region of the first conductivity type located on a surface of the semiconductor substrate;
A second region located on a surface of the semiconductor substrate, adjacent to the first region, and including a first conductivity type impurity having a higher concentration than the first region;
A first impurity region of a second conductivity type that is electrically connected to the photoelectric conversion portion and is located on the surface of the semiconductor substrate and in the first region ;
Located in the first area, and, with the connected first impurity region electrically, the second impurity region of the second conductivity type for accumulating the signal charges,
With
The second impurity region has an impurity concentration lower than that of the first impurity region;
Wherein when viewed in a direction perpendicular to the semiconductor substrate the surface of at least part of said second impurity region, Ri gate electrode and Do weight of the reset transistor,
The imaging device , wherein when viewed from the direction, at least a part of the second region overlaps with a gate electrode of the reset transistor .

Images