JP3584196B2 - Light receiving element and photoelectric conversion device having the same - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a light receiving element structure of an image sensor used in an image reading system such as a digital camera, an image scanner, a facsimile, and a copying machine, and a photoelectric conversion device using the same. The present invention relates to a light receiving element structure suitable for a photoelectric conversion device having a relatively large light receiving element having a pixel opening of several tens of microns or more.
[0002]
[Prior art]
In recent years, non-CCD image sensors such as CCD image sensors and CMOS image sensors have been actively developed as photoelectric conversion devices.
[0003]
In general, a photodiode formed of a semiconductor pn junction is used as a light receiving element of these photoelectric conversion devices.
[0004]
Conventional technology (1)
For example, Japanese Patent Application Laid-Open No. 55-154784 discloses that a region having the same conductivity type as the substrate and having a higher impurity concentration than the substrate is provided on the surface of the substrate where the pn junction is not formed, and the dark current generated on the substrate surface is reduced. Reduced structures have been proposed.
[0005]
29 (A) and 29 (B) show a conventional light receiving element structure according to the same publication, 201 is an n-type semiconductor substrate, 202 is a p-type semiconductor layer, and 203 is an impurity concentration of 5 × 10^Fifteencm^-3-10 × 10^Fifteencm^-3An n-type semiconductor layer having a thickness of 0.2 μm to 0.3 μm; 205, a thermal oxide film;⁺A channel stopper, 209 is a non-reflective coating film (anti-reflection coating film) made of a nitride film, 215 and 216 are aluminum electrodes, and 228 is n⁺The type semiconductor layer 238 is a back electrode. DL indicates a depletion layer, and DLS indicates a surface-side portion of the depletion layer.
[0006]
In this conventional example, since the anode of the photodiode is formed only of the p-type semiconductor layer 202, the ohmic contact with the electrode 215 is deteriorated when the concentration is reduced, and when the concentration is increased, the depletion layer DL is reduced. It does not extend into 202.
[0007]
Conventional technology (2)
Further, as a light receiving element for a one-dimensional photoelectric conversion device, one having reduced junction capacitance formed by a pn junction has been proposed as disclosed in JP-A-61-264758.
[0008]
FIG. 30 shows the upper surface of a conventional photoelectric conversion device such as a CCD image sensor according to the same publication, where 301 is a p-type substrate, and 302 is an n-type substrate.⁺Of the p-type substrate 301⁺A portion surrounded by the type accumulation unit 302 is a p-type photoelectric conversion region as a pixel. PG is a photo gate, SG is a shift gate, and SR is a CCD shift register.
[0009]
In this structure, the p-type substrate 301 and n⁺An electric signal corresponding to an image signal is generated as a p-type photoelectric conversion element by the type accumulation unit 302, shifted through a photogate PG and a shift gate SG, and sequentially transferred from the CCD shift register SR as a horizontal output line. Read out. With this structure, although the area of the pn junction is reduced, the perimeter of the pn junction is increased, so that the capacitance value of the pn junction cannot be sufficiently reduced, and it is difficult to achieve high sensitivity.
[0010]
Conventional technology (3)
Further, as a photosensitive portion structure used for a contact type image sensor, for example, as disclosed in Japanese Patent Application Laid-Open No. 1-303752, there is a photosensitive portion structure in which dark current caused by scribing of a chip end in a photosensitive portion structure is reduced. Proposed.
[0011]
FIG. 31 shows a cross section of a conventional light receiving element according to the same publication, wherein 301 is a p-type semiconductor region, 302 is an n-type semiconductor region, 303 is a p-type shallow channel stop layer, 305 is a field oxide film, and 306 is p-type. A mold substrate, 308 is a p-type channel stop layer, 309 is an interlayer insulating film, and 317 is a light shielding film for defining an opening OP. The depletion layer DL extends into the p-type semiconductor region 301, and electrons of the generated photocarriers PC are collected in the n-type semiconductor region 302 by an internal electric field.
[0012]
Conventional technology (4)
As a light receiving element in a CCD image sensor, for example, a photodiode having a cross-sectional structure of n-type substrate / p-type region / n-type region / p-type region, as disclosed in Japanese Patent Application Laid-Open No. 64-14958, is used. Commonly used.
[0013]
FIG. 32 shows a cross section of a conventional light receiving element according to the same publication, 406 denotes an n-type substrate, 401 denotes a p-type semiconductor region, 402 denotes an n-type semiconductor region, 403 denotes a shallow p-type semiconductor layer, and 408 denotes a p-type semiconductor layer.⁺409 denotes an insulating film, 415 denotes an electrode made of polysilicon, and 420 denotes an n-type region of the CCD register.
[0014]
Conventional technology (5)
On the other hand, as a photoelectric conversion device using a light receiving element, for example, in Japanese Patent Application Laid-Open No. 9-205588, a photodiode is used as a light receiving element, an electrode is attached to this light receiving element, the charge is connected to the gate electrode of a MOS transistor, and charges are transferred to a source hole. A photoelectric conversion device that performs batch reading using an amplifier has been proposed.
[0015]
[Problems to be solved by the invention]
However, when the photo-generated carriers are accumulated in a pn photodiode and applied to an amplification-type photoelectric conversion device that reads out a signal voltage from the pn photodiode by using a charge-to-voltage converter, the sensitivity may be reduced.
[0016]
In the case of an amplification type photoelectric conversion device, the light output Vp is expressed by the formula (1).
[0017]
Vp = Qp / Cs (1)
Here, Qp is the amount of charge stored in the pn photodiode, and Cs is the capacitance of the photodiode.
[0018]
For example, in the case of an amplification type photoelectric conversion device having a pixel in which a MOS source follower or a reset MOS transistor is connected to the photodiode, the capacitance Cs of the photodiode is
Cs = Cpd + Ca (2)
Can be represented.
[0019]
Here, Cpd is the pn junction capacitance of the pn photodiode itself including the light receiving unit, and Ca is another capacitance connected to the photodiode. In the above case, the gate capacitance of the MOS transistor constituting the MOS source follower and the reset MOS transistor. It includes the junction capacitance between the source and the well, the overlap capacitance between the source and the gate, the wiring capacitance, and the like.
[0020]
Therefore, in order to realize high sensitivity, it is necessary to effectively accumulate photogenerated carriers and to minimize the capacity of the photodiode in which the carriers are accumulated.
[0021]
On the other hand, when light is incident on the photodiode, charge is generated in the photodiode, and the charge generated in the depletion layer formed by the pn junction surface in the semiconductor substrate and its surroundings is collected on the anode or the cathode, and the electrode is formed there. When attached, it can be extracted as an electrical signal.
[0022]
FIG. 33 is a sectional view of a light receiving element having a conventional electrode. 701 is a first semiconductor region, and 702 is a second semiconductor region to be an anode. The respective conductivity types are n-type and p-type. DL is a depletion layer formed by a pn junction between the first semiconductor region 701 and the second semiconductor region 702. Although not shown, a reverse bias is applied between the first semiconductor region 701 and the second semiconductor region 702. Further, reference numeral 715 denotes an electrode, and the electrode 715 is connected to the second semiconductor region 702 via a contact hole CH of the insulating film 709.
[0023]
The electrode 715 is made of, for example, a metal mainly composed of Al or the like, and is connected to an electrode region formed on the main surface of the semiconductor substrate via a contact hole CH of an insulating film covering the surface of the photodiode. Generally, such a light receiving element has a configuration in which a conductive material such as Al is connected to a semiconductor region in order to obtain an optical signal by a photocarrier photoelectrically converted in the semiconductor region.
[0024]
For example, when this electrode is formed by using a general RIE (reactive ion etching) method, usually, over-etching is performed so as not to leave an unnecessary portion. At the time of this over-etching, some of the ions accelerated by the electric field penetrate the insulating film 709 and reach the main surface of the semiconductor substrate, thereby damaging the vicinity of the interface between the semiconductor and the insulating film, thereby generating crystal defects. There are cases.
[0025]
Also, in the process after the formation of the electrodes, crystal defects may occur similarly to the above due to plasma ashing of the photoresist.
[0026]
In a general light receiving element, a pn junction surface exists around the semiconductor region on the main surface of the semiconductor substrate to which the electrodes are connected, and the junction surface reaches near the interface between the main surface of the semiconductor substrate and the insulating film. There are many.
[0027]
Therefore, when the electrode is formed inside the bonding surface reaching the main surface of the semiconductor substrate, a crystal defect due to etching damage occurs near the bonding surface, and this crystal defect becomes a carrier generation center. The crystal defects generated in the depletion layer cause dark current.
[0028]
In addition, the dark current generated by this causes a change in the amount of crystal defects generated near the bonding surface or a change in the amount of crystal defects themselves due to misalignment of the mask when forming a current or the like and etching conditions. This also causes a variation in dark current.
[0029]
[Object of the invention]
A first object of the present invention is to provide a light receiving element capable of minimizing a pn junction capacitance of a photodiode portion and effectively utilizing photogenerated carriers, and a photoelectric conversion device having the same.
[0030]
A second object of the present invention is to provide a light receiving element in which occurrence of defects in a semiconductor region where a depletion layer is formed is suppressed.
[0031]
[Means for Solving the Problems]
The light receiving element of the present invention includes first semiconductor regions 1, 11, 21, 31, 81 of the first conductivity type and second semiconductor regions 2, 12 of the second conductivity type disposed on the first semiconductor regions. , 32, 81, a first conductive type third semiconductor region 3, 13, 33, 83 disposed on the surface of the second semiconductor region, and a conductive member disposed on the surface of the second semiconductor region. In a light receiving element having second conductive type electrode regions 4, 14, 34, 84 connected to an anode or a cathode electrode, the third semiconductor region is formed so as to surround the periphery of the electrode region. Cage,A second conductivity type internal region having a higher impurity concentration than the second semiconductor region and a lower impurity concentration than the electrode region is formed between the electrode region and the second semiconductor region.The electrode region is disposed on a surface of the internal regionI have. It is better if each part is designed as follows.
[0032]
The electrode region is set in a floating state (floating state) to accumulate photo-generated charges, and a bias is applied to the first semiconductor region to apply a reverse bias between the first semiconductor region and the second semiconductor region. Apply voltage.
[0033]
A potential gradient is formed between the electrode region and the second semiconductor region that can move the photo-generated charges toward the electrode region.
[0034]
Further, the internal region is made up of a plurality of regions having different impurity concentrations from each other. The internal region is formed so as to surround the periphery of the electrode region. The internal region is formed at a position shallower than the second semiconductor region.
[0036]
Further, the first semiconductor region is formed from one of a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, and a well formed in the semiconductor substrate.
[0037]
Further, the light receiving element of the present invention includes a first conductive type first semiconductor region 51, 61, 71, 81, and a second conductive type second semiconductor region 52, which is disposed on the first semiconductor region. 62, 72, and 82, a second conductivity type electrode region disposed on the surface of the second semiconductor region and connected to an anode or cathode electrode 15 made of a conductor, and the first and second semiconductor regions. A first conductivity type disposed between the surface of the semiconductor substrate including the first substrate and the insulating film 9 adjacent to the surface of the semiconductor substrate, and formed to surround the electrode region and the second semiconductor region. The third semiconductor region 53, 63, 73, 83, wherein the depletion layer DL formed between the electrode region and the third semiconductor region is in contact with the insulating film. All parts 59, 69, 89And the entire second semiconductor region.It is characterized by the following.
[0038]
Each part may be designed as follows.
[0039]
The first semiconductor region is formed of an epitaxial layer, the second semiconductor region is formed inside the upper surface side, and the area of the upper surface of the anode or cathode electrode is made larger than the area of the upper surface of the second semiconductor region.
[0040]
The second semiconductor region is formed of portions having different impurity concentrations from each other, and the area of the upper surface of the anode or the cathode electrode is made larger than the area of the upper surface of the second semiconductor region.
[0041]
The second semiconductor region is formed of a high-concentration region having a high impurity concentration and a low-concentration region having a low impurity concentration, and the third semiconductor region is formed on an upper surface of the low-concentration region.
[0042]
The extending portion of the anode or the cathode electrode covers at least an area above the third semiconductor region.
[0043]
When these light receiving elements are combined with a light source such as an LED for irradiating an object such as a document and an imaging element, a photoelectric conversion device is obtained.
[0044]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described in detail with reference to the drawings.
[0045]
(Embodiment 1)
Hereinafter, a first embodiment as a basic embodiment of the present invention will be described with reference to FIGS. 1 (A) to 1 (D), 2 and 3. FIG.
[0046]
FIGS. 1A to 1D are drawings showing the features of the present embodiment best, FIG. 1A is a top view of a light receiving element portion of the present embodiment, and FIG. 1A is a cross-sectional view taken along a line AA ′, FIG. 1C is a potential profile in the direction along the line XX ′ in FIG. 1B, and FIG. FIG. 5 is a potential profile diagram in a direction along a line YY ′.
[0047]
Reference numerals 1, 2, and 3 denote first semiconductor regions of the first conductivity type provided in the semiconductor substrate, second semiconductor regions of the second conductivity type provided in the first semiconductor region 1, respectively. This is a third semiconductor region of the first conductivity type provided on the main surface side of the second semiconductor region 2.
[0048]
Reference numeral 4 denotes an electrode region adjacent to the second semiconductor region 2 for extracting charges generated by light, and specifically, has the same conductivity type as that of the second semiconductor region 2 and an impurity concentration lower than that. It is composed of a high high concentration impurity region or the like.
[0049]
Reference numeral 102 denotes a light receiving region including the first, second, and third semiconductor regions 1, 2, 3, and 3. In the light receiving region 102, carriers generated by light incidence are captured in the region 101. Of course, if light enters the region 101, carriers are generated also in the region 101.
[0050]
In FIG. 1, the first conductivity type is shown as p-type and the second conductivity type is shown as n-type.
[0051]
If necessary, an insulating film is formed on the surface of the semiconductor substrate, an opening is formed in the insulating film, and a conductor serving as an electrode is formed in the opening.
[0052]
For example, in the light receiving region 102, carriers (in this case, electrons) generated by the photons hν move in the horizontal direction as shown in FIG. 1C, and the electrons pass through this potential groove, that is, the lowest potential region. 4 is collected in the area 101.
[0053]
In the absence of such a potential structure, the generated electrons stray in the substrate due to diffusion, and if they cannot reach the region 4 within the lifetime, they recombine with holes and disappear.
[0054]
As shown in FIG. 1D, a further feature of the present embodiment is that the third semiconductor region 3, the first semiconductor region 1, and the second semiconductor region 3 on the surface are so depleted that the second semiconductor region 2 is almost completely depleted. The point is that the impurity concentration and the junction depth of the region 2 and the potential applied to the electrode region 4 and the region 1 are set. As a result, the second semiconductor region 2 hardly contributes as a capacity, and the capacity of the light receiving section can be reduced.
[0055]
That is, electrons generated near the junction interface between the regions 2 and 3 are collected in the region 2 by the built-in potential due to the pn junction. On the other hand, electrons generated near the junction interface between the regions 2 and 3 are collected in the region 2 by a built-in potential due to the pn junction. Here, since the region 2 of the light receiving region 102 is almost depleted by the two pn junctions, there is no neutral region. Such a state will be referred to as complete depletion. Then, the collected electrons are collected in the region 4 as described above and output from an electrode (not shown).
[0056]
FIG. 2 shows the distribution of the impurity concentration in the direction along the line YY '. In FIG. 2, Np1 indicates a p-type impurity concentration such as boron (B) in a p-type semiconductor substrate serving as a starting material of the region 1, and Nn1 indicates a phosphorus or arsenic introduced for forming the region 2. Np2 indicates a p-type impurity concentration introduced for forming the region 3.
[0057]
Nc indicates the net impurity concentration (net value) of each region.
[0058]
The impurity concentration and thickness in each region can be selected from the following ranges. As a parameter of the thickness, a junction depth from the substrate surface is shown. The first semiconductor region 1 has an impurity concentration ND1 of 10¹⁴cm^-3-10¹⁷cm^-3, More preferably 10^Fifteencm^-3-10¹⁶cm^-3And the junction depth is 0.1 μm to 1000 μm.
[0059]
The impurity concentration ND2 of the second semiconductor region 2 is 10^Fifteencm^-3-10¹⁸cm^-3, More preferably 10¹⁶cm^-3-10¹⁷cm^-3And the junction depth is 0.2 μm to 2 μm.
[0060]
The impurity concentration ND3 of the semiconductor region 3 is 10¹⁶cm^-3-10¹⁹cm^-3, More preferably 10¹⁷cm^-3-10¹⁸cm^-3And the junction depth is 0.1 μm to 0.5 μm.
[0061]
The impurity concentration ND4 of the electrode region 4 is 10¹⁸cm^-3-10²¹cm^-3, More preferably 10¹⁹cm^-3-10²⁰cm^-3And the junction depth is 0.1 μm to 0.3 μm.
[0062]
The impurity concentration ND2 of the second semiconductor region 2 is higher than the impurity concentration ND1 of the first semiconductor region 1, and the impurity concentration ND3 of the third semiconductor region 3 is higher than the impurity concentration ND2 of the second semiconductor region 2. It is good to decide.
[0063]
For more detailed description, FIG. 3 is a graph showing the relationship between the voltage of the electrode region 4 and the capacitance at that time. Although the capacity decreases as the voltage increases, the capacity of the region 4 becomes constant at the point A.
[0064]
When the voltage is low, region 2 is not depleted, and the capacitance changes depending on the depletion layer capacitance between region 2 and region 3 and the depletion layer capacitance between region 2 and region 1. . That is, as the voltage of the region 4 increases, the depletion layer expands, and thus the capacitance gradually decreases. However, when the upper and lower depletion layers are connected, the region 2 in the light receiving region 102 is almost completely depleted, and the capacitance is reduced. It decreases sharply and then stabilizes. The transition point is point A in the figure, and the voltage at point A is hereinafter referred to as a depletion voltage.
[0065]
Since the depletion voltage is determined depending on the thickness of each of the regions 1, 2, 3 and the impurity concentration,
(A) the potential of the electrode region 4 when the light receiving element is reset,
(B) The voltage of the electrode region 4 when the light output of the light receiving element is saturated
Is set to be equal to or higher than the depletion voltage, the capacitance of the photodiode itself can be substantially reduced to about the junction capacitance C0 at the bottom of the reference numeral 101, and high sensitivity can be realized.
[0066]
Here, the electric potential of the electrode changes due to the accumulation of the charge generated by the light in the electrode region. However, the operating point (the range in which the potential changes) is designed to be equal to or higher than the depletion voltage, so that the electrode region Since the capacitance of No. 4 has linearity, it is possible to obtain a photoelectric conversion characteristic with high sensitivity and good linearity.
[0067]
Further, when the voltage decreases at the boundary of the depletion voltage, the capacitance value increases exponentially from C0 to a capacitance value determined by the area of the region 2.
[0068]
For example, the thickness of the region 1 is about 600 μm and the impurity concentration is 1 × 10¹⁶cm^-3Region 2 has a junction depth of 0.5 μm and an impurity concentration of 1 × 10¹⁷cm^-3Region 3 has a junction depth of 0.2 μm and an impurity concentration of 1 × 10¹⁸cm^-3Region 4 has a junction depth of 0.2 μm and an impurity concentration of 1 × 10¹⁹cm^-3The capacitance ratio of the photodiode when the region 4 is not depleted as compared with the photodiode capacitance when the light receiving element has the upper surface area of the region 2 of 80 μm × 80 μm and the upper surface area of the region 4 of 1.2 μm × 1.2 μm. Is about 4400 times.
[0069]
If there is no potential profile as shown in FIG. 1 (C), electrons generated in the vicinity of the electrode region 4 can easily reach there, but electrons generated at the end of the light receiving surface are located in the electrode region about 40 μm apart. The probability of reaching is very low, resulting in a significant loss of sensitivity.
[0070]
On the other hand, in the structure of the present embodiment, electrons generated at least within about 1 μm from the surface can be collected almost anywhere in the light receiving surface. In particular, since most of the blue light is absorbed within 1 μm of the silicon surface, the sensitivity of blue, which is a problem in the visible light sensor, is improved.
[0071]
In addition, by using a technique such as high-energy ion implantation, a retrograde well structure having a peak value of the impurity concentration inside the substrate is used, or conversely, the concentration of the substrate 1 is reduced and the depletion layer is expanded. It is also possible to collect electrons generated at a deep place.
[0072]
Furthermore, by forming a high-concentration impurity layer on the substrate surface, providing a low-impurity-concentration epitaxial layer thereon, and applying the present invention, it is possible to obtain a light-receiving portion structure with high long-wavelength sensitivity.
[0073]
FIG. 4 shows an example of a read and reset circuit used in the present invention. In FIG. 4, D1 is a photodiode formed of a light receiving element according to the present invention, M1 is a reset switch formed of a MOS transistor or the like, M2 is an amplification element formed of a MOS transistor or the like, and M3 is a load formed of a MOS transistor or the like. It can also be used. VR is a reset line or a reset terminal for applying a reset reference voltage, VDD is a power supply voltage line or a power supply terminal for applying a power supply voltage, φ_RIs a reset control line for turning on / off the reset switch M1, and V_OUTIs an output terminal.
[0074]
The operation of the read and reset circuit of FIG. 4 will be described. Reset control line φ_RThen, the reset switch M1 is turned on, a reset reference voltage higher than the depletion voltage is applied to the cathode (region 4 in FIG. 1A), and the floating gate of the amplifier M2 is reset. Then, the accumulation of the optical carriers starts, and the potential of the input terminal of the amplification element M2 changes. After a predetermined accumulation time has elapsed, the selection line φ_SWhen a selection switch M3 is turned on by inputting an on-pulse, a current corresponding to an optical carrier flows through a source follower circuit having transistors M2 and M3, and an output signal is obtained.
[0075]
(Embodiment 2)
FIG. 5A is a top view of the light receiving element according to the present embodiment, and FIG. 5B is a cross-sectional view taken along line BB ′ of FIG. 5A.
[0076]
In FIG. 5, reference numeral 11 denotes a first semiconductor region of a first conductivity type (here, n type), 12 denotes a second semiconductor region of a second conductivity type (here, p type), and 13 denotes a third semiconductor region of the first conductivity type. The semiconductor region 14 is an electrode region of the second conductivity type having a high impurity concentration.
[0077]
In the present embodiment, an element isolation region (isolation region) 5 formed by a selective oxidation method called LOCOS or the like for isolating the light receiving element is formed.
[0078]
Next, the method for manufacturing the light receiving element according to the present embodiment will be explained. A silicon oxide SiO2 is formed by a selective oxidation method in which a silicon nitride film SiN (not shown) is formed as an oxidation resistant mask, and a thick oxide film is formed in a portion exposed therefrom.₂Is formed (FIG. 6A). Such a method is known as LOCOS.
[0079]
Next, a photoresist mask (not shown) is formed, ion implantation is performed, and heat treatment is performed to form a p-type second semiconductor region 12 in the first semiconductor region 11 made of an n-type semiconductor substrate. The depletion layer formed by the pn junction is prevented from reaching the edge 104 by separating the edge 103 of the second semiconductor region 12 from the edge 104 of the element isolation region 5 where many defects exist. Thus, generation of dark current due to defects can be suppressed (FIG. 6B).
[0080]
Next, an n-type third semiconductor region 13 is formed on the surface of the substrate by forming a photoresist mask (not shown) and performing ion implantation, removing the photoresist mask, and performing heat treatment (FIG. 6C )).
[0081]
Then, a photoresist mask (not shown) is formed, ions are implanted, and a heat treatment is performed after the removal of the photoresist mask to form the p-type electrode region 14, whereby the structure shown in FIG. 5B is obtained.
[0082]
After that, if necessary, an insulating film covering the surface is formed, a contact hole is opened, and the electrode region 14 may be connected to a read and reset circuit formed in another place of the same semiconductor substrate through a wiring.
[0083]
In this embodiment, since a signal is output from the anode of the photodiode, the configuration of the read and reset circuit used in this embodiment is also the same in terms of the potential level and the conductivity type.
[0084]
FIG. 7 is a circuit diagram of another read and reset circuit used in the present invention. In FIG. 7, D1 is a photodiode comprising a light receiving element of the present invention, M2 and M3 are an amplifying element and a selecting element, respectively, and a source which is an amplifier for converting a photoelectric charge generated in the photodiode D1 into a charge voltage and reading it out. Constitutes a follower. The selection of the pixel was performed by turning on / off the switch M3 which is also a low current source of the source follower. After reading out the photoelectric charge information of the pixel with the selection switch M3, the photodiode D1 was reset by the reset switch M1. Reset voltage (φ_R−Vth), the reset voltage was set such that a reverse voltage higher than the depletion voltage was applied to the anode of the photodiode. Here, Vth is a threshold value of the reset switch M1. The outputs of the amplification element M2 and the selection element M3 having the source follower configuration are output via the buffer B1, the coupling capacitor C for cutting off the DC component, and the buffer B2 by shifting the ON time of the selection element. .
[0085]
For example, since the depletion voltage was 1.0 volt in the reverse bias voltage of the photodiode D1, the reset voltage was set to be applied 3 volts in the reverse bias voltage. That is, when the power supply voltage applied to the terminal VDD was used at 5 volts, the voltage applied to the reset terminal VR was set to 2.0 volts, and the read operation was performed.
[0086]
In the present embodiment, when the size of the light receiving surface is 40 μm × 40 μm and the size of the upper surface of the electrode region 14 is 6 μm × 6 μm, the capacitance of the photodiode is 3.8 fF, which is considerably lower than the conventional one, and high photoelectric conversion. Sensitivity could be obtained.
[0087]
In the present embodiment, image information in the region in front of the light receiving surface can be obtained, and a high-definition image can be obtained.
[0088]
In particular, the present embodiment is effective in the case of a light receiving element having a large light receiving surface such that light collection efficiency is deteriorated. When the size of the light receiving surface is 20 μm square or more, the collection efficiency starts to deteriorate, and this is particularly effective for a light receiving element having a light receiving surface larger than this size.
[0089]
(Embodiment 3)
FIG. 8A shows an upper surface of a light receiving element according to Embodiment 3 of the present invention, and FIG. 8B shows a cross section taken along line CC ′ of FIG. 8A.
[0090]
The difference from the embodiment shown in FIGS. 5A and 5B is that the second semiconductor region is composed of two regions having different impurity concentrations from each other. In FIG. 8, the internal region 22 in contact with the electrode region 14 has a higher impurity concentration than the external region 12 and has a lower impurity concentration than the electrode region 14. The junction depth of the inner region 22 may be shallower or deeper than the outer region 12.
[0091]
FIG. 9 shows a potential profile in a direction along the line CC ′ of FIG. 8A. A potential gradient steeper than that in FIG. 1C is formed by the inner region 22 and the outer region 12 having different impurity concentrations. In this way, the charges generated at the end of the light receiving surface can be easily collected on the electrode region 14, and the optical signal reading time can be shortened.
[0092]
Next, the method for manufacturing the light receiving element according to the present embodiment will be explained with reference to FIG. An element isolation region 5 made of silicon oxide is formed on the n-type semiconductor substrate 11 by a selective oxidation method in which a silicon nitride film (not shown) is formed as an oxidation-resistant mask and a thick oxide film is formed in a portion exposed from the mask (FIG. FIG. 10 (A)).
[0093]
A p-type second semiconductor region 12 is formed in the first semiconductor region 11 formed of an n-type semiconductor substrate by forming a photoresist mask (not shown), performing ion implantation, and performing heat treatment. The depletion layer formed by the pn junction is prevented from reaching the edge 104 by separating the edge 103 of the second semiconductor region 12 from the edge 104 of the element isolation region 5 where many defects exist.
[0094]
Thus, generation of dark current due to defects can be suppressed. Then, a photoresist mask (not shown) is formed, and an internal region 22 having a high impurity concentration is formed by ion implantation and heat treatment (FIG. 10B).
[0095]
Next, by ion implantation and heat treatment, n⁺A third semiconductor region 13 of a mold is formed (FIG. 10C).
[0096]
Then, by ion implantation and heat treatment, p⁺When the mold electrode region 14 is formed, the structure shown in FIG. 8B is obtained.
[0097]
Thereafter, if necessary, a transparent insulating film covering the surface is formed, an opening is formed in the insulating film, and a read and reset circuit formed in another place of the same semiconductor substrate is connected to the electrode region 14 through wiring. Should be connected.
[0098]
As described above, the same circuit as that shown in FIG. 7 can be employed as the readout circuit and the reset circuit according to the present embodiment.
[0099]
(Embodiment 4)
FIG. 11A shows the top surface of the light receiving element according to the present embodiment, and FIG. 11B shows a cross section taken along line DD ′ of FIG. 11A.
[0100]
The difference from the embodiments shown in FIGS. 5A and 5B is that an n-type epitaxial layer 21 formed on the surface of a p-type semiconductor substrate 6 by epitaxial growth is used as a first semiconductor region. After the formation of the n-type epitaxial layer 21, the p-type second semiconductor region 12 is formed by ion implantation or the like, and further, the n-type⁺Type third semiconductor region 13 is formed, and ion implantation and heat treatment are performed.⁺A mold electrode region 14 is formed.
[0101]
In the present embodiment, instead of forming the n-type epitaxial layer 21, an n-type well formed by ion implantation and heat treatment in a p-type semiconductor substrate can be used.
[0102]
According to the present embodiment, it is possible to prevent charges generated at a deep position of the p-type substrate from reaching the p-type second semiconductor region 12.
[0103]
Specifically, if the thickness of the well is, for example, about 4 μm, most of the holes generated at a depth of about 4 μm away from the surface of the light receiving element flow into the p-type substrate, so that the dark current is not generated. Can be suppressed.
[0104]
In the case of the structure shown in FIGS. 5A and 5B, noise generated when driving the reset circuit or the readout circuit easily enters the second semiconductor region. On the other hand, by forming the second semiconductor region in a well formed individually or commonly for all pixels as in the present embodiment, the entry of the noise can be suppressed.
[0105]
(Embodiment 5)
12 shows a top view of the light receiving element according to the fifth embodiment, FIG. 13 shows a cross section taken along line EE 'in FIG. 12, and FIG. 14 shows a cross section taken along line FF' in FIG. Is shown.
[0106]
In FIG. 12, a p-type second semiconductor region 32 constituting a photodiode serving as a light receiving element is formed in an opening OP, and a p-type internal region 22 is formed in this region 32. Also, in the internal region 22, p⁺The electrode region 34 is formed of a first metal layer at the drain of the MOS transistor M1 serving as a reset switch and at the gate of the source follower MOS transistor M2 serving as an amplifying element. They are electrically connected by the wiring 15. The opening OP of the light receiving element is defined by a light shielding layer 17 formed of a second metal layer, and the light shielding layer 17 is connected to a power supply and fixed at a predetermined reference potential.
[0107]
Where p⁺The electrode region 34 of the type is arranged closer to the direction in which the drain portion of the reset MOS transistor M1 and the source follower MOS transistor M2 are arranged than the center of the opening, and on the side opposite to the electrode region 34. Is provided with a power supply line 16 for determining the potential of an n-type well region 31 as a first semiconductor region. In the figure, the size of the opening OP is 40 μm × 60 μm.
[0108]
13 and 14, the second semiconductor region 32 is formed in the opening OP of the n-type well region 31 provided in the p-type semiconductor substrate 6, and the internal region 22 is further formed in the second semiconductor region 32. It can be seen that the electrode region 34 is formed in the inner region 22 in an island shape.
[0109]
On the main surfaces of the second semiconductor region 32 and the internal region 22, an n-type surface region 33 is provided as a third semiconductor region, and is electrically connected to the n-type well region 31 at an end of the opening OP. .
[0110]
Therefore, a photodiode is formed by the pn junction between the second semiconductor region 32 and the internal region 22 made of the p-type semiconductor and the first and third semiconductor regions 31 and 33 made of the n-type semiconductor, and the photodiode is photoelectrically converted by the photodiode. The optical carrier is p⁺The potential of the wiring 15 collected in the electrode region 34 made of the mold semiconductor and formed of the first metal layer is changed.
[0111]
Further, a protective film 18 is provided on the electrode region 34 and on the light shielding layer 17 formed of the second metal layer.
[0112]
Here, as shown in FIG.⁺The mold region 34 is arranged on the side where the reset MOS transistor M1 and the source follower MOS transistor M2 are arranged, that is, on the right side in FIG. 14 with respect to the center of the opening OP. The contact of the power supply line 16 for supplying⁺It is arranged only on the opposite side of the mold region (1511).
[0113]
Here, the n-type well region 31 is formed in the p-type substrate 6 and is surrounded by a p-type well region 7 serving as an element isolation region for each pixel, and is electrically connected to each pixel by a pn junction. The structure is separated into
[0114]
In FIG. 13 and FIG. 14, representative values of the approximate surface concentration and the junction depth of each region are shown below.
[0115]
p-type substrate 6: about 1 × 10^Fifteen(Cm^-3)
First semiconductor region 31: about 1 × 10¹⁷(Cm^-3) / About 4.0 μm
Second semiconductor region 32: about 2 × 10¹⁷(Cm^-3) / About 0.35 μm
Internal area 22: about 3 × 10¹⁷(Cm^-3) / About 0.30 μm
Third semiconductor region 33: about 3 × 10¹⁸(Cm^-3) / About 0.20 μm
Electrode area 34: about 3 × 10¹⁹(Cm^-3)
In this embodiment, the depletion voltage of each of the region 32 and the region 22 is:
Area 32: about -1.0 V
Region 22: about -1.5V
It has become.
[0116]
Therefore, since the depletion voltage of the regions 32 and 22 increases toward the electrode region 34, a potential gradient of the photocarrier is formed, and the photocarrier can be more efficiently collected at the electrode region 34. It becomes.
[0117]
In the present embodiment, since the photomask (reticle) for exposure is formed such that the corners of the region 32 and the region 22 are all obtuse, potential grooves are formed due to non-uniform electric fields at the corners. And the afterimage characteristics are improved. Furthermore, since the region 31 is formed in the p-type substrate 6 and has a structure in which the periphery is surrounded by the p-type well region 7 for each pixel, crosstalk generated by mixing of optical carriers into adjacent pixels is generated. Can be almost completely suppressed, and a high-quality resolution pattern can be obtained.
[0118]
Further, even if the photo carriers that are saturated or more are accumulated in a certain pixel, the overflowing photo carriers are absorbed by the surrounding p-type well region 7 and the substrate 6, so that the bleeding is not affected on other pixels. A few high-quality images can be obtained.
[0119]
In the present embodiment, the region 32 and the region 22 are illustrated as regions where the photodiode is formed. For example, the second p-type internal region including the electrode region 34 inside the internal region 22 is illustrated. Are formed, and the depletion voltage in the second internal region is set to an impurity concentration and a junction depth that are higher than the depletion voltage in the internal region 22, thereby forming a light receiving element having further lower image lag characteristics. It is also possible.
[0120]
(Embodiment 6)
15 shows a top view of a light receiving element according to the sixth embodiment, FIG. 16 shows a cross section taken along line GG ′ in FIG. 15, and FIG. 17 shows a cross section taken along line HH ′ in FIG. Is shown.
[0121]
The present embodiment differs from the embodiments shown in FIGS. 12 to 14 in that the planar shape of the internal region 22 made of a p-type semiconductor is changed so as to have a portion whose width gradually changes.
[0122]
In addition, a portion 22A whose width narrows downward in the drawing extends downward from above in the drawing beyond the center of the light receiving surface (opening).
[0123]
Reference numeral 8 shown in FIG. 17 is a contact region having a high impurity concentration, and serves as a cathode contact of the power supply line 16.
[0124]
15 to 17, a second semiconductor region of a photodiode serving as a light receiving element is formed in an opening OP, and an internal region 22 is formed in this region 32. Further, an electrode region 34 is formed in the internal region 22. This region 34 is formed of a wiring formed of a first metal layer at the drain of the reset MOS transistor M1 and the gate of the source follower MOS transistor M3. 15 are electrically connected. The opening OP of the light receiving element is defined by a light shielding layer 17 formed of a second metal layer, and the light shielding layer 17 is connected to a power supply and fixed at a desired potential.
[0125]
Here, the electrode region 34 is arranged so as to be closer to the direction in which the drain portion of the reset MOS transistor M1 and the source follower MOS transistor M2 are arranged than the center of the opening, and the opening opposite to the electrode region 34. A power supply line 16 for supplying reverse bias electric power to the n-type well region 31 as the first semiconductor region is provided on the unit side. In the figure, the size of the opening OP is 40 μm × 60 μm.
[0126]
An n-type surface region 33 as a third semiconductor region is provided on the main surfaces of the region 32 and the region 22, and is electrically connected to the n-type well region 31.
[0127]
Therefore, a photodiode is formed by a pn junction between the p-type region 32 and the region 22 and the n-type region 31 and the region 33. Photocarriers photoelectrically converted by the photodiode are collected in the region 34 and the potential of the wiring 15 is reduced. Change it.
[0128]
Further, a protective film 17 is provided on the light-shielding layer 17 formed of the second metal layer.
[0129]
Here, the electrode region 34 is arranged on the side where the reset MOS transistor M1 and the source follower MOS transistor M2 are arranged, that is, on the right side in FIG. 17 with respect to the center of the opening. The contact of the power supply line 16 for supplying a potential is arranged only on the side opposite to the electrode region 34 (the left side in FIG. 17).
[0130]
Here, the n-type well region 31 is formed in the p-type substrate 6 and is surrounded by the p-type well region 7 for each pixel, and has a structure electrically isolated for each pixel. I have.
[0131]
Further, the inner region 22 has a shape whose width gradually increases from W1 to W2 (W2> W1) toward the electrode region 34, and the corners of the upper surfaces of the region 32 and the region 22 are all It has a shape consisting of an obtuse angle greater than 90 degrees.
[0132]
In FIGS. 16 and 17, representative values of approximate surface concentration / junction depth in each region are shown below.
[0133]
p-type substrate 6: about 1 × 10^Fifteen(Cm^-3)
Area 31: about 1 × 10¹⁷(Cm^-3) / About 4.0 μm
Area 32: about 2 × 10¹⁷(Cm^-3) / About 0.35 μm
Area 22: about 3 × 10¹⁷(Cm^-3) / About 0.30 μm
Area 33: about 3 × 10¹⁸(Cm^-3) / About 0.20 μm
Area 34: about 3 × 10¹⁹(Cm^-3)
In this embodiment, the depletion voltage of each of the region 32 and the region 22 is:
Area 32: about -1.0 V
Region 22: about -1.5V
It has become.
[0134]
Therefore, since the depletion voltage in the regions 32 and 22 increases toward the electrode region 34, a potential gradient of the photocarrier is formed, and the photocarrier can be more efficiently collected in the region 54. .
[0135]
Further, since the power supply line 16 for supplying a voltage for fixing the potential of the n-type well region 31, which is the first semiconductor region, is provided on the opposite side of the region 34, the photocurrent generated by the photo-generated electrons becomes n-type. By flowing in the well region 31 toward the contact region 8, a potential gradient is generated from the contact region 8 toward the region 34, and the photo-generated holes are more efficiently p⁺It can be collected in the mold region 511 and the afterimage characteristics are improved.
[0136]
In addition, in the present embodiment, since the region 22 has a portion whose width increases toward the region 34, the light generation holes reaching the tip of the region 22 due to the potential gradient flow toward the region 34. In this case, since the sheet resistance of the region 22 gradually decreases with respect to the photocurrent generated by the light generation holes, the light generation holes can be collected in the region 34 at high speed, and the afterimage characteristics during high-speed operation are improved. I do.
[0137]
Further, since the tip of the region 22 is arranged beyond the center of the opening OP, the efficiency of collecting holes on the contact region 8 side is improved.
[0138]
Further, since the corners of the region 32 and the region 22 are all formed with obtuse angles, a potential groove due to non-uniform electric field at the corner portion is less likely to be formed, and the afterimage characteristics are further improved. Such a shape can be easily formed by a pattern of a photomask used when exposing the photoresist.
[0139]
Furthermore, since the region 31 is formed in the p-type substrate 6 and has a structure in which the periphery is surrounded by the p-type well region 7 for each pixel, crosstalk generated by mixing of optical carriers into adjacent pixels is generated. Can be suppressed almost completely, and a high-quality resolution pattern can be obtained.
[0140]
Further, even if a high carrier exceeding saturation is accumulated in a certain pixel, the overflowing optical carrier is absorbed by the surrounding region 7 and the substrate 6, so that it does not affect the other pixels and has a low blur and high quality. Pixel can be obtained.
[0141]
In the present embodiment, the region 32 and the region 22 are illustrated as regions for forming the photodiode. For example, a second internal region 22 that further includes the region 34 inside the internal region 22 is provided. By setting the depletion voltage in the second internal region to an impurity concentration and a junction depth higher than the depletion voltage in the internal region 22, a light receiving element having further lower image lag characteristics is formed. Is also possible.
[0142]
(Embodiment 7)
FIG. 18 is a top view of the light receiving element according to the present embodiment, and FIG. 19 is a cross-sectional view taken along line II ′ of FIG.
[0143]
The feature of the light receiving element of the seventh embodiment is that a doped region 43 having a low impurity concentration is formed in an offset region between the electrode region 34 and the semiconductor region 33.
[0144]
18 and 19, a p-type region as a second semiconductor region 32 of a photodiode serving as a light receiving element is formed in an opening OP, and a p-type region as an electrode region 34 formed in the p-type region 32 of the photodiode is formed.⁺The mold region is electrically connected to the drain of the reset MOS transistor M1 and the gate of the source follower MOS transistor M2 by a wiring 15 formed of a first metal layer. The opening OP of the light receiving element is defined by a light shielding layer 17 formed of a second metal layer, and the light shielding layer 17 is connected to a power supply and fixed at a desired potential. Here, the size of the opening OP is 40 μm × 40 μm.
[0145]
A p-type region 32 is formed in the opening OP of the n-type well region 31 provided in the p-type semiconductor substrate 6, and a p-type region 32 is formed in the p-type region 32.⁺The mold region 34 is provided in an island shape.
[0146]
Further, an n-type surface region 33 as a third semiconductor region is provided on the main surface of the p-type region 34, and is electrically connected to the n-type well region 31.
[0147]
Here, the n-type surface region 33 is directly p⁺An offset (interval) of about 2 μm is provided so as not to be in contact with the mold region 34, and a second n-type surface region 43 is formed on the entire surface of the light receiving element including the offset region.
[0148]
Therefore, a photodiode is formed by the pn junction of the p-type region 32 and the n-type regions 31, 33, and 43, and the photocarrier photoelectrically converted by the photodiode is p-type.⁺The potential of the wiring 15 collected in the mold electrode region 34 and formed of the first metal layer is changed.
[0149]
Further, an interlayer insulating film 9 is provided between the semiconductor surface and the first metal layer and between the first metal layer and the second metal layer, and a light-shielding layer formed by the second metal layer A protective film 18 is provided on the upper part of 17.
[0150]
In FIG. 19, the approximate surface concentration / junction depth of each region is shown below.
[0151]
p-type substrate 6: about 1 × 10^Fifteen(Cm^-3)
n-type well region 31: about 1 × 10¹⁷(Cm^-3) / About 4.0 μm
p-type region 32: about 2 × 10¹⁷(Cm^-3) / About 0.35 μm
First n-type surface region 33: about 3 × 10¹⁸(Cm^-3) / About 0.20 μm
Second n-type surface region 43: about 3 × 10¹⁷(Cm^-3) / About 0.1 μm
p⁺Mold area 34: about 3 × 10¹⁹(Cm^-3)
Therefore, if the second n-type surface region 43 does not exist, the impurity concentration near the surface of the offset region is 10%.¹⁷cm^-3The following p-type region is obtained. Further, since the boron concentration near the semiconductor surface is liable to fluctuate depending on the manufacturing process, carriers generated in this offset region cause dark current and dark current variation.
[0152]
On the other hand, p is set so that this offset region is not formed.⁺When the mold region 34 is brought into contact with the first n-type surface region 33, p⁺The reverse bias between the mold region 34 and the first n-type surface region 33 tends to cause breakdown.
[0153]
In contrast, the surface concentration of the second n-type surface region 43 is set to 10¹⁷-10¹⁸cm^-3By setting to about⁺Even if a reverse bias is applied between the mold region 34 and the first n-type surface region 33, problems such as breakdown do not occur.
[0154]
On the other hand, if the offset area is too small, the offset may be reduced due to misalignment in photolithography.⁺The probability that the mold region 511 contacts the first n-type surface region 520 increases, and the yield decreases.
[0155]
Therefore, the concentration near the surface of the offset region is 10¹⁷cm^-3Since the n-type region is on the order of, it is possible to suppress carrier generation in the offset region. For example, even if this second n-type surface region 43 is formed on the entire surface of the light receiving portion by ion implantation, the first n-type surface region 33 and p⁺Since the impurity concentration is sufficiently low with respect to the mold region 34, these regions are hardly affected. As described above, since there is no problem such as misalignment in photolithography, it is possible to selectively control the surface concentration of the offset region and reduce the dark current.
[0156]
According to the findings of the present inventor, as a result of measuring the dark current, the dark current is reduced to 場合 when the second n-type surface region 43 is present, as compared with the case where the second n-type surface region 43 is not present.
[0157]
Here, the depletion voltage of the semiconductor region 32 in the present embodiment was about -2V. Therefore, for example, when the n-type well region 31 is connected to the power supply voltage in the operation at the power supply voltage of 5 V, p⁺If the potentials of the mold region 34 and the wiring 15 are 3 V or less, the p-type region 32 is depleted, and the neutral region disappears.
[0158]
The above-described depletion voltage changes sensitively mainly with respect to the impurity concentration and the junction depth of each of the n-type well region 31, the p-type region 32, and the first n-type surface region 33. Therefore, the manufacturing variation of the depletion voltage is relatively large, for example, about ± 1.0 V at ± 3σ. However, by setting the depletion voltage and the operating point in appropriate regions, the depletion voltage can be reduced. A high yield can be maintained even if there is variation.
[0159]
In the present embodiment, the n-type surface region 43 is provided in order to suppress the generation of carriers on the surface of the offset region. However, the present invention is not limited to the n-type. Current suppression can be realized. In this case, the p-type neutral region increases, but the p-type may be used when the capacity of the light-receiving unit has a margin by design. In any case, from the viewpoint of reducing dark current and preventing breakdown, the impurity concentration in the offset region is 10%.¹⁶-10¹⁸cm^-3Degree, more preferably 5 × 10¹⁶~ 5 × 10¹⁷cm^-3It is.
[0160]
The n-type well effect 31 is formed in the p-type substrate 6 and has a structure in which the periphery is surrounded by the p-type well region 7 for each pixel.
[0161]
Next, the method for manufacturing the light receiving element according to the present embodiment will be described with reference to FIGS.
[0162]
An n-type well region 31 and a p-type region 7 are formed on the surface side of the p-type semiconductor substrate 6.
[0163]
The field insulating film 5 is formed by selective oxidation. After a P-type semiconductor region 32 serving as a photodiode is formed inside a region surrounded by the field insulating film 5, an n-type semiconductor region 33 is formed on the surface thereof.
[0164]
Ion implantation is performed on the substrate surface to form an n-type semiconductor layer 43. Then, a p-type electrode region 34 is formed.
[0165]
The distance between the electrode region 34 and the semiconductor region 33 (the width of the offset region) is 0.4 μm to 1.5 μm, and more preferably 0.5 μm to 1.0 μm. And the concentration is lower by at least one order of magnitude than the electrode region 34 and is higher than that of the semiconductor region 32.
[0166]
Next, another embodiment of the read and reset circuit used in the present invention will be described again with reference to FIGS.
[0167]
FIG. 21 is a circuit diagram of the circuit according to the present embodiment.
[0168]
In FIG. 21, D1 is a photodiode as a light receiving element according to each embodiment of the present invention, M2 is a PMOS transistor of an amplifying element, and forms a source follower with a constant current source via a selection switch M3. . M1 is a reset switch, and M3 is a selection switch. M4 is a transfer switch for transferring a signal from the photodiode to the input terminal of the source follower.
[0169]
The optical signal and the reset signal read from the source follower are respectively transferred to the memory unit ME, and are output to the outside via the buffer B1, the coupling capacitor C, and the buffer B2 via the read scanning circuit RE and the like.
[0170]
According to the present embodiment, in particular, as a result of suppressing the area of the electrode to 1 μm square, the junction capacitance can be suppressed to 0.1 fF. As a result, reset noise can be suppressed to about four electrons, and a solid-state imaging device having no afterimage even with a dynamic range of 10 bits can be provided with a high yield.
[0171]
Next, another read and reset circuit used in the present invention will be described. This circuit is disclosed in Japanese Patent Application Laid-Open No. 9-205588.
[0172]
FIG. 22 is an equivalent circuit diagram of one pixel of the circuit described in the above publication.
[0173]
In FIG. 22, here, for each pixel, a light receiving element D1, a reset MOS switch M1 for resetting the light receiving element D1, a first MOS source follower M2 for converting a signal charge of the light receiving element D1 into a voltage signal, and a light receiving element D1 A MOS switch M3 for holding a noise signal at the time of reset during the accumulation period, a holding capacitor 605, a second MOS source follower M4 for converting the signal of the holding capacitor 605 into an impedance, and a MOS for reading a noise signal charge immediately after reset. The switch 607 includes a switch 607, a noise signal holding capacitor 609, a MOS switch 608 for reading an optical signal charge after storing an optical signal, and a light signal holding capacitor 610.
[0174]
Further, this circuit includes a shift for sequentially reading out the noise signal of the noise signal holding capacitor 609 and the optical signal of the optical signal holding capacitor 610 to the noise signal common output line 690 and the optical signal common output line 691, respectively. A register 613, buffer amplifiers 614 and 614 'for converting the voltages of the noise signal common output line 690 and the optical signal common output line 691 into impedances, and the noise signal common output line 690 and the optical signal common output line 691 A differential amplifier 615 for obtaining a voltage difference signal and amplifying the signal, and an output buffer amplifier 692 for impedance-converting the output of the differential amplifier 615 and outputting a signal to the outside of the photoelectric conversion device. Is provided. A common output line reset unit 693 for resetting the noise signal common output line 690 and the optical signal common output line 691 every time one pixel is read is also provided.
[0175]
The light output voltage VP of the photoelectric conversion device shown in FIG. 22 is represented by the following [Equation 1].
[0176]
(Equation 1)
Vp = [QP / Cpd] · Gsf1 · Gsf2 · [CT / (CT + CH)] · Gamp
here,
QP: Optical signal charge
CPD: Light receiving unit capacity
Gsf1: the gain of the first source follower M2
Gsf2: gain of second source follower M4
CT: capacitance value of noise signal and optical signal storage capacitance
CH: capacitance value of the common output line capacitance of the noise signal and the optical signal
Gamp: gain of differential amplifier 615
It is.
[0177]
In FIG.
V1PD: potential of the light receiving element immediately after resetting the light receiving element,
V2PD: the potential of the light receiving element after photocharge accumulation,
Then, the above equation can be represented as the equation of [Equation 2].
[0178]
(Equation 2)
V2PD−V1PD = ΔVPD = [QP / Cpd] = [Vp / [Gsf1 · Gsf2 · [CT / (CT + CH)] · Gamp]]
Here, ΔVPD is a potential change of the light receiving element due to the photocharge.
[0179]
Accordingly, by setting V1PD and V2PD in the depletion region in the light receiving element in the above formula, a highly sensitive photoelectric conversion device can be realized.
[0180]
In this embodiment, in each of the above equations,
Gsf1 = Gsf2 = 0.9
CT / (CT + CH) = 0.5
Gamp = 20
Power supply voltage (VDD): 5V
Depletion voltage of light receiving element: -2V
Saturation output of light output (Vp): 2V
Reset voltage (V_R): 1V
Was set.
[0181]
Therefore, according to the above equations,
(A) Potential (V1PD) of light receiving element immediately after reset: about 0.70 V
(B) Potential (V2PD) of light receiving element at the time of saturation output: about 0.95V
It becomes.
[0182]
From the values of the power supply voltage and the depletion voltage, it is understood that the light-receiving element portion is in a depleted state if the potential of the light-receiving element portion is 3 V or less.
[0183]
According to (a) and (b) in the above equations, the potential (V1PD) of the light receiving element immediately after reset and the potential (V2PD) of the light receiving element at the time of saturation output are both 3 V or less. It can be used in a small range and has high sensitivity.
[0184]
Incidentally, as a result of measuring the capacitance of the light receiving portion, it was found that the total of the parasitic capacitance such as the junction capacitance of the electrode region of the light receiving element, the gate capacitance of the source follower MOS, the junction capacitance of the drain of the reset MOS, the wiring capacitance, etc. It was 25 fF.
[0185]
Further, in the present embodiment, when the variation of the depletion voltage is about −2 V ± 2 V, the depletion region of the light receiving element portion is 1 V to 5 V, but the operating point in this embodiment is the minimum value of the depletion region. Since it is smaller than 1 V, a high yield can be maintained even if the depletion voltage varies by about ± 2 V.
[0186]
Note that the reason why the potential of the light receiving element portion immediately after the reset is lower than the reset voltage (Vres) is that the potential of the light receiving element portion is turned off when the reset switch is turned off because an NMOS transistor is used for the reset switch. Is turned to the minus side.
[0187]
Further, the present embodiment has shown an example in which the present inventors have applied to a photoelectric conversion device proposed in Japanese Patent Application Laid-Open No. 9-205588, but the present invention is not limited to this embodiment. For example, it goes without saying that the present invention can be applied to other photoelectric conversion devices and solid-state imaging devices.
[0188]
Although not shown, this embodiment constitutes a primary photoelectric conversion device provided with 344 pixels using the pixels having the above configuration as line sensors.
[0189]
By using the photoelectric conversion device of the present embodiment to form a contact image sensor and use it as an image reading device of an image input system such as a facsimile or an image scanner, the afterimage characteristics are good even during high-speed operation. Therefore, high-quality image reading can be realized, and a low-cost image reading apparatus can be provided because of high yield.
[0190]
(Embodiment 8)
Hereinafter, Embodiment 8 of the present invention will be described with reference to FIGS. 23 (A) and 23 (B).
[0191]
FIG. 23A shows an upper surface of the light receiving element portion of the present embodiment, and FIG. 23B shows a cross section taken along line JJ ′ of FIG.
[0192]
23A and 23B, reference numeral 51 denotes a first semiconductor region which is a semiconductor substrate, and 52 denotes a second semiconductor region. Here, the respective conductivity types are n-type and p-type. The second semiconductor region 52 is formed inside the opening OP defined by the light shielding layer 17.
[0193]
A depletion layer DL is formed by a pn junction between the first semiconductor region 51 and the second semiconductor region 52. A reverse bias is applied between the first semiconductor region 51 and the second semiconductor region 52, and a large depletion layer DL extends toward the region 51 with a low impurity concentration. The electrode 15 is connected to the second semiconductor region 52 via the contact hole CH of the insulating film 9.
[0194]
When light is applied to the light receiving element, charges are generated in and around the depletion layer DL. The charge is collected in the second semiconductor region 52. On the other hand, many crystal defects exist at the interface between the main surface of the semiconductor substrate and the insulating film 9. This crystal defect becomes a generation level of an electron-hole pair and causes a dark current. In particular, the influence of crystal defects near the depletion layer DL is large.
[0195]
In addition, when the electrode 15 is formed, if the formation position extends to a position where the depletion layer DL is not covered by the electrode 15, damage due to etching or the like increases the amount of crystal defects and dark current.
[0196]
Therefore, in the structure of the light receiving element of the present embodiment, the portion 59 where the depletion layer DL and the insulating film 9 are in contact with each other is covered with the electrode 15 via the insulating film 9 so that the etching damage at the time of electrode formation is reduced. Since it does not reach DL, the dark current can be reduced.
[0197]
In addition, the electrode 15 is always formed on the portion 59 where the depletion layer DL and the insulating film 15 are in contact with each other in consideration of the misalignment in the photolithography. This suppresses the amount of crystal defects generated near the depletion layer DL from fluctuating due to process variations. Therefore, variations in dark current due to process variations are reduced.
[0198]
In the present embodiment, for example, Al, Al alloy, Ti, Ti alloy, W, W alloy, Co, Co alloy, Ta, Ta alloy, Mo, Mo alloy, Cu, Cu alloy, WN, TiN , TaN, Cr, Cr alloys and other metals, alloys and compounds are used. Or, they may be a plurality of types of laminates. Alternatively, it can be used as a conductive material mainly composed of silicon, such as doped polysilicon.
[0199]
(Embodiment 9)
FIG. 24A shows an upper surface of the light receiving element, and FIG. 24B shows a cross section taken along line KK ′ of FIG.
[0200]
In FIG. 24, 66 is an n-type semiconductor substrate, and 67 is a buried n-type semiconductor substrate 66 formed by ion implantation.⁺Mold region, 61 is n⁺N, which is the first semiconductor region formed on the mold region 67⁻Type epitaxial layer, 68 is n⁻Buried n-type epitaxial layer 61 by ion implantation.⁺N in contact with the mold area⁺It is a type area.
[0201]
Reference numeral 62 denotes a second semiconductor region and an electrode region, specifically, a p-type high-concentration impurity region. Reference numeral 63 denotes an n-type region, which is provided to suppress the spread of the depletion layer DL on the main surface of the semiconductor substrate (the surface of the epitaxial layer). The electrode 15 made of a metal or the like containing Al as a main component is electrically connected to the electrode region 62 via a contact hole CH of the insulating film 9 formed on the main surface of the substrate. Further, 17 is a light shielding layer, OP is an opening, 5 is a LOCOS insulating film for element isolation, and 9 is an interlayer insulating film for insulating the light shielding layer 17 from the electrode 15.
[0202]
In this embodiment, the n-type substrate 66 and n⁺Mold region 67 and n⁻Type epitaxial layer 61 and n⁺The semiconductor portion formed by the mold region 68, the n-type region 63, and the electrode region 62 is referred to as a substrate.
[0203]
In FIG. 24, n⁻Type epitaxial layer 61 with n⁺By forming a structure surrounded by the mold regions 67 and 68, a potential barrier was formed. As a result, holes among carriers generated by light are finally collected in the p-type electrode region 62 having the lowest potential.
[0204]
The depletion layer DL is formed around the electrode region 62. Here, the impurity concentration of the electrode region 62 is set to about 3 × 10¹⁹cm^-3, N-type region 63 has an impurity concentration of about 2 × 10¹⁷cm^-3When a reverse bias voltage of 3 V is applied to these, the layer width of the depletion layer DL is about 0.14 μm. Most of the depletion layer DL has the electrode region 62 and n⁻N from the pn junction surface with mold region 61⁻It spread to the mold region 61 side. On the substrate surface, the spread of the depletion layer DL is suppressed by the n-type region 63.
[0205]
The electrode 15 is arranged, for example, 0.4 μm larger than the electrode region 62 so as to cover the upper part of the portion where the depletion layer DL is in contact with the interlayer insulating film 9. As a result, the crystal defects caused by the etching damage when the electrode 62 is formed or the damage due to the resist ashing do not reach the depletion layer DL, and the dark current is reduced.
[0206]
The dark current was compared between the case where the electrode 15 was formed so as to cover the portion 59 where the depletion layer DL and the insulating film 9 were in contact with each other. As a result, the portion where the depletion layer DL was in contact with the insulating film 9 was obtained. Is formed so as to completely cover the upper portion, the dark current is reduced to 2/3. That is, the dark current can be reduced depending on the size and the formation position of the electrode 15.
[0207]
Although the substrate 66 and the regions 67 and 68, the epitaxial layer 61, and the region 63 are described as n-type and the region 62 is described as p-type for the sake of simplicity, the present embodiment is limited to this conductivity type. Instead, each may be of the opposite conductivity type.
[0208]
In the present embodiment, n⁻Type epitaxial layer 61⁺As a structure surrounded by the mold regions 67 and 68, a potential barrier is formed to prevent photocarriers from being mixed into adjacent pixels. Since optical carriers do not mix into adjacent pixels, high-quality resolution patterns can be obtained by almost completely suppressing the occurrence of crosstalk.
[0209]
(Embodiment 10)
FIG. 25A shows the top surface of the light receiving element, and FIG. 25B shows a cross section taken along line LL ′ of FIG.
[0210]
In FIG. 25, reference numeral 76 denotes an n-type substrate. 77 is a buried n formed by ion implantation into an n-type substrate 76;⁺Mold region, 71 is n⁺N, which is the first semiconductor region formed on the mold region 77⁻Type epitaxial layer, 78 is n⁻Formed by ion-implantation into the p-type epitaxial layer⁺This is a mold region and surrounds the periphery of the epitaxial layer 71.
[0211]
Reference numeral 72 denotes a second semiconductor region. Reference numeral 74 denotes an electrode region, specifically, a p-type high-concentration impurity region. Reference numeral 73 denotes an n-type region, which is provided to suppress the spread of the depletion layer DL on the main surface of the substrate. Reference numeral 15 denotes an electrode formed of a metal or the like containing Al as a main component. Electrode 15 is electrically connected to electrode region 74 through contact hole CH of insulating film 9 formed on the main surface of the substrate.
[0212]
When the electrode region 74 is miniaturized and the depletion layer DL spreads over the electrode region having a high impurity concentration, a dark current increases due to defects in the depletion layer. p⁻The semiconductor region 72 of the mold is provided to suppress it. OP is an opening, 5 is an element isolation insulating film, and the upper interlayer insulating film 9 is an insulating film for insulating the light shielding layer 17 from the electrode 15.
[0213]
In this embodiment, the n-type substrate 76 and the n-type⁺Mold region 77 and n⁻Type epitaxial layer 71 and n⁺What is formed by the mold region 78, the n-type region 73, and the electrode region 74 is referred to as a substrate.
[0214]
In FIG. 25, n⁻Type epitaxial layer 71⁺Since the potential barrier is formed by the structure surrounded by the mold regions 77 and 78, the holes among the carriers generated by the light are finally transferred to the p-type electrode region 74 having the lowest potential. Collected.
[0215]
Depletion layer DL is formed around p-type region 72. Here, the impurity concentration of the p-type region 72 is set to about 3 × 10¹⁸cm^-3, N-type region 73 has an impurity concentration of about 2 × 10¹⁷cm^-3When a reverse bias voltage of 3 V was applied to these, the layer width of the depletion layer DL was about 0.15 μm. Most of the depletion layer DL has spread to the n-type region 71 side from the pn junction surface of the p-type region 72 and the n-type region 71.
[0216]
The electrode 15 is arranged, for example, 0.4 μm larger than the p-type region 72 so as to cover a portion 69 where the depletion layer DL and the insulating film 9 are in contact. As a result, crystal defects on the substrate surface caused by etching damage when the electrode 15 is formed and damage due to resist ashing do not reach the depletion layer DL, so that dark current can be reduced.
[0217]
For simplicity, the substrate 76 and the regions 77 and 78, the epitaxial layer 71 and the region 73 are described as n-type, and the regions 72 and 74 are described as p-type. However, this embodiment is limited to this conductivity type. Instead, each may be of the opposite conductivity type.
[0218]
(Embodiment 11)
FIG. 26A is a top view of a light receiving element according to Embodiment 11 of the present invention, and FIG. 26B is a cross-sectional view taken along a line MM ′ in FIG.
[0219]
In FIG. 26, 86 is a p-type substrate, 81 is an n-type region as a first semiconductor region, 82 is a p-type region as a second semiconductor region, and 83 is n as a third semiconductor region.⁺It is a type area.
[0220]
84 is a p-type high concentration impurity region which is an electrode region, that is, p⁺Mold region, and n⁺The mold region 83 and the offset region OF are arranged therebetween. Reference numeral 15 denotes an electrode, which is formed of a metal containing Al as a main component. The electrode 15 is connected to the p-type substrate 86 via a contact hole CH of the insulating film 9 formed on the main surface of the p-type substrate 86.⁺It is electrically connected to the mold region 84. DL is a depletion layer.
[0221]
The p-type region 82 and the n-type region 81 and n⁺The structure is sandwiched between the mold regions 83. As a result, the depletion layer DL is formed at the p-type junction on the lower surface side and the pn junction on the upper surface side of the p-type region 82, and a state like a low potential groove is formed in the semiconductor region 82.
[0222]
As a result, of the charges generated by light, holes are collected in the p-type region 82, and finally, p⁺Collected in the mold area 84. Further, the impurity concentration of the n-type region 81 and the p-type region 82, n⁺By appropriately setting the impurity concentration and the junction depth of the mold region 83 and the bias voltage of the pn junction, almost the entire n-type region 81 can be depleted. As a result, the p-type region 82 hardly contributes to the capacitance of the light receiving element, and the capacitance of the light receiving element can be reduced.
[0223]
Without forming the offset region OF, the electrode region 84 and n⁺When the mold region 83 is brought into contact, the electrode region 84 and n⁺When a reverse bias is applied to the mold region 83, breakdown is caused, and a large amount of leakage current⁺It is not preferable because it flows into the mold region 84.
[0224]
Further, if the offset region OF is too small, the alignment error in photolithography or the like causes p⁺Mold region 84 and n⁺The probability of contact with the mold region 83 increases. This lowers the yield of the light receiving elements.⁺Mold region 84 and left and right n⁺A 1 μm offset region OF is provided between each of the mold regions 83.
[0225]
The electrode 15 was formed so as to cover a portion 89 where the depletion layer DL and the insulating film 9 were in contact. Therefore, a crystal defect on the substrate surface caused by etching damage at the time of forming the electrode 15 or damage by ashing of the resist does not reach the depletion layer DL, and the dark current is reduced.
[0226]
The present embodiment is not limited to this conductivity type, and each conductivity type may be a conductivity type opposite to that described above.
[0227]
Further, in the present embodiment, the n-type region 81 is formed in the p-type substrate 86 to prevent optical carriers from being mixed into adjacent pixels. Therefore, the occurrence of crosstalk is almost completely suppressed, and a high-quality resolution pattern can be obtained.
[0228]
Even if an optical carrier equal to or larger than the accumulated saturation value is generated in a certain pixel, the overflowing optical carrier is absorbed by the p-type region 86 around the n-type region 81, and does not affect other pixels. A high-quality image with little bleeding can be obtained.
[0229]
With reference to FIGS. 27A to 27C and FIGS. 28A to 28C, the method for manufacturing the light receiving element according to the present embodiment will be described.
[0230]
A p-type semiconductor substrate 86 is prepared, and an n-type region 81 made of an n-type semiconductor is formed by ion implantation or the like (FIG. 27A).
[0231]
The field insulating film 5 is formed by a selective oxidation method, and thereafter, a p-type semiconductor region 82 is formed (FIG. 27B).
[0232]
n⁺After the formation of the semiconductor region 83 of the⁺A mold electrode region 84 is formed. Here, if necessary, low-concentration dopant ions may be implanted into the offset region between the semiconductor region 83 and the electrode region 84 (FIG. 27C).
[0233]
Next, an insulating film 9 made of PSG (PhosphoSilicate Glass: oxide film doped with phosphorus), BSG (BoroSilicate Glass), BPSG (BoroPhosphoSilicata Glass), or the like is formed, and an opening CH is formed on the electrode region 84 ( FIG. 28 (A)).
[0234]
Next, a layer 15 of a conductive material such as Al-Cu is formed by sputtering or the like (FIG. 28B). At this time, a barrier metal such as TiN may be formed below the conductive material layer 15.
[0235]
Then, the conductive material layer 15 is₃, Cl₂Then, patterning is performed by dry etching using, for example, leaving a layer 15 of a conductive material so as to cover the offset portion. Thus, the anode electrode 15 is obtained.
[0236]
The read and reset circuits shown in FIGS. 4, 7, 21 and 22 can also be used in the light receiving elements of the eighth to eleventh embodiments described above.
[0237]
Further, the present invention can be preferably applied to the photoelectric conversion device proposed in Japanese Patent Application Laid-Open No. 9-205588. For example, other photoelectric conversion devices and solid-state imaging devices can be applied. Thus, a solid-state imaging device having a high yield in the manufacturing process can be manufactured, and thus a high-quality device can be provided.
[0238]
【The invention's effect】
By using the photoelectric conversion device of the present embodiment to form a contact image sensor and using it as an image reading device of an image input system such as a facsimile or an image scanner, for example, a low dark current is realized, so that high quality Since image reading can be realized and the yield is high, a low-cost image reading device can be provided.
[0239]
As described above, a light-receiving element capable of reducing dark current can be obtained, and a high-performance photoelectric conversion device with less variation in dark current can be realized even when manufacturing processes vary. It is possible to provide an image reading apparatus and an image input system which can obtain a simple image and are inexpensive.
[Brief description of the drawings]
FIG. 1A is a top view of a light receiving element according to an embodiment of the present invention, FIG. 1B is a cross-sectional view of the light receiving element according to an embodiment of the present invention, and FIG. FIG. 4D is a schematic diagram illustrating a potential profile in a vertical direction, and FIG. 4D is a schematic diagram illustrating a potential profile in a vertical direction of a light receiving element according to an embodiment of the present invention.
FIG. 2 is a diagram showing an impurity concentration distribution in a light receiving element according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating a relationship between an applied voltage and a capacitance in a light receiving element.
FIG. 4 is a circuit diagram of a read and reset circuit used in the present invention.
FIG. 5A is a top view of a light receiving element according to the embodiment of the present invention, and FIG. 5B is a cross-sectional view of the light receiving element according to the embodiment of the present invention.
FIGS. 6A to 6C are schematic cross-sectional views illustrating an example of a method for manufacturing a light receiving element according to the embodiment of the present invention.
FIG. 7 is a circuit diagram of a read and reset circuit used in the present invention.
FIG. 8A is a top view of a light receiving element according to an embodiment of the present invention, and FIG. 8B is a cross-sectional view of the light receiving element according to an embodiment of the present invention.
FIG. 9 is a schematic diagram showing a lateral potential profile of the light receiving element according to the embodiment of the present invention.
FIGS. 10A to 10C are schematic cross-sectional views illustrating an example of a method for manufacturing a light-receiving element according to an embodiment of the present invention.
FIG. 11A is a top view of a light receiving element according to an embodiment of the present invention, and FIG. 11B is a cross-sectional view of the light receiving element according to the embodiment of the present invention.
FIG. 12 is a top view of the light receiving element according to the embodiment of the present invention.
FIG. 13 is a cross-sectional view of a light receiving element according to an embodiment of the present invention.
FIG. 14 is a cross-sectional view of a light receiving element according to an embodiment of the present invention.
FIG. 15 is a top view of the light receiving element according to the embodiment of the present invention.
FIG. 16 is a cross-sectional view of a light receiving element according to an embodiment of the present invention.
FIG. 17 is a cross-sectional view of a light receiving element according to an embodiment of the present invention.
FIG. 18 is a top view of the light receiving element according to the embodiment of the present invention.
FIG. 19 is a sectional view of a light receiving element according to the embodiment.
FIGS. 20A to 20D are schematic cross-sectional views illustrating an example of a method for manufacturing a light receiving element according to an embodiment of the present invention.
FIG. 21 is a circuit diagram of a read and reset circuit used in the present invention.
FIG. 22 is a circuit diagram of a read and reset circuit used in the present invention.
FIG. 23A is a top view of a light receiving element according to an embodiment of the present invention, and FIG. 23B is a cross-sectional view of the light receiving element according to an embodiment of the present invention.
24A is a top view of a light receiving element according to an embodiment of the present invention, and FIG. 24B is a cross-sectional view of the light receiving element according to an embodiment of the present invention.
FIG. 25A is a top view of a light receiving element according to the embodiment of the present invention, and FIG. 25B is a cross-sectional view of the light receiving element according to the embodiment of the present invention.
26A is a top view of a light receiving element according to an embodiment of the present invention, and FIG. 26B is a cross-sectional view of the light receiving element according to an embodiment of the present invention.
FIGS. 27A to 27C are diagrams showing an example of the method for manufacturing the light receiving element according to the present embodiment.
FIGS. 28A to 28C are views showing an example of the method for manufacturing the light receiving element according to the present embodiment.
FIGS. 29A and 29B are cross-sectional views of a conventional light receiving element.
FIG. 30 is a top view of a conventional light receiving element.
FIG. 31 is a cross-sectional view of a conventional light receiving element.
FIG. 32 is a cross-sectional view of a conventional light receiving element.
FIG. 33 is a sectional view of a conventional light receiving element.
[Explanation of symbols]
1,11,31 First semiconductor region
2, 12, 32 Second semiconductor region
3, 13, 33 Third semiconductor region
4,14,34 Low potential area (electrode area)
5 Device isolation area
15 Wiring
16 Power line
17 Shading layer
101 electrode area
102 Photodiode area (light receiving area)
103 Edge
104 Edge
605 storage capacity
609 Noise signal holding capacity
610 Optical signal holding capacity
614 buffer amplifier
615 differential amplifier
690 Noise signal common output line
691 Optical signal common output line
M1 Reset MOS transistor
M2 amplifying MOS transistor
M3 selection MOS transistor

Claims (14)

A first semiconductor region of a first conductivity type;
A second semiconductor region of a second conductivity type disposed on the first semiconductor region;
A third semiconductor region of a first conductivity type disposed on a surface of the second semiconductor region;
A second conductivity type electrode region connected to an anode or a cathode electrode made of a conductor,
Said third semiconductor region is formed so as to surround the periphery of the electrode region, the internal region of a lower impurity concentration than high and the electrode region impurity concentration than the second semiconductor region second conductivity type A light receiving element formed between the electrode region and the second semiconductor region , wherein the electrode region is disposed on a surface of the internal region . The light receiving element according to claim 1,
The electrode region is in a floating state and accumulates photo-generated charges,
A light receiving element, wherein a bias voltage for applying a reverse bias between the first semiconductor region and the second semiconductor region is applied to the first semiconductor region. The light receiving element according to claim 1,
A light-receiving element, wherein a potential gradient capable of moving photo-generated charges toward the electrode region is formed between the electrode region and the second semiconductor region. The light receiving element according to claim 1,
The light receiving element according to claim 1, wherein the internal region includes a plurality of regions having different impurity concentrations. The light receiving element according to claim 1,
The light receiving element is characterized in that the internal region is formed so as to surround the periphery of the electrode region. The light receiving element according to claim 1,
The light receiving element according to claim 1, wherein the internal region is formed at a position shallower than the second semiconductor region. The light receiving element according to claim 1,
The light-receiving element according to claim 1, wherein the first semiconductor region includes one of a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, and a well formed in the semiconductor substrate. A first semiconductor region of a first conductivity type;
A second semiconductor region of a second conductivity type disposed on the first semiconductor region;
A second conductivity type electrode region disposed on the surface of the second semiconductor region and connected to an anode or a cathode electrode made of a conductor;
A third semiconductor region of a first conductivity type, which is disposed on a surface of the first semiconductor region , and is formed so as to surround the electrode region and the periphery of the second semiconductor region;
Said anode or cathode electrode, and the whole of the second semiconductor region, a depletion layer is formed between the electrode region and the third semiconductor region, characterized in that the cover, and all parts in contact with the insulating film Light receiving element. The light receiving element according to claim 8,
It said first semiconductor region is a light receiving element characterized epitaxial layer der Rukoto. The light receiving element according to claim 8,
It said second semiconductor region, the light receiving element characterized in that it has a different portion of the impurity concentration from each other. The light receiving element according to claim 8,
The second semiconductor region has a high concentration region with a high impurity concentration and a low concentration region with a low impurity concentration, and the third semiconductor region is formed on an upper surface of the low concentration region. Light receiving element. The light receiving element according to claim 8,
The light-receiving element, wherein the anode or the cathode electrode covers at least an area above the third semiconductor region. 9. A plurality of light receiving elements according to claim 1 or 8, a reading and reset circuit for reading and resetting photocharges from the plurality of light receiving elements, respectively, and a buffer circuit for buffering an output of the reading and reset circuit. And a coupling capacitor for cutting a DC component of the output of the buffer circuit. 9. A plurality of light receiving elements according to claim 1 or 8, a read and reset circuit for reading and resetting photocharges from the plurality of light receiving elements, a selection switch for selecting the respective photocharges, and the reading. A photoelectric conversion device, comprising: a memory unit for temporarily storing an output of the reset circuit; and a readout scanning unit for reading out the memory unit in time series.

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