JP2005347740A - Photoelectric converter and imaging system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a PD forming well structure contributing to the improvement of imaging performance while using an existing CMOS formation manufacturing method. <P>SOLUTION: In the photoelectric converter wherein an pixel containing an photoelectric conversion region for converting light into a signal charge and a peripheral circuit containing a circuit for processing the signal charge outside the pixel region where the pixel is formed are disposed on the same substrate, the photoelectric conversion region is formed by containing a first semiconductor region of a primary conductivity type formed on the substrate and a second semiconductor region of a secondary conductivity type which is the same conductive type as in the signal charge, the peripheral circuit is formed by containing a third conductive region of the first conductive type, and the impurity concentration of the first semiconductor region is configured so as to be higher than that of the third semiconductor region. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a photoelectric conversion device, and more specifically to a MOS type photoelectric conversion device.

  In recent years, the photoelectric conversion device is used as a solid-state imaging device of a two-dimensional image input device centering on a digital still camera and a video camcorder. Alternatively, it is used as a one-dimensional image reading apparatus centering on facsimiles and scanners, and demand is rapidly increasing.

  As this photoelectric conversion device, a CCD (Charge Coupled Device) or a MOS type sensor is used. As a representative of MOS type sensors, CMOS photoelectric conversion devices (hereinafter referred to as “CMOS sensors”) have been put into practical use (see Patent Document 1 below).

  FIG. 9 is an example of a circuit configuration diagram of a pixel of a solid-state imaging device equipped with a CMOS sensor.

  In FIG. 9, 1 is a photodiode (hereinafter referred to as “PD”) that converts light into signal charges, 2 is a transfer MOS transistor that transfers signal charges generated by the PD, and 3 is temporarily transferred signal charges. Floating diffusion region (hereinafter referred to as “FD”) 4 is stored, 4 is a reset MOS transistor for resetting FD3 and PD1, 5 is a selection MOS transistor for selecting any one row in the array, 6 Is a source follower MOS transistor that converts the signal charge of FD3 into a voltage and amplifies it by a source follower type amplifier, and these constitute a pixel. Reference numeral 7 is a readout line that is shared by one column and reads out a pixel voltage signal, and 8 is a constant current source for making the readout line 7 a constant current. Although not shown, one or both of a circuit for processing a signal from the pixel and a driving circuit (shift register) for driving a transistor in the pixel are formed as a peripheral circuit in the same substrate. ing.

  Each pixel (except for the constant current source 8) is arranged in an array to constitute an imaging device.

  FIG. 10 is a schematic cross-sectional view of a pixel of an imaging device equipped with a CMOS sensor, and particularly shows a portion of PD1 and transfer MOS transistor 2 in FIG. 11 is an N-type silicon substrate, 12 is a P-type well, 13a is a gate oxide film of a MOS transistor, 13b is a thin oxide film on the light receiving portion, 14 is a gate electrode of the transfer MOS transistor 2, and 15 is N of PD1. Type anode, 16 is a surface P type region for embedding PD1, 17 is a selective oxide film for element isolation, and 18 is an N type high concentration region which forms FD3 and also serves as a drain region of transfer MOS transistor 2 , 19 is a silicon oxide film that insulates the gate electrode 14 from the metal first layer 21, 20 is a contact plug, 22 is an interlayer insulating film that insulates the metal first layer 21 and the metal second layer 23, and 24 is a metal second layer. Reference numeral 23 denotes an interlayer insulating film that insulates the metal layer 23 from the metal layer 25, and a passivation film 26.

  In the color photoelectric conversion device, a color filter layer (not shown) is formed on the passivation film 26 and a microlens for improving sensitivity is formed. Light incident from the surface enters the PD through the opening without the metal third layer 25. The light is absorbed in the N-type anode 15 or the P-type well 12 of the PD to generate an electron / hole pair. Among these, electrons are accumulated in the N-type anode 15.

  Further, as a feature of the CMOS sensor, a PD forming well for forming a light receiving region in the pixel portion and a peripheral circuit forming well for forming a driving device are of the same conductivity type, so that a conventional CMOS process is performed. Advantages that can be used are listed. That is, the biggest feature of a CMOS sensor is that an inexpensive solid-state imaging device can be manufactured using an existing semiconductor manufacturing line without requiring a special manufacturing line like a CCD.

  11 and 12 are diagrams showing the well forming methods of the conventional CMOS sensor using a general CMOS process.

  Here, an example using an N-type silicon substrate is shown.

  First, a silicon thermal oxide film 27 and a silicon nitride film 28 are formed on the N-type silicon substrate 11 (FIG. 11A).

  After removing the silicon nitride film 28 in a desired region by the pattern of the photoresist 29, a P-type impurity 30 is introduced by ion implantation (FIG. 11B). When the thermal oxidation process is performed after removing the photoresist 29, the silicon oxide film 36 is formed only in the region where the P-type impurity 30 is introduced. Next, the aforementioned silicon nitride film 28 is removed, and N-type impurities 32 are introduced by ion implantation (FIG. 11C). At this time, since the aforementioned oxide film 36 is formed on the region where the P-type impurity 30 is introduced, the N-type impurity 32 is self-aligned in a region other than the region where the P-type impurity 30 is formed. It is formed. Needless to say, the oxide film 36 is formed to a thickness that does not penetrate when the N-type impurity 32 is implanted.

  As described above, after introducing the P-type impurity 30 and the N-type impurity 32 into a desired region, a thermal diffusion process is performed to obtain a desired depth and concentration profile, and the P-type well 12 and the N-type well 33 are formed. It forms (FIG.11 (d)).

  Subsequently, once all the oxide film is removed, a silicon thermal oxide film 27 and a silicon nitride film 28 are formed again, a desired region is patterned with a photoresist 29, and the silicon nitride film 28 is etched (FIG. 12A). ).

  Finally, after being electrically isolated by the selective oxide film 17, well regions for forming MOS transistors, resistors, capacitors, diodes, and the like are formed (FIG. 12B).

  Thereafter, the gate oxide film 40 and the gate electrode 41 of the MOS transistor are formed, the N-type region 42 of the PD and the P-type region 43 of the surface are formed, the source / drain 44 of the NMOS transistor and the source / drain 45 of the PMOS transistor. After that, a solid-state imaging device is completed through a wiring formation process (not shown) (FIG. 12C).

  FIG. 12B shows that the PD formation P-type well, the peripheral circuit formation P-type well, and the peripheral circuit formation N-type well are formed by the selective oxide film 17 in order from the left. In addition, there is an advantage that an inexpensive and easy process can be adopted by a minimum photolithography process and a self-aligned well formation method.

  Further, although not a conventional CMOS process, a method of controlling the concentration profile by providing a buried epitaxial region in the PD region as shown in Patent Document 2 below has been proposed.

  Patent Document 3 includes a plurality of photoelectric conversion elements and scanning means for reading signals of the photoelectric conversion elements, and the photoelectric conversion elements are impurity layers having a lower concentration than the impurity layer in which the scanning means is formed. There is a disclosure of a solid-state imaging device formed inside. This enables miniaturization of the MOS transistor by forming the scanning circuit in the high concentration impurity layer according to the proportional reduction rule. In addition, it is described that the photoelectric conversion part is formed in the low-concentration impurity layer, thereby extending the depletion layer around the PD and improving the photosensitivity.

Patent Document 4 describes a peripheral well in which a logic circuit is formed and a well in which a pixel cell is formed. Specifically, a configuration is disclosed in which the well in which the pixel cell is formed is a retrograde well, and the impurity concentration of the peripheral well decreases from the top to the bottom of the well (FIG. 12 of the specification). reference). Further, the impurity concentration is the same value of 1 × 10 ¹⁶ to 2 × 10 ¹⁸ atoms / cm ³ . In addition, the depth of the well to be formed is deeper in the well in which the PD region is formed (see FIG. 11 in the specification).
JP 2001-332714 A JP 2000-232214 A Japanese Patent Laid-Open No. 01-243462 US Pat. No. 6,444,014

  As described above, the CMOS type solid-state imaging device has an advantage that the existing CMOS forming and manufacturing method can be used, but includes several problems for improving the imaging performance.

  The first problem is that the impurity introduced into the peripheral circuit forming well region of the same conductivity type as the PD forming well region is the same as shown in the conventional example (FIG. 11B). In the example, the impurity concentration of the PD formation well region and the peripheral circuit formation P-type well region cannot be set separately. For example, in order to improve the spectral characteristics of incident light, it is not possible to reduce only the impurity concentration of the PD formation well, and the threshold value of the MOS transistor provided in the PD formation well is set to a peripheral circuit P-type well concentration. It is very difficult to control without changing.

  The second problem is that the thermal diffusion processing after introducing each impurity in the PD formation well region and the peripheral circuit formation well region is often performed in a lump as shown in FIG. For this reason, it is impossible in principle to control only the concentration profile depth of the PD formation well region. In order to improve the characteristics of the CMOS sensor, the concentration profile of the peripheral circuit formation well must be changed one by one. Inevitably, a serious design inconvenience occurs.

  The configuration described in Patent Document 3 has the following points to be examined. That is, in the configuration in which the concentration of the wells forming the peripheral circuit is high, the efficiency of collecting charges in the photoelectric conversion unit may not be sufficient. This may become a larger problem to be solved as pixels become finer and sensitivity decreases.

  Further, the configuration described in Patent Document 4 has the following points to be examined. That is, the well depth and well structure are different between the well for forming the photoelectric conversion portion and the well for forming the peripheral circuit, but the impurity concentration is the same, so that the photoelectric conversion is performed as described above. In some cases, the efficiency of collecting charges in the portion cannot be sufficiently obtained.

  Accordingly, an object of the present invention is to provide a photoelectric conversion device capable of realizing a PD formation well structure that contributes to improvement in imaging performance while using an existing CMOS formation manufacturing method.

  As means for achieving the above object, the present invention proposes to independently control and form the concentration profile of the peripheral circuit forming well of the same conductivity type as the PD forming well.

Therefore, the photoelectric conversion device of the present invention includes a pixel including a photoelectric conversion region that converts light into signal charge, and a peripheral circuit including a circuit for processing the signal charge outside the pixel region where the pixel is formed. In the photoelectric conversion device arranged on the same substrate,
The photoelectric conversion region is formed including a first semiconductor region of the first conductivity type formed on the substrate and a second semiconductor region of the second conductivity type that is the same conductivity type as the signal charge,
The peripheral circuit is formed including a third semiconductor region of the first conductivity type;
The impurity concentration of the first semiconductor region is higher than the impurity concentration of the third semiconductor region.

The photoelectric conversion device of the present invention includes a pixel including a photoelectric conversion region that converts light into signal charge, and a peripheral circuit including a circuit for processing the signal charge outside the pixel region where the pixel is formed. In the photoelectric conversion device arranged on the same substrate,
The photoelectric conversion region is formed including a first semiconductor region of the first conductivity type formed on the substrate and a second semiconductor region of the second conductivity type that is the same conductivity type as the signal charge,
The peripheral circuit is formed including a third semiconductor region of the first conductivity type;
Each of the first and third semiconductor regions has an impurity concentration peak.

  According to the present invention, since the concentration profile of the well in the PD region is set independently, the degree of freedom of design can be increased, and the characteristics of the device can be improved without changing circuit characteristics other than in the PD region. Further, by forming the well in the PD region deeply, the photoelectrically converted charge can be more efficiently guided to the PD on the surface side, and the sensitivity can be increased.

  An outline of an embodiment of the present invention will be described with reference to the drawings. Here, the well used in the description refers to a region where impurities of a desired conductivity type are diffused, and the manufacturing method thereof is not limited. It has the same function as the semiconductor region. Further, in this specification, a semiconductor substrate that is a material substrate may be expressed as a “substrate”, but such a material substrate is processed to form, for example, one or a plurality of semiconductor regions and the like. Alternatively, a member that is in the middle of a series of manufacturing steps or a member that has undergone a series of manufacturing steps can also be referred to as a substrate.

  A photoelectric conversion device according to one aspect of the present invention includes a pixel including a photoelectric conversion region that converts light into a signal charge, and a peripheral including a circuit for processing the signal charge outside the pixel region in which the pixel is formed In a photoelectric conversion device in which a circuit is arranged on the same substrate, a first conductivity type first semiconductor region formed on the substrate and a second conductivity type second semiconductor region having the same conductivity type as the signal charge The photoelectric conversion region is formed, and the peripheral circuit is formed including the third semiconductor region of the first conductivity type. The impurity concentration of the first semiconductor region is the same as that of the third semiconductor region. It is characterized by being higher than the impurity concentration. Here, referring to FIG. 7, for example, 108 to 111 correspond to the first semiconductor region of the first conductivity type. Here, a plurality of regions are illustrated, but a single semiconductor region may be used. 105 corresponds to the second semiconductor region. When the signal charge is an impurity region having the same conductivity type as the signal charge, it becomes an N-type impurity region and accumulates electrons. For example, 301 and 302 correspond to the third semiconductor region. Here, a plurality of regions are described, but a single region may be used. In the following description of the embodiments, the region corresponding to the second semiconductor region may not be clearly shown, but it is assumed that it is formed in the same manner as in FIG.

  In addition, a photoelectric conversion device according to another aspect of the present invention includes a pixel including a photoelectric conversion region that converts light into signal charge, and a circuit for processing the signal charge outside the pixel region in which the pixel is formed. In the photoelectric conversion device in which the peripheral circuit including the first conductive region is disposed on the same substrate, the first conductivity type first semiconductor region formed on the substrate and the second conductivity type second that is the same conductivity type as the signal charge. The photoelectric conversion region is formed to include the first semiconductor region, the peripheral circuit is formed to include the first conductivity type third semiconductor region, and each of the first and third semiconductor regions has an impurity concentration peak. It is characterized by having. As described above, this corresponds to each region in FIG.

  Hereinafter, it will be described in detail with reference to the drawings.

[Embodiment 1]
1 and 2 are diagrams showing a CMOS sensor well forming method, particularly a PD forming well and a peripheral circuit forming well forming method according to the first embodiment of the present invention.

  Here, the PD formation well includes pixel circuits such as a transfer MOS transistor, an FD, a reset MOS transistor, a selection MOS transistor, and a source follower MOS transistor for signal amplification in addition to the PD. In the peripheral circuit forming well, a circuit for processing a signal from the pixel, a driving circuit for driving the above-described transistor in the pixel, and the like are formed.

  First, a silicon thermal oxide film 27 and a silicon nitride film 28 as a mask material are formed on an N-type silicon substrate 11, and a desired region is patterned with a photoresist 29 (FIG. 1A).

  Next, the silicon nitride film 28 is patterned by dry etching (FIG. 1B), a selective oxide film 17 is formed by thermal oxidation, the nitride film is removed, and each well region separated by the selective oxide film is secured. (FIG. 1 (c)).

  Next, the photoresist 29a is patterned only in a region to be a PD formation well, and desired P-type impurities 30a and 30b are introduced by ion implantation (FIG. 1D). Since the P-type impurities 30a and 30b are introduced only into the PD region, the dose amount, acceleration voltage, and the number of ion implantations can be set freely, and the mask material has the maximum acceleration energy. Thus, the thickness of the resist 29a is determined. Although not shown in the figure, it goes without saying that a heat treatment can be freely applied in order to obtain a desired profile after resist removal after the implantation of the P-type impurities 30a and 30b.

  After setting the concentration profile of the well region for forming the PD in this way, the photoresist 29b is patterned only in the peripheral circuit P-type well region, and the P-type impurity 31 is introduced. Next, the N-type impurity 32 is sequentially introduced into the N-type well region for the peripheral circuit by the photoresist 29c in the same manner (FIG. 2B). Finally, in order to optimize the concentration profile of each well, a desired heat treatment is performed to form the PD forming well 34, the peripheral circuit forming P-type well 12, and the N-type well 33 (FIG. 2C).

  As described above, by using the method of this embodiment, an optimal well structure can be designed for each well.

FIG. 3 shows the concentration profile of the PD formation well region in the present embodiment, in particular, after patterning the PD formation well region, the P-type impurity 30a is changed to 5E11 to 1E13 atoms / cm ² , 40 to 700 keV, and the P-type impurity 30b. 2E11 to 1E14 atoms / cm ² and 700 keV to 2.7 MeV with multiple ion implantations, and then a drive process was performed in a N ₂ atmosphere at a temperature of 1000 to 1200 ° C. for 0.5 to 6 hours. It is the schematic diagram of the density | concentration profile of the BB cross section of FIG.2 (c) obtained in the case.

  The P-type impurities 30a and 30b may be the same material or different materials. In the case of different materials, the introduction by ion implantation is performed with a time lag.

  Further, the concentration profile of the AA cross section of the PD formation well region shown in the conventional example (FIG. 12B) is indicated by a broken line in the drawing, and this embodiment is used for forming the conventional example and the peripheral circuit. It can be seen that it has a deeper P-type concentration profile than the P-type well. With this diffusion depth, it is possible to further improve the spectral sensitivity, which has a deep penetration length in the long wavelength region, especially the optical carriers entering the PD formation well.

  In addition, the PD formation well and the peripheral circuit formation well have a lower impurity concentration in the deep part of the substrate than on the semiconductor substrate surface side. Then, the impurity concentration of the peripheral circuit formation well is lower than that of the PD formation well, and the depth of the well is reduced. As a result, the charge collection efficiency of the PD can be improved, and the production efficiency of the device can be improved.

  Here, with respect to the location where the impurity concentrations of the two wells are compared, the substrate surface is located far enough from the diffusion region for forming the source / drain region of the MOS transistor, for example, below the gate electrode and the source / drain region. The concentration at the same depth may be compared.

  In the present embodiment, since the heat treatment is performed under the same heat treatment conditions at the time of forming the well, neither the PD region nor the peripheral circuit region has a clear impurity concentration peak. The impurity concentration may be compared in the PD region and the peripheral circuit region.

[Embodiment 2]
4 and 5 are diagrams showing a CMOS sensor well formation method, particularly a PD formation well and a peripheral circuit formation well structure formation method according to the second embodiment.

  4A to 4C are the same as those in the first embodiment.

  In the present embodiment, resist patterning 29a is performed only in a region to be a PD formation well, and a desired P-type impurity 30a is introduced by ion implantation under the same conditions as in the first embodiment.

  Since the P-type impurity 30a is introduced only into the PD region, the dose amount, energy, the number of ion implantations, etc. can be set freely. In addition, the thickness of the resist 29a can be adjusted as a mask material in accordance with the acceleration energy. Furthermore, in this embodiment, ion implantation is performed in a plurality of times as shown in FIGS.

  A shallow semiconductor region 35a may be formed by heat treatment after ion implantation, and then a deeper semiconductor region 35b may be formed by ion implantation to form a PD formation well (FIG. 5A). P-type impurities 30a and 30b may be the same material or different materials. The impurity concentration peak of the deep semiconductor region 35b is preferably higher than the impurity concentration peak of the semiconductor region 35a. This is because the semiconductor region 35b functions as a potential barrier that prevents charges generated in the PD from leaking into the substrate and adjacent pixels. As for the semiconductor region 35a, the impurity concentration at the impurity concentration peak is preferably higher than the impurity concentration peak of the P-type well forming the peripheral circuit. As a result, the transfer voltage (depletion voltage) at the time of signal transfer from the PD to the FD can be controlled to be low.

  The P-type impurity region of the PD formation well has a common area with the P-type impurity region of the peripheral circuit formation well, and only the PD formation well has a P-type impurity region of the peripheral circuit formation well. Also, a deep P-type impurity region may be provided.

  After this, FIG. 5 (a) and subsequent figures are the same manufacturing flow as FIG. 2 (a) and subsequent figures.

  FIG. 6 is a schematic diagram showing the concentration profile of the PD forming well region in this embodiment, particularly the concentration profile of the CC cross section in FIG.

  The concentration profile of the AA cross section of the well region for PD formation shown in the conventional example (FIG. 12B) is indicated by a broken line in the figure.

  The P-type impurity region of the PD formation well is composed of a plurality of impurity regions having an impurity concentration peak, and the concentration of the deepest P-type impurity region is higher than the concentration of the next deepest P-type impurity region.

  As shown in this figure, when there is a deep diffusion layer peak corresponding to the semiconductor region 35b described above in the deep diffusion region, the charges generated in the region shallower than this peak are efficiently surfaced by the potential difference of the P-type diffusion layer. Since it reaches the PD on the side, the sensitivity can be further improved.

  Table 1 is a table comparing the PD sensitivity of the embodiment of the present invention and the conventional example by actual measurement, and shows that the PD sensitivity of the present embodiment is improved by 10% or more compared to the conventional example. Thus, the effectiveness of this embodiment is shown.

また、以上示した実施形態１及び実施形態２を用いた画素構造は、先に示した図９及び図１０へ適用可能なことは言うまでもない。更に、本実施形態の手法は、先に示した埋め込み型ＰＤを用いるプロセス（上記特開２０００−２３２２１４号公報参照）に対し、エピタキシャル成長の際に発生するオートドープ効果や結晶欠陥等のリスクを回避できるだけでなく、イオンインプランテーションと通常の熱処理との自由な組み合わせにより、周辺回路領域と全く独立して、実施形態１中の図２（ｃ）あるいは実施形態２中の図５（ａ）に示した理想的なＰＤ形成用ウエルの設計を可能にした。

Needless to say, the pixel structure using the first and second embodiments described above can be applied to FIGS. 9 and 10 described above. Furthermore, the method of the present embodiment avoids risks such as auto-doping effects and crystal defects that occur during epitaxial growth, compared to the process using the embedded PD described above (see Japanese Patent Laid-Open No. 2000-232214). As shown in FIG. 2 (c) in the first embodiment or FIG. 5 (a) in the second embodiment, not only as a result of the free combination of ion implantation and normal heat treatment, but also completely independent of the peripheral circuit region. This makes it possible to design an ideal PD formation well.

[Embodiment 3]
A difference of the present embodiment from the first and second embodiments is that the well in which the PD is formed is composed of a plurality of impurity regions having an impurity concentration peak, and the peripheral circuit forming well also has an impurity region having an impurity concentration peak. It is the point comprised by these. The formation process can be formed in the same process as the process shown in FIGS. However, the implantation process of the P-type impurity 31 is performed with different acceleration voltages and doses.

  FIG. 7 shows a schematic cross-sectional view of the PD formation region and the peripheral circuit formation region of the present embodiment.

  In FIG. 7, reference numeral 101 denotes an N-type silicon substrate (semiconductor substrate), and P-type semiconductor regions 108, 109, 110 (first to third impurity regions) including regions having an impurity concentration peak in the N-type silicon substrate 101. Are formed on the surface of the substrate, and there are an element isolation region 102, a gate electrode 103 of a transfer MOS transistor, a readout region 104, a PD accumulation region 105 (N-type semiconductor region), a PD surface P region 106, and a P-type semiconductor region 111. Is formed. The light shielding layer 107 has an opening to shield light to areas other than the PD.

  Reference numerals 301 and 302 denote P-type semiconductor regions (fourth and fifth impurity regions) having an impurity concentration peak for forming a peripheral circuit. Reference numerals 303, 304, and 305 denote gate electrode, source, and drain regions of the MOS transistor, respectively. As is apparent from FIG. 7, the PD formation well (first to third impurity regions) is formed deeper than the peripheral circuit formation well. As will be described later, the impurity concentration peak concentration of the third impurity region 110 is set higher than the peak concentrations of the fourth and fifth impurity regions 301 and 302.

  According to such a configuration, it is possible to form a desired well profile in both the PD formation well and the peripheral circuit formation well by the dose amount and the acceleration voltage at the time of impurity ion implantation. In addition, since the peak concentration of the third impurity region 110 formed in the deep portion of the substrate of the PD formation well can be set high, the charge collection efficiency can be improved.

  The impurity concentration profile of the well in which the PD is formed is as shown in FIG.

  The third impurity region 110 formed at the deepest part of the substrate, that is, at the deepest position of the substrate as compared with the light receiving surface has the highest impurity concentration peak concentration, and the next highest is the N type of the conductivity type opposite to the well. This is a first impurity region 108 adjacent to the region. The second impurity region 109 has a lower impurity concentration peak concentration than the first impurity region 108 and the third impurity region 110.

  Next, the impurity concentration relationship of each semiconductor region will be described. The reason why the third impurity region 110 has the highest impurity concentration peak concentration is to prevent a charge generated in the deep part of the substrate from leaking to the substrate side and to serve as a potential barrier for use as a signal. The second impurity region 109 is formed at a lower concentration than the third impurity region 110 in order to collect signal charges generated near the third impurity region 110 on the surface side. Further, the first impurity region 108 formed near the surface has a higher impurity concentration than the second impurity region 109, and serves to suppress the width of the depletion layer at the junction with the PD accumulation region 105. It has. As a result, the depletion voltage of the PD can be lowered, and the PD can be completely reset and transferred without increasing the potential for resetting the readout region 104. In addition, the transfer gate voltage required for PD reset and transfer, that is, the ON voltage applied to the gate electrode 103 of the transfer MOS transistor can be reduced, and a dynamic range can be ensured without causing an increase in power supply voltage. It becomes.

  FIG. 8 is an explanatory diagram of the density profile in the vertical direction of the PD section. The density | concentration profile of the AA and BB cross section of FIG. 7 is shown.

  Reference numeral 206 denotes a density profile corresponding to the surface P region 106 of the PD. 206 can be formed by implantation of boron or boron fluoride. Reference numeral 205 denotes a density profile corresponding to the PDPD accumulation region 105. 205 can be formed by implantation of phosphorus or arsenic. Reference numeral 208 denotes a concentration profile corresponding to the first impurity region 108 close to the accumulation region 205. 209 and 209 ′ are concentration profiles corresponding to the intermediate region 109 (second impurity region). In FIG. 8, the intermediate region 109 is formed with two steps of peaks.

  As described above, this embodiment is also effective when forming by a plurality of stages of ion implantation in accordance with a desired structure. The concentration profiles 209 and 209 ′ of the intermediate region 109 can be formed by two injections of boron or boron fluoride having different acceleration energies. Reference numeral 210 denotes a concentration profile corresponding to the third impurity region 110 located deeper than the first and second impurity regions 108 and 109. Further, the P-type semiconductor region 111 is omitted.

  Reference numerals 211 and 212 denote concentration profiles corresponding to the fourth and fifth impurity regions 301 and 302 in FIG. Reference numeral 204 denotes a concentration profile corresponding to the drain region 305. As is apparent from FIG. 8, the impurity concentration peak concentration of the third impurity region 110 is higher than that of the fourth and fifth impurity regions 301 and 302. More preferably, the impurity concentration peak concentration of the first impurity region 108 is also set higher than that of the fourth and fifth impurity regions 301 and 302. As a result, as described above, the charge collection efficiency can be improved, and the depletion voltage can be kept low.

In order to have the functions as described above, specific values of the peak concentration position and peak concentration of each semiconductor region are shown below. The third impurity region 110 has an impurity concentration peak concentration of 1 × 10 ¹⁶ / cm ³ to 1 × 10 ¹⁸ / cm ³ , and a depth at which the peak is located is 2.0 μm to 4.0 μm from the substrate surface. . The first impurity region 108 has an impurity concentration peak concentration of 2 × 10 ¹⁵ / cm ³ to 2 × 10 ¹⁷ / cm ³ , and a depth at which the peak is located is 0.5 μm to 1.0 μm. The peak concentration of the second impurity region 109 is 1 × 10 ^{15 to} 5 × 10 ¹⁶ / cm ³ , and it is effective to set the peak depth from 0.8 μm to 2.5 μm.

The peak concentration of the fourth and fifth impurity regions 301 and 302 is set to 1 × 10 ¹⁶ / cm ³ to 1 × 10 ¹⁸ / cm ³ , and the peak depth is set to 0.3 to 1.0 μm. Is good.

  According to the configuration of the present embodiment described above, it is possible to form a desired well profile in both the PD formation well and the peripheral circuit formation well by the dose amount and the acceleration voltage at the time of impurity ion implantation. In addition, the charge collection efficiency can be improved by setting the peak concentration of the third impurity region 110 formed in the deep portion of the PD forming well at that time higher than that of the peripheral circuit region. The peak concentration of the second impurity region 109 is preferably set lower than that of the fourth and fifth impurity regions 301 and 302.

(Application to digital cameras)
FIG. 13 is a diagram illustrating an example of a circuit block in the case where the photoelectric conversion devices according to Embodiments 1 to 3 of the present invention are applied to a camera as an imaging system.

  A shutter 1001 is provided in front of the photographing lens 1002 to control exposure. The amount of light is controlled as necessary by the diaphragm 1003 to form an image of the subject on the solid-state imaging device 1004. The solid-state imaging device 1004 uses the photoelectric conversion device of the present invention. A signal output from the solid-state imaging device 1004 is processed by a signal processing circuit 1005 and converted from an analog signal to a digital signal by an A / D converter 1006. The output digital signal is further processed by a signal processing unit 1007. The processed digital signal is stored in the memory unit 1010 or sent to an external device through the external I / F 1013. The solid-state imaging device 1004, the imaging signal processing circuit 1005, the A / D converter 1006, and the signal processing unit 1007 are controlled by a timing generation unit 1008, and the entire system is controlled by an overall control unit / arithmetic unit 1009. In order to record an image on the recording medium 1012, the output digital signal is recorded through a recording medium control I / F unit 1011 controlled by the overall control unit / arithmetic unit.

The figure which shows a part of well formation method of the CMOS sensor in Embodiment 1 of this invention. The figure which shows a part of well formation method of the CMOS sensor in Embodiment 1 of this invention. Schematic diagram of the concentration profile of the well region for PD formation in Embodiment 1 of the present invention The figure which shows a part of well formation method of the CMOS sensor in Embodiment 2 of this invention. The figure which shows a part of well formation method of the CMOS sensor in Embodiment 2 of this invention. Schematic diagram of the concentration profile of the well region for PD formation in Embodiment 2 of the present invention Schematic sectional view of a pixel portion and a peripheral circuit portion of the third embodiment Fig. 7 shows the concentration profile in Fig. 7. Pixel circuit diagram of a solid-state imaging device equipped with a conventional CMOS sensor Schematic cross-sectional view of a pixel of a solid-state imaging device equipped with a conventional CMOS sensor The figure which shows a part of each well formation method of the conventional CMOS sensor using a general CMOS process. The figure which shows a part of each well formation method of the conventional CMOS sensor using a general CMOS process. The figure which showed the example of the circuit block in the case of applying the photoelectric conversion apparatus in Embodiment 3 of this invention to a camera.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... N type silicon substrate 12 ... P type well 17 ... Selective oxide film 27 ... Silicon thermal oxide film 28 ... Silicon nitride film 29, 29a, 29b, 29c ... Photoresist 30a, 30b ... P type impurity 31 ... P type impurity 32 ... N-type impurity 33 ... N-type well 34 ... PD formation well 35a, 35b ... Semiconductor region 108 ... first impurity region 109 ... second impurity region 110 ... third impurity region 301,302 ... fourth, fifth Impurity region

Claims (7)

A photoelectric conversion device in which a pixel including a photoelectric conversion region for converting light into a signal charge and a peripheral circuit including a circuit for processing the signal charge are arranged on the same substrate outside the pixel region where the pixel is formed In
The photoelectric conversion region is formed including a first semiconductor region of the first conductivity type formed on the substrate and a second semiconductor region of the second conductivity type that is the same conductivity type as the signal charge,
The peripheral circuit is formed including a third semiconductor region of the first conductivity type;
The photoelectric conversion device according to claim 1, wherein an impurity concentration of the first semiconductor region is higher than an impurity concentration of the third semiconductor region. A photoelectric conversion device in which a pixel including a photoelectric conversion region for converting light into a signal charge and a peripheral circuit including a circuit for processing the signal charge are arranged on the same substrate outside the pixel region where the pixel is formed In
The photoelectric conversion region is formed including a first semiconductor region of the first conductivity type formed on the substrate and a second semiconductor region of the second conductivity type that is the same conductivity type as the signal charge,
The peripheral circuit is formed including a third semiconductor region of the first conductivity type;
The photoelectric conversion device, wherein each of the first and third semiconductor regions has an impurity concentration peak.   The photoelectric conversion device according to claim 2, wherein an impurity concentration peak concentration of the first semiconductor region is higher than an impurity concentration peak concentration of the third semiconductor region.   4. The photoelectric conversion device according to claim 2, wherein an impurity concentration peak position of the first semiconductor region is disposed deeper than an impurity concentration peak position of the third semiconductor region. 5.   The first semiconductor region has a structure in which a plurality of semiconductor regions having impurity concentration peaks are arranged in the depth direction in the substrate, and the impurity concentration of the impurity concentration peak formed in the deepest part is 5 is higher than the impurity concentration at the impurity concentration peak formed on the photoelectric conversion region side. 5. The photoelectric conversion device according to claim 2, wherein   The first semiconductor region and the third semiconductor region are formed from a plurality of semiconductor regions having an impurity concentration peak, and the impurity concentration peak concentration is the highest among the plurality of regions for forming the first semiconductor region. The peak concentration of the high region is higher than the peak concentration of the region having the highest impurity concentration peak concentration among the plurality of regions for forming the third semiconductor region. The photoelectric conversion apparatus of Claim 1.   A photoelectric conversion device according to claim 1, an optical system that forms an image of light on the photoelectric conversion device, and a signal processing circuit that processes an output signal from the photoelectric conversion device. An imaging system characterized by that.

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