JP5277880B2 - Solid-state imaging device, method for manufacturing solid-state imaging device, and electronic apparatus - Google Patents

Description

  The present invention relates to a solid-state imaging device, a method for manufacturing the solid-state imaging device, and an electronic apparatus including the solid-state imaging device.

  As a solid-state imaging device, a CMOS type solid-state imaging device is known. This CMOS type solid-state imaging device is configured by forming two pixels by a photodiode and a plurality of transistors, so-called MOS transistors, and arranging the plurality of pixels in a required pattern. This photodiode is a photoelectric conversion element that generates and accumulates signal charges according to the amount of received light, and the plurality of MOS transistors are elements for transferring signal charges from the photodiodes.

  FIG. 7 shows a schematic cross-sectional configuration of a main part of a conventional CMOS solid-state imaging device (described in Patent Document 1 below) applied to an image sensor. FIG. 7 is a cross-sectional configuration of the pixel portion of the solid-state imaging device 216.

  A conventional solid-state imaging device 216 shown in FIG. 7 has a pixel isolation region 208 on the surface side of a p-type substrate 201 made of silicon, and a pixel 200 made up of a photodiode PD and a plurality of MOS transistors in each divided region. Have. The plurality of MOS transistors are a charge read transistor Tr1, a reset transistor Tr2, an amplifier transistor Tr3, and a vertical selection transistor (not shown), respectively. A pixel region composed of these four MOS transistors and the photodiode PD is a unit pixel. A plurality of unit pixels are arranged in a two-dimensional matrix.

  The photodiode PD includes an n + -type impurity region 203 formed in order from a surface of the p-type substrate 201 in a required depth direction, an n-type impurity region 202, and a high impurity formed on the surface of the n + -type impurity region 203. The p-type impurity region 204 has a concentration.

The charge readout transistor Tr1 includes a planar gate electrode 209 formed on a substrate adjacent to a region where the photodiode PD is formed via a gate insulating film 217, and an n + impurity region formed on the substrate surface. Source / drain region 205. This source / drain region 205 constitutes a floating diffusion region.
The amplifier transistor Tr3 is formed on the substrate surface with the source / drain region 206, the planar gate electrode 211 formed on the substrate adjacent to the region where the source / drain region 206 is formed via the gate insulating film 217, and the like. Source / drain region 207 including n + impurity regions.
The reset transistor Tr2 includes a source / drain region 205, a planar gate electrode 210 formed on the substrate 201 adjacent to the region where the source / drain region 205 is formed via a gate insulating film 217, and the surface of the substrate 201. And a source / drain region 206 composed of n + impurity regions.
The source / drain region 206 is connected to a power supply wiring 213 formed on the substrate 201 via an interlayer insulating film 215 via a contact portion 212.
A desired wiring 214 is formed in the interlayer insulating film 215.

  As described above, the photodiode PD and the plurality of MOS transistors are arranged for each unit pixel 200 on the surface of the substrate 201 of the conventional solid-state imaging device 216.

  Incidentally, in recent years, in a solid-state imaging device, the pixel size has been miniaturized in order to highly integrate a large number of pixels. In particular, in each pixel region of the conventional solid-state imaging device 216 as shown in FIG. 7, the photodiode PD and a plurality of MOS transistors are arranged on the same plane of the substrate 201, so that the unit pixel 200 is configured. On the surface of the substrate 201, an area constituting them is required. For this reason, the area of one pixel tends to increase. In such a configuration, when the pixel size is miniaturized, the area of the photodiode PD is reduced, and there is a problem that the saturation charge amount (Qs) is lowered and the sensitivity is lowered. .

  In order to solve this problem, several methods for reducing the pixel size by sharing a MOS transistor in a pixel with a plurality of adjacent pixels have been proposed.

  Further, as a completely different approach to a method for preventing a decrease in saturation charge amount (Qs) and a decrease in sensitivity due to a reduction in pixel size, Patent Document 3 proposes a solid-state imaging device using an embedded gate electrode. ing.

JP-A-11-122532 JP 2002-513145 A Japanese Patent Laying-Open No. 2005-223084

  As described above, in the solid-state imaging device, various proposals have been made in order to prevent a decrease in saturation charge amount and a decrease in sensitivity due to a reduction in pixel size. However, it has become difficult to obtain a sufficient amount of saturation charge as the pixel size has been rapidly reduced in recent years.

  In addition, when an embedded gate electrode as in Patent Document 3 is used, a silicon semiconductor substrate is selectively etched in order to form the embedded gate electrode. For this reason, it is necessary to suppress dark current generated from defects caused by damage caused by selective etching.

In view of the above-described points, the present invention provides a solid-state imaging device that increases the saturation charge amount (Qs) and suppresses dark current, and a manufacturing method thereof.
Moreover, this invention provides the electronic device provided with the said solid-state imaging device.

In order to solve the above problems and achieve the object of the present invention, the solid-state imaging device of the present invention has a substrate, a photodiode, a readout gate electrode, a dark current suppression region, and a readout channel region.
A plurality of photodiodes are stacked in the depth direction of the substrate. The readout gate electrode is a vertical readout gate electrode, and is formed so as to be embedded in the depth direction of the substrate in order to read out signal charges of a plurality of photodiodes stacked in the depth direction of the substrate.
The dark current suppression region is formed by covering the bottom and side surfaces of the readout gate electrode with the first conductivity type semiconductor region, and is formed with a uniform width on the side surface of the readout gate.
The read channel region is formed of a second conductivity type semiconductor region in a region between the dark current suppression region formed on the side surface of the read gate electrode and the photodiode.

  In the solid-state imaging device of the present invention, signal charges are accumulated by a plurality of photodiodes stacked in the depth direction of the substrate. As a result, the saturation charge amount increases. Further, since the signal charge is read out by the vertical read gate electrode, it is possible to prevent the transfer of the signal charge from remaining. Further, since the dark current suppression region formed on the side surface of the read gate electrode is formed with a uniform width, variation in read characteristics is reduced.

  In addition, the method for manufacturing a solid-state imaging device of the present invention includes a step of forming a plurality of photodiodes stacked in the depth direction of the substrate, and a step of forming a mask layer and a photoresist film on the substrate. Next, there is a step of patterning a photoresist film by a photolithography method, etching the mask layer using the patterned photoresist film as a mask, and forming an opening reaching the substrate surface. Next, a step of ion-implanting the first conductivity type impurity into the substrate through the opening, and a region on the substrate surface side of the region of the substrate from which the first conductivity type impurity is ion-implanted through the opening A step of ion-implanting impurities of the second conductivity type. Next, the step of removing the resist film, the step of forming the first sidewall spacer on the surface of the mask layer including the opening, the step of reducing the diameter of the opening, the first conductivity type through the reduced opening A step of ion-implanting impurities. Next, a step of forming a second sidewall spacer on the side wall of the reduced opening and further reducing the diameter of the opening, etching the substrate using the reduced opening as a mask, and a groove adjacent to the photodiode Forming a step. Next, a step of forming a gate insulating film by covering the bottom and side surfaces of the groove, and a step of forming a read gate electrode by embedding an electrode material in the groove where the gate insulating film is formed.

  In the method for manufacturing a solid-state imaging device according to the present invention, a region in which a desired impurity is ion-implanted or a groove is formed while the diameter of the opening is reduced stepwise. The groove is formed by self-alignment. Accordingly, it is not necessary to perform mask alignment for ion implantation into a predetermined region or to form a groove portion, and the readout gate electrode and its peripheral semiconductor region can be formed with high accuracy.

The electronic apparatus of the present invention includes an optical lens, a solid-state imaging device, and a signal processing circuit. The solid-state imaging device includes a substrate, a photodiode, a readout gate electrode, a dark current suppression region, and a readout channel region.
A plurality of photodiodes are stacked in the depth direction of the substrate. The readout gate electrode is a vertical readout gate electrode, and is formed so as to be embedded in the depth direction of the substrate in order to read out signal charges of a plurality of photodiodes stacked in the depth direction of the substrate.
The dark current suppression region is formed by covering the bottom and side surfaces of the readout gate electrode with the first conductivity type semiconductor region, and is formed with a uniform width on the side surface of the readout gate.
The read channel region is formed of a second conductivity type semiconductor region in a region between the dark current suppression region formed on the side surface of the read gate electrode and the photodiode.

  In the electronic apparatus of the present invention, light incident from the optical lens is converted into signal charges in the solid-state imaging device, and is output as a video signal via the signal processing circuit. In the solid-state imaging device, signal charges are accumulated by a plurality of photodiodes stacked in the depth direction of the substrate. As a result, the saturation charge amount increases. Further, since the signal charge is read out by the vertical read gate electrode, it is possible to prevent the transfer of the signal charge from remaining. Further, since the dark current suppression region formed on the side surface of the read gate electrode is formed with a uniform width, variation in read characteristics is reduced.

According to the solid-state imaging device according to the present invention, it is possible to provide a solid-state imaging device in which the saturation charge amount (Qs) of a unit pixel is increased and generation of white current is suppressed by suppressing generation of dark current.
According to the method for manufacturing a solid-state imaging device of the present invention, a solid-state imaging device in which a dark current suppression region and a readout channel region are accurately formed and generation of white current is suppressed by suppressing generation of dark current is manufactured. be able to.
According to the electronic device according to the present invention, by providing the solid-state imaging device of the present invention, it is possible to provide an electronic device with improved sensitivity and high image quality.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS.

<First Embodiment>
[Overall structure of solid-state imaging device]
First, the entire structure of a CMOS solid-state imaging device, that is, a CMOS image sensor according to the first embodiment of the present invention will be described with reference to FIG.

  A solid-state imaging device 1 shown in FIG. 1 includes an imaging region 3 composed of a plurality of pixels 2 arranged on a substrate 11 made of Si, a vertical drive circuit 4 as a peripheral circuit of the imaging region 3, and column signal processing. The circuit 5 includes a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

  The pixel 2 is composed of a photodiode which is a photoelectric conversion element and a plurality of MOS transistors, and is formed by regularly arranging a plurality of pixels in a two-dimensional array on the substrate 11.

  The imaging region 3 is composed of pixels 2 regularly arranged in a two-dimensional array. The imaging area 3 is an optical area that is actually received light and can store signal charges generated by photoelectric conversion, and an optical area that is formed around the effective pixel area and serves as a reference for the black level. And a black reference pixel region for outputting black.

  The control circuit 8 generates a clock signal, a control signal, and the like that serve as a reference for operations of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock To do. The clock signal and control signal generated by the control circuit 8 are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.

  The vertical drive circuit 4 is configured by a shift register, for example, and selectively scans each pixel 2 in the imaging region 3 in the vertical direction sequentially in units of rows. Then, the pixel signal based on the signal charge generated according to the amount of light received in the photodiode of each pixel 2 is supplied to the column signal processing circuit 5 through the vertical signal line.

  The column signal processing circuit 5 is arranged, for example, for each column of the pixels 2, and a signal output from the pixels 2 for one row is sent to the black reference pixel region (not shown, but around the effective pixel region) for each pixel column. Signal processing such as noise removal and signal amplification. A horizontal selection switch (not shown) is provided between the output stage of the column signal processing circuit 5 and the horizontal signal line 10.

  The horizontal drive circuit 6 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, and the pixel signal is output from each of the column signal processing circuits 5 to the horizontal signal line. 10 to output.

The output circuit 7 performs signal processing and outputs the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10.
The solid-state imaging device in the first to fifth embodiments described below constitutes the solid-state imaging device 1 in FIG. 1, and particularly shows a cross-sectional configuration of the pixel 2 in the effective imaging region.

  FIG. 2 shows a schematic cross-sectional configuration of the imaging region 3 of the solid-state imaging device 1 according to the present embodiment.

The solid-state imaging device 1 of the present embodiment example drives a substrate 20, a photodiode PD formed on the substrate 20, a plurality of pixel transistors for reading signal charges obtained from the photodiode PD, and the pixel transistors. And a wiring layer 47 for the purpose.
In the following description, a p-type semiconductor region is used as the first conductivity type semiconductor region of the present invention, and an n-type semiconductor region is used as the second conductivity type. Also, n-type and n + type are written in ascending order of n-type impurity concentration, and p-type and p + -type are written in ascending order of p-type impurity concentration. In the present embodiment example, a surface irradiation type solid-state imaging device that is irradiated with light L from the surface side of the substrate 20 will be described.

  The substrate 20 is made of silicon made of a p-type semiconductor.

A plurality of photodiodes PD are formed in a matrix in the vertical and horizontal directions in the substrate 20 corresponding to the pixels 2 shown in FIG. The photodiode PD constitutes a light receiving portion that receives light in the pixel 2. The photodiode PD includes a plurality of photodiodes formed in the depth direction having pn junctions j ₁ and j ₂ that are junctions between a p-type semiconductor region and an n-type semiconductor region. In the embodiment, the first photodiode PD1 and the second photodiode PD2 are included. Specifically, a p + type semiconductor region 21, an n + type semiconductor region 22, a p + type semiconductor region 23, an n + type semiconductor region 24, and an n type semiconductor region 25 are formed in order from the surface of the substrate 20. first photodiode PD1 is formed by a semiconductor region 21 and the n + -type semiconductor region 22 and the pn junction _{j 1.} Further, the pn junction j ₂ with its first p + -type semiconductor region 23 is formed continuously below the photodiode PD1 and the n + -type semiconductor region 24 and the second photodiode PD2 is formed.

  In the photodiode PD having such a configuration, the light L incident on the photodiode PD which is a light receiving unit is photoelectrically converted here, and the signal charge obtained by the photoelectric conversion is formed by the pn junction j1. Accumulated in each potential well.

  The pixel transistor includes a charge readout transistor Tr1, a reset transistor Tr2, and an amplifier transistor Tr3.

  First, the charge readout transistor Tr1 includes a readout gate electrode 26 formed adjacent to the photodiode PD formed for each pixel 2 and a floating diffusion region FD.

  The read gate electrode 26 is a columnar vertical gate electrode formed by embedding an electrode material through a gate insulating film 27 in a groove 50 formed in the depth direction from the surface of the substrate 20. In addition, a planar electrode portion 26a for drawing out a wiring is formed on the upper portion of the read gate electrode 26 constituted by the vertical gate electrode. The bottom of the read gate electrode 26 is formed vertically in the substrate 20 so as to reach a position deeper than the depth of the pn junction j2 constituting the second photodiode PD2.

The bottom and side surfaces of the read gate electrode 26 including the gate insulating film 27 are covered with dark current suppression regions 30 and 29 made of p-type semiconductor regions. In particular, the dark current suppression region 29 formed on the side surface of the read gate electrode 26 is formed to have a uniform width around the side surface of the read gate electrode 26. A read channel region 28 made of an n-type semiconductor region is formed around the dark current suppression region 29 formed on the side surface of the read gate electrode 26. In this embodiment, the read channel region 28 is formed so as to cover the entire periphery of the dark current suppression region 29 formed on the side surface of the read gate electrode 26. One side surface of the read channel region 28 is formed so as to be in contact with the pn junctions j ₁ and j ₂ constituting the first photodiode PD1 and the second photodiode PD2. Further, the other side surface of the read channel region 28 is formed in contact with the floating diffusion region FD formed on the surface of the substrate 20.

  The floating diffusion region FD has a high concentration impurity concentration on the surface side of the substrate 20 at a position in contact with the read channel region 28 formed on the side surface of the vertical read gate electrode 26 opposite to the side in contact with the photodiode PD. N + type semiconductor region. This floating diffusion region FD is a region from which signal charges accumulated in the photodiode PD are read out.

  In the charge readout transistor Tr1, when a positive voltage is applied to the readout gate electrode 26, the potential of the readout channel region 28 changes, and the photodiode PD and the floating diffusion region FD are electrically connected.

  FIG. 3 shows a planar layout configuration of the pixel 2 of the solid-state imaging device 1 of the present embodiment. As shown in FIG. 3, in the solid-state imaging device 1 of the present embodiment, one charge readout transistor Tr1 is formed for each photodiode PD constituting one pixel. The floating diffusion region FD is shared between the four adjacent pixels 2.

  The reset transistor Tr2 includes a floating diffusion region FD, a source / drain region 32, and a reset gate electrode 31.

The configuration of the floating diffusion region FD is as described above.
The source / drain region 32 is formed of an n + type semiconductor region on the surface of the substrate 20 so as to be separated from the floating diffusion region FD. The source / drain region 32 is connected to a power supply wiring 36 for supplying a power supply voltage.
The reset gate electrode 31 is formed on the upper surface of the substrate 20 between the floating diffusion region FD and the source / drain region 32 via a gate insulating film 27. One end of the reset gate electrode 31 is adjacent to the floating diffusion region FD, and the other end is adjacent to the source / drain region 32.

  In the reset transistor Tr <b> 2, when a positive voltage is applied to the reset gate electrode 31, a channel region is formed in the substrate 20 region below the reset gate electrode 31. By this channel region, the floating diffusion region FD and the source / drain region 32 are electrically connected.

The amplifier transistor Tr3 is composed of source / drain regions 32 and 34 and an amplifier gate electrode 33.
The structure of the source / drain region 32 is as described above.
The source / drain region 34 is formed of an n + type semiconductor region on the surface of the substrate 20 so as to be separated from the source / drain region 32 described above.
The amplifier gate electrode 33 is formed on the upper surface of the substrate 20 between the source / drain region 32 and the source / drain region 34 via the gate insulating film 27. One end of the amplifier gate electrode 33 is adjacent to the source / drain region 32, and the other end is adjacent to the source / drain region 34.

  In the amplifier transistor Tr3, a voltage is applied to the amplifier gate electrode 33 in response to a voltage change in the floating diffusion region FD due to signal charges being read out to the floating diffusion region FD. By applying a voltage to the amplifier gate electrode 33, a channel region is formed in the substrate 20 region below the amplifier gate electrode 33, and the source / drain regions 32 and 34 are electrically connected by this channel region. The

  In addition, although not shown, a selection transistor or the like is formed as necessary.

  As described above, each pixel 2 is configured by the photodiode PD and desired pixel transistors such as the charge readout transistor Tr1, the reset transistor Tr2, and the amplifier transistor Tr3. The pixel 2 formed on the substrate 20 includes the pixel separation region 35. Is separated from the adjacent pixel 2. A wiring layer 47 in which a multilayer wiring 38 including a power supply wiring 36 is formed via an interlayer insulating film 37 is formed on the substrate 20 on which the photodiode PD and a desired pixel transistor are formed.

  In the solid-state imaging device 1 described above, the light L is irradiated from the surface side of the substrate 20 and the light PD is received by the photodiode PD. For this reason, although not shown, on-chip color filters and on-chip lenses are formed at positions corresponding to the respective pixels 2 on the wiring layer 47 on the substrate 20.

<Method for manufacturing solid-state imaging device>
Next, a method for manufacturing the solid-state imaging device 1 according to the present embodiment will be described with reference to FIGS. Here, a case where the pixel size is, for example, 0.9 μm will be described, and the description will be made with particular attention to the manufacturing process of the read gate electrode 26 portion. Except for the portion of the readout gate electrode 26, a conventional method for manufacturing a solid-state imaging device can be applied. In addition, the manufacturing process of the readout gate electrode 26 is usually performed after the manufacturing process of the photodiode PD. In this embodiment, before the p + type semiconductor region 21 on the surface of the substrate 20 constituting the photodiode PD is formed. It is done in stages. Further, in the manufacturing process of the present embodiment example, the pn junction j ₁ of the _first photodiode PD is formed to a depth of about 0.1 μm from the surface of the substrate 20, and the pn junction j _{2 of the second} photodiode PD2 is formed. Is assumed to be formed to a depth of about 0.5 μm from the surface of the substrate 20.

First, as shown in FIG. 4A, a silicon oxide film (SiO ₂ ) to be a gate insulating film 27 is formed on the substrate 20 to a thickness of 5 nm.
Next, a silicon nitride film (SiN) 41 is formed on the gate insulating film 27 to a thickness of 100 nm, and a silicon oxide film (SiO ₂ ) 42 is formed on the silicon nitride film 41 to a thickness of 1 μm. The silicon nitride film 41 and the silicon oxide film 42 constitute a mask layer 40 used for ion implantation into the substrate 20.

  Subsequently, a photoresist film 43 is formed on the silicon oxide film 42 to a thickness of 0.6 μm. The photoresist film 43 is exposed and developed by lithography to form a pattern of the photoresist film 43. In this embodiment, a circular opening 44a having a diameter of 0.3 μm is formed in the photoresist film 43 in a pattern. The diameter of the opening 44a varies depending on the pixel size, and the numerical values used in this embodiment are an example.

  Next, using the photoresist film 43 in which the opening 44a is formed as a mask, the mask layer 40 and the gate insulating film 27 are etched until the surface of the substrate 20 is exposed, thereby forming the opening 44b.

Next, as shown in FIG. 4B, the depth from the surface of the substrate 20 is 0.6 to 0.8 μm or more through the opening 44b in the gate insulating film 27, the mask layer 40, and the photoresist film 43, and 1 to Boron, which is an impurity of the p-type semiconductor region, is ion-implanted into a region of 1.5 μm or less. That is, at a position deeper than the pn junction j _2, boron ions are implanted. Thereby, the dark current suppressing region 30 covering the bottom of the read gate electrode 26 is formed.
Subsequently, phosphorus, which is an impurity of the n-type semiconductor region, is ion-implanted into a region having a depth from the surface of the substrate 20 of 0.6 to 0.8 μm or less through the opening 44b. That is, the surface of the substrate 20, formed in a region obtained by multiplying a position deeper than the pn junction j _2. This n-type semiconductor region becomes the read channel region 28.

  The ion implantation depth of these boron and phosphorus impurities needs to be sufficiently shallower than the total film thickness of the photoresist film 43 and the mask layer 40 composed of the silicon oxide film 42 and the silicon nitride film 41. Further, it is desirable to design the impurity concentration of phosphorus so as to increase from a deep region of the substrate 20 toward the surface.

  Next, the photoresist film 43 is removed. Then, as shown in FIG. 4C, a silicon oxide film is formed with a thickness of 50 nm on the surface of the mask layer 40, and a first sidewall spacer 45 is formed. The first sidewall spacer 45 reduces the diameter of the opening 44b formed in the mask layer 40, and the diameter of the opening 44c reduced by the first sidewall spacer 45 is 0.2 μm. .

  Subsequently, boron, which is an impurity of the p-type semiconductor region, is ionized into a region having a depth of 0.8 to 1 μm or less from the surface of the substrate 20 through the opening 44c reduced by the first sidewall spacer 45. inject. At this time, the impurity concentration of boron is made as uniform as possible in the depth direction from the surface of the substrate 20. This p-type semiconductor region becomes the dark current suppression region 29 formed on the side surface of the read gate electrode 26.

  Next, as shown in FIG. 4D, a silicon oxide film is further formed with a thickness of 50 nm on the side wall of the opening 44c reduced by the first side wall spacer 45, and the second side wall spacer 46 is formed. . The second side wall spacer 46 further reduces the diameter of the opening 44c reduced by the first side wall spacer 45, and the diameter of the opening 44d reduced by the second side wall spacer 46 is 0. .1 μm.

  Then, as shown in FIG. 5E, the silicon oxide film constituting the first sidewall spacer 45 formed on the bottom of the opening 44d is dried via the opening 44d reduced by the second sidewall spacer 46. Etching is performed to expose the surface of the substrate 20.

  Thereafter, as shown in FIG. 5F, the substrate 20 is etched to a depth of about 1 μm by using the mask layer 40 having the opening 44d reduced by the first sidewall spacer 45 and the second sidewall spacer 46 as a mask. Include. Thereby, a groove 50 for forming the read gate electrode 26 is formed.

  Next, as shown in FIG. 5G, as a pretreatment for thermal oxidation for removing damage, a silicon oxide film constituting the mask layer 40, the first sidewall spacer 45, and the second sidewall spacer 46 is formed with hydrofluoric acid. Remove.

  Then, as shown in FIG. 5H, a gate insulating film 27 made of a silicon oxide film is formed on the surface of the trench 50. The gate insulating film 27 formed here corresponds to the read gate electrode 26.

  Then, as shown in FIG. 5I, a phosphorus-doped gate electrode material is embedded in the trench 50 and the opening 44b formed in the silicon nitride film 41 via the gate insulating film 27. Then, the gate electrode material on the silicon nitride film 41 is removed by CMP (Chemical Mechanical Polishing).

Thereafter, as shown in FIG. 5J, the silicon nitride film 41 is removed with hot phosphoric acid to obtain a read gate electrode 26 having a desired shape. The readout gate electrode 26 of the present embodiment formed in this manner has a vertical gate electrode formed in the groove 50 and a planar electrode portion 26a formed in the opening 4b of the silicon nitride film 41. Configured. In the planar electrode portion 26a, wiring is drawn out.
Although not shown, desired gate electrodes such as the reset gate electrode 31 and the amplifier gate electrode 33 are formed when the read gate electrode 26 is formed.

  As described above, the read gate electrode 26 is completed. Thereafter, for example, there is a step of forming the p + type semiconductor region 21 on the outermost surface side of the substrate 20 constituting the photodiode PD.

  In the method for manufacturing the solid-state imaging device 1 according to the present embodiment, the exposure mask is used only in the exposure / development process for forming the pattern of the photoresist film 43 in the manufacturing process of the readout gate electrode 26. Then, the opening 44b of the mask layer 40 etched using the photoresist film 43 is reduced by the first sidewall spacer 45 or the second sidewall spacer 46, and the reduced openings 44c and 44d are passed through the reduced openings 44c and 44d. The dark current suppression region 29, the read channel region 28, the groove 50, and the like can be formed. That is, in this embodiment, only one exposure mask is used when the read gate electrode 26 is formed, and the dark current suppression region 29, the read channel region 28, the groove 50, and the like are formed by self-alignment. Therefore, there is no influence of mask misalignment.

  The dark current suppression region 29 is for preventing unnecessary charges from entering the photodiode PD and causing dark current when the charge is accumulated in the photodiode PD. Therefore, the dark current suppression region 29 is preferably formed on the side surface of the read gate electrode 26 with a more uniform width and a uniform concentration. More specifically, if the dark current suppression region 29 is too thick, the gate bias cannot be controlled and a so-called transfer residue occurs. Conversely, if the dark current suppression area 29 is too thin, it may cause dark current. Usually, it is desirable that these controls be performed at ± 20 to 30 nm. For this reason, determining the width of the dark current suppression region 29 by ion implantation through a conventional thick film resist that is difficult to achieve alignment accuracy may cause a serious problem in terms of characteristic variation. Also, the read channel region 28 needs to be a uniform layer in order to prevent untransferred signal charges.

  In this embodiment, since the dark current suppression region 29 is formed by self-alignment and is not affected by mask misalignment and can have a uniform width, transfer is performed while suppressing the generation of dark current. It is set as the structure which a remainder does not arise.

  In this embodiment, the read channel region 28 is also formed by self-alignment, so that it is not affected by misalignment of the mask and can have a uniform width. Can do.

  In this embodiment, the dark current suppression region 30 formed at the bottom of the read gate electrode 26 is formed with the photoresist film 43 formed. As a result, the impurities for forming the dark current suppression region 30 can be ion-implanted with high precision into a deep region of the substrate 20 and a region covering the bottom of the read gate electrode 26.

  In this embodiment, the mask layer 40 has a two-layer structure of a silicon nitride film 41 and a silicon oxide film 42 having a selectivity to hydrofluoric acid, and only the silicon oxide film 42 is removed in the step shown in FIG. 5G. Thereby, the groove portion 50 and the opening portion 44a having a larger diameter than the groove portion 50 are obtained by self-alignment, and the read gate electrode 26 is formed by embedding the groove portion 50 and the opening portion 44a with the electrode material. Thereby, the planar electrode portion 26a for drawing out the wiring is accurately formed on the upper portion of the vertical gate electrode formed on the pillar.

  In this embodiment, since the read gate electrode 26, the dark current suppression region 29, and the read channel region 28 are formed by self-alignment, characteristic variation due to misalignment is prevented, and it is not necessary to create an unnecessary alignment margin. Therefore, even when the pixel size is reduced, the readout gate electrode 26 can be formed with high accuracy.

<Driving method of solid-state imaging device>
Next, the driving method of the solid-state imaging device 1 formed as described above will be described.

  First, the light L is irradiated from the surface side of the solid-state imaging device 1 shown in FIG. Then, the light L collected by the on-chip lens enters the photodiode PD through a color filter (not shown).

The light incident on the photodiode PD is photoelectrically converted in the first photodiode PD1 and the second photodiode PD2, and a signal charge is generated there. The generated signal charge is accumulated in a potential well formed by the pn junction j ₁ constituting the first photodiode PD1 or the pn junction j ₂ constituting the second photodiode PD2.

  Further, in the solid-state imaging device 1 of the present embodiment example, the bottom and side surfaces of the readout gate electrode 26 are configured to contact the dark current suppression regions 29 and 30 through the gate insulating film 27 to accumulate signal charges. Sometimes, a negative voltage is applied to the read gate electrode 26. By doing so, holes are pinned to the bottom and side surfaces of the read gate electrode 26 via the gate insulating film 27. In this way, hole pinning, in which holes are pinned, allows dark current noise entering from the read gate electrode 26 to be confined in the dark current suppression regions 29 and 30 during signal charge accumulation. As a result, dark current reaching the first photodiode PD1 and the second photodiode PD2 can be reduced.

  In the present embodiment, for example, when the signal charge is accumulated, the signal charge overflowing beyond the saturation charge amount (Qs) of the first photodiode PD1, for example, passes through the read channel region and is adjacent to the second charge. Move to photodiode PD2. On the contrary, the signal charge overflowed by the second photodiode PD2 moves to the first photodiode PD1. That is, in the present embodiment, the signal charge that exceeds the saturation charge amount of one photodiode overflows to the other photodiode. As a result, the saturation charge amount (Qs) of the entire photodiode PD can be increased.

  After the signal charge is accumulated, a positive voltage is applied to the read gate electrode 26. As a result, the potential of the read channel region 28 becomes deeper. As a result, the signal charges accumulated in the first photodiode PD1 and the second photodiode PD2 are transferred through the read channel region 28 and simultaneously read out to the floating diffusion region FD.

  The subsequent driving method is the same as that of a normal solid-state imaging device. That is, the signal charge is transferred to the floating diffusion region FD, and a voltage is applied to the amplifier gate electrode 33 of the amplifier transistor Tr3 due to a voltage change in the floating diffusion region FD. Thereby, the signal output by the signal charge is amplified and output.

  Further, when a positive voltage is applied to the reset gate electrode 31, the floating diffusion region FD and the source / drain region 32 are connected, so that the floating diffusion region FD is applied to the source / drain region 32. Reset to the same voltage as the power supply voltage.

  In the solid-state imaging device 1 according to the present embodiment, a photodiode PD including first and second photodiodes PD1 and PD2 is formed in the depth direction of the substrate 20. With such a configuration, the saturation charge amount (Qs) of the entire photodiode PD increases. For this reason, it becomes possible to improve the sensitivity of a solid-state imaging device.

  In the solid-state imaging device 1 according to the present embodiment, the charge readout transistor Tr1 having the vertical readout gate electrode 26 embedded in the depth direction of the photodiode PD is configured. This makes it possible to completely transfer the signal charges accumulated in the first and second photodiodes PD1 and PD2 formed in the depth direction of the substrate 20 to the floating diffusion region FD.

  In the solid-state imaging device according to the present embodiment, the example is configured by two photodiodes including the first photodiode PD1 and the second photodiode PD2, but a desired number of two or more photodiodes are provided. A plurality of layers can be stacked. Even when the pixel size is reduced, the saturation charge amount (Qs) can be increased and the sensitivity can be improved by stacking a plurality of photodiodes. For this reason, it is easy to reduce the pixel size while increasing the saturation charge amount and improving the sensitivity, and the structure of this embodiment is advantageous for reducing the pixel size. Further, the saturation charge amount can be increased and the dynamic range can be increased, so that the contrast can be improved.

  In the solid-state imaging device 1 of the present embodiment, the first conductivity type is p-type and the second conductivity type is n-type, but the first conductivity type may be n-type and the second conductivity type may be p-type. Good. In that case, in the driving method described above, the voltage applied to each pixel transistor is read as positive negative and negative negative.

  In the solid-state imaging device 1 according to the present embodiment, the front-illumination type solid-state imaging device has been described. When the solid-state imaging device 1 of the present embodiment is configured as a backside illumination type in which light is incident from the backside of the substrate, interlayer insulation is provided above the surface side of the semiconductor substrate on which the imaging region 3 and the peripheral circuit portion are formed. A multilayer wiring layer is formed through the film, and the back surface side becomes a light incident surface (so-called light receiving surface). An on-chip color filter is formed on the pixel 2 in the imaging region 3 on the back side through a planarizing film, and an on-chip microlens is further formed thereon.

  In the solid-state imaging device 1 of the present embodiment, the read channel region 28 is formed by ion implantation of n-type impurities, but the concentration is about two orders of magnitude lower than the dark current suppression region 29. If so, it can be formed of a non-doped region.

<Second Embodiment>
[Electronics]
Hereinafter, an embodiment in which the above-described solid-state imaging device of the present invention is used in an electronic apparatus will be described. In the following description, an example in which the solid-state imaging device 1 according to the first embodiment is used as a camera will be described as an example.

FIG. 6 shows a schematic cross-sectional configuration of a camera according to the second embodiment of the present invention. The camera according to the present embodiment is an example of a video camera that can shoot a still image or a moving image.
The camera according to this embodiment includes a solid-state imaging device 1, an optical lens 110, a shutter device 111, a drive circuit 112, and a signal processing circuit 113.

The optical lens 110 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 1. As a result, the signal charge is accumulated in the solid-state imaging device 1 for a certain period. The optical lens 110 may be an optical lens system including a plurality of optical lenses.
The shutter device 111 controls a light irradiation period and a light shielding period for the solid-state imaging device 1.
The drive circuit 112 supplies a drive signal that controls the transfer operation of the solid-state imaging device 1 and the shutter operation of the shutter device 111. Signal transfer of the solid-state imaging device 1 is performed by a drive signal (timing signal) supplied from the drive circuit 112. The signal processing circuit 113 performs various signal processing. The video signal subjected to the signal processing is stored in a storage medium such as a memory or output to a monitor.

  In the solid-state imaging device 1 used in the camera according to the present embodiment, a plurality of color signals can be detected from one pixel using a photodiode stacked in a substrate, and the effective number of pixels can be improved and the saturation charge can be increased. The quantity (Qs) and sensitivity are improved. For this reason, in the camera of the present embodiment, the camera can be reduced in size, and a camera with higher image quality can be obtained. That is, it is possible to reduce the size, increase the resolution, and improve the image quality of the electronic device.

1 is an overall configuration diagram of a solid-state imaging device according to a first embodiment of the present invention. 1 is a schematic cross-sectional configuration diagram of a main part of a solid-state imaging device according to a first embodiment of the present invention. 1 is a plan layout diagram of a solid-state imaging device according to a first embodiment of the present invention. 1A to 1D are manufacturing process diagrams (part 1) of the solid-state imaging device according to the first embodiment of the present invention. E to J are manufacturing process diagrams (part 2) of the solid-state imaging device according to the first embodiment of the present invention. It is a schematic block diagram of the electronic device which concerns on the 2nd Embodiment of this invention. It is a schematic sectional block diagram of the solid-state imaging device of a prior art example.

Explanation of symbols

  1 .. Solid-state imaging device, 2... Pixel, 2 a... First pixel, 2 b... Second pixel, 3 .. imaging region, 4 .. vertical drive circuit, 5. ..Horizontal drive circuit 7 ..Output circuit 8 ..Control circuit 9 ..Vertical signal line 10 ..Horizontal signal line 11 ..Substrate 20 ..Substrate 21 ..p + type semiconductor region 22... N + type semiconductor region, 23... P + type semiconductor region, 24... N + type semiconductor region, 25... N type semiconductor region, 26... Read gate electrode, 27. Channel region, 29, 30 ... Dark current suppression region, 31 ... Reset electrode, 32, 34 ... Source / drain region, 33 ... Amplifier gate electrode, 35 ... Pixel isolation region

Claims (7)

A substrate,
A plurality of photodiodes stacked in the depth direction of the substrate;
A vertical readout gate electrode formed to be embedded in the depth direction of the substrate in order to read out the signal charge of the photodiode;
A dark current suppression region formed of a first conductivity type semiconductor region formed to cover the bottom and side surfaces of the read gate electrode, and having a uniform width on the side surface of the read gate electrode, and the first conductivity type semiconductor region And a readout channel region formed of a second conductivity type semiconductor region between the photodiode and the photodiode,
A solid-state imaging device configured to include:   The solid-state imaging device according to claim 1, wherein the read channel region is formed so as to cover a periphery of the dark current suppression region formed so as to cover a side surface of the read gate electrode.   3. The solid-state imaging device according to claim 2, wherein the readout channel region is formed from the substrate surface to a position deeper than a depth of a pn junction of a photodiode at a deepest position among the plurality of photodiodes. . Forming a plurality of photodiodes stacked in the depth direction of the substrate;
Forming a mask layer and a photoresist film on the substrate;
Patterning a photoresist film by photolithography, etching the mask layer using the patterned photoresist film as a mask, and forming an opening reaching the substrate surface;
A step of ion-implanting a first conductivity type impurity into the substrate through the opening;
A step of ion-implanting a second conductivity type impurity into the region on the substrate surface side of the substrate from the region where the first conductivity type impurity is ion-implanted through the opening;
Removing the resist film;
Forming a first sidewall spacer on the surface of the mask layer including the opening, and reducing the diameter of the opening;
A step of ion-implanting a first conductivity type impurity through the reduced opening;
Forming a second sidewall spacer on the sidewall of the reduced opening, and further reducing the diameter of the opening;
Etching the substrate using the reduced opening as a mask to form a groove adjacent to the photodiode;
Forming a gate insulating film by covering the bottom and side surfaces of the groove,
Forming a read gate electrode by embedding an electrode material in the groove where the gate insulating film is formed;
A method for manufacturing a solid-state imaging device including:   5. The method of manufacturing a solid-state imaging device according to claim 4, wherein the readout channel region is formed to a position deeper than a depth of a pn junction of a photodiode formed at a deepest position among the plurality of photodiodes. The mask layer has a two-layer structure of a nitride film and an oxide film formed in this order from the substrate side, and before the step of forming the gate insulating film, the oxide film and the opening constituting the mask layer Removing the first and second sidewall spacers formed to reduce the diameter of
6. The method of manufacturing a solid-state imaging device according to claim 5, wherein the electrode material is embedded in the groove and an opening made of a nitride film, and the upper part of the readout gate electrode is a planar electrode part for extracting an electrode. An optical lens,
A substrate, a plurality of photodiodes stacked in the depth direction of the substrate, a vertical readout gate electrode formed to be embedded in the depth direction of the substrate to read out signal charges of the photodiode, and a readout A dark current suppressing region formed of a first conductivity type semiconductor region formed to cover the bottom and side surfaces of the gate electrode and having a uniform width on the side surface of the read gate electrode; and the first conductivity type semiconductor region; A solid-state imaging device including a readout channel region formed of a semiconductor region of a second conductivity type between the photodiode and the photodiode; and
A signal processing circuit for processing an output signal of the solid-state imaging device;
Electronic equipment composed of

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