JP5365144B2 - SOLID-STATE IMAGING DEVICE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To adjust a gate interface by increasing a saturated charge amount Qs in a solid-state imaging device, and to suppress, for instance, the generation of a dark current or improve charge transfer by the adjustment of the gate interface. <P>SOLUTION: The solid-state imaging device includes: a photodiode PD embedded in a semiconductor substrate 11 and acting as a photoelectric conversion element; a vertical transfer transistor Tr1 of which the channel direction is vertical to the semiconductor substrate 11; and an impurity ion implantation region 25 for gate interface adjusting formed around a transfer gate of the vertical transfer transistor Tr1. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a solid-state imaging device, a manufacturing method thereof, and an electronic apparatus including the solid-state imaging device.

  Solid-state imaging devices are roughly classified into an amplification-type solid-state imaging device typified by a CMOS (Complementary Metal Oxide Semiconductor) image sensor and a charge transfer type solid-state imaging device typified by a CCD (Charge Coupled Device) image sensor. These solid-state imaging devices are widely used in digital still cameras, digital video cameras, and the like. In recent years, as a solid-state imaging device mounted on a mobile device such as a camera-equipped mobile phone or a PDA (Personal Digital Assistant), a CMOS image sensor is often used from the viewpoint of low power supply voltage and power consumption. .

  As a CMOS solid-state imaging device, a photoelectric conversion element (photodiode) is formed inside a p-type silicon semiconductor substrate, a vertical transfer transistor is formed, and the pixel size is reduced without reducing the saturation charge amount (Qs) and sensitivity. There has been proposed a solid-state imaging device that is miniaturized (see Patent Document 1). FIG. 26 shows a cross-sectional structure of a main part of a pixel of such a CMOS solid-state imaging device.

  The CMOS solid-state imaging device 111 is a back-illuminated solid-state imaging device that irradiates light from the back surface of the substrate. In the CMOS solid-state imaging device 111, pixel transistors constituting each pixel, in this example, a transfer transistor Tr1, a reset transistor Tr2, and an amplification transistor Tr3 are formed on the surface side of the semiconductor substrate 112. A photodiode PD is formed below these pixel transistors. The photodiode PD includes an n-type semiconductor region 113 composed of a high impurity region (n + region) 113A and a low impurity region (n region) 113B serving as a charge storage region inside the semiconductor substrate 112, and a high impurity concentration on the surface side thereof. A p-type semiconductor region (p + region) 114 is formed.

  The vertical transfer transistor Tr1 is a columnar shape embedded through a gate insulating film 115 in a trench 114 reaching the n-type high concentration impurity region (n + region) 113A of the photodiode PD in the depth direction from the surface of the semiconductor substrate 112. The transfer gate electrode 116 is configured. An n-type source / drain region 117 serving as a floating diffusion (FD) 40 is formed on the surface of the semiconductor substrate 112 so as to be in contact with the gate insulating film 115. The transfer gate electrode 116 of the vertical transfer transistor Tr1 is formed at a position corresponding to the center of the unit pixel 131, that is, the center of the photodiode PD. A high impurity concentration p-type semiconductor region (p + region) 121 is formed so as to surround the gate insulating film 115 formed in the high impurity concentration region (n + region) 113A of the photodiode PD.

  The reset transistor Tr2 includes a pair of n-type source / drain regions 117 and 118 on the surface side of the semiconductor substrate 112 and a reset gate electrode 123 formed through a gate insulating film. The amplification transistor Tr3 includes a pair of n-type source / drain regions 119 and 120 on the surface side of the semiconductor substrate 112, and a reset gate electrode 124 formed through a gate insulating film. Further, on the semiconductor substrate 112 on which the pixel transistors (Tr1, Tr2, Tr3) are formed, a multilayer wiring layer in which a plurality of wirings 126 are formed via an interlayer insulating film 125 is formed. Further, although not shown, an on-chip microlens or the like is formed on the back surface of the semiconductor substrate 112 at a position corresponding to the color filter and each pixel thereon. In FIG. 19, reference numeral 130 denotes a pixel separation region. Reference numeral 131 denotes a unit pixel.

In addition, a back-illuminated solid-state imaging device is also disclosed in Patent Document 2.
Japanese Patent Laying-Open No. 2005-223084 JP 2003-31785 A

  By the way, in the solid-state imaging device 111 described above, the vertical transfer transistor Tr1 is arranged at the center of the pixel so that the distance between the periphery of the photodiode PD and the transfer gate electrode 116 is the same, and complete transfer of signal charges is facilitated. It is supposed to be. However, the transfer gate electrode 116 is present to inhibit the formation of the photodiode PD. Therefore, the transfer gate electrode 116 cannot be formed as the photodiode PD, and the saturated charge amount (Qs) per unit area is reduced, which is a disadvantageous structure for pixel characteristics.

  In the solid-state imaging device 111, the effective channel length is determined by the distance between the photodiode PD and the floating diffusion FD (n-type source / drain region 117). However, in the case of this configuration, the n + region 113A is present in contact with the transfer gate electrode, and white damage due to dark current due to GIDL (Gate Induced Drain Leakage) occurs, which may greatly damage the pixel characteristics.

  In the solid-state imaging device 111, as shown in FIG. 26, a p− region 122 is formed on the surface of the n-type semiconductor region (n + region) 113A of the photodiode PD so as to surround the transfer gate electrode 116. The p− region 122 facilitates charge transfer at the transfer gate electrode 116 while maintaining the charge accumulation amount of the photodiode PD. However, if the area 122 is p−, it is difficult to actually secure the transfer path.

  In the solid-state imaging device 111, the p-region 122 is formed between the gate insulating film 115 associated with the transfer gate electrode 116 and the n-type semiconductor region (n + region) 113A of the photodiode PD, whereby the photodiode PD is formed. Generation of dark current due to defects is suppressed. However, in order to form the transfer gate electrode 116, it is necessary to suppress dark current generated from defects caused by damage caused when the silicon semiconductor substrate 112 is selectively etched, and the p− region 122 is insufficient. .

  In the solid-state imaging device 111, the channel region beside the transfer gate electrode between the n-type source / drain region 117 of the floating diffusion and the photodiode PD is a p-type region. However, with this structure, it is difficult to completely transfer the signal charges accumulated in the photodiode PD. In a solid-state imaging device, it is desired to improve charge transfer with an increase in the amount of saturated charges even if the pixels are miniaturized.

In view of the above, the present invention provides a solid-state imaging device in which the saturation charge amount (Qs) is increased and the transfer gate interface is adjusted, and a manufacturing method thereof.
Moreover, this invention provides the electronic device provided with the said solid-state imaging device.

A solid-state imaging device according to the present invention includes a photodiode serving as a plurality of layers of photoelectric conversion elements formed in a depth direction of a semiconductor substrate, a vertical transfer transistor having a channel direction perpendicular to the semiconductor substrate, an overflow path connecting the n-type semiconductor region serving as the charge accumulation region of the photodiode of the plurality of layers, and a vertical-type impurity ion implantation region for the gate interface adjustments formed around the transfer gate portion of the transfer transistor And the overflow path also serves as the channel region.

In the solid-state imaging device of the present invention, multiple layers of photodiodes are formed in the depth direction of the semiconductor substrate, and when one of the photodiodes reaches the saturation charge amount during charge accumulation, the overflowing signal charge is passed through the overflow path. It accumulates in a photodiode that is not saturated. As a result, the saturation charge amount (Qs) increases. Since an impurity ion implantation region for adjusting the gate interface is formed around the vertical transfer gate portion, a structure in which there is no afterimage and generation of white scratches can be realized. If the impurity ion implantation region is, for example, an n-type semiconductor region, the charge transfer efficiency is further improved. If the impurity ion-implanted region is a p-type semiconductor region, the generation of dark current is suppressed and the occurrence of white scratches is suppressed.

A method of manufacturing a solid-state imaging device according to the present invention includes a step of forming an overflow path connecting a plurality of photodiodes in the depth direction of a semiconductor substrate and an n-type semiconductor region serving as a charge storage region of each photodiode; A step of forming an impurity ion implantation region in contact with the overflow path in a depth direction of the semiconductor substrate; a step of forming a groove portion extending in the depth direction of the semiconductor substrate in the impurity ion implantation region; and an inner wall surface of the groove portion Forming a transfer gate electrode of the vertical transfer transistor so as to be embedded in the trench.

  In the method for manufacturing a solid-state imaging device according to the present invention, after forming a plurality of layers of photodiodes and an overflow path, an impurity ion implantation region is formed, and then a groove portion for embedding a transfer gate electrode is formed in the impurity ion implantation region. . Thereby, the impurity ion implantation region along the inner wall surface of the groove can be formed. In addition, a vertical transfer gate portion facing the overflow path across the impurity ion implantation region can be formed.

The method for manufacturing a solid-state imaging device according to the present invention includes a step of forming an impurity ion implantation region in the depth direction of the semiconductor substrate, and a step of forming a groove extending in the depth direction of the semiconductor substrate in the impurity ion implantation region. A step of connecting a plurality of photodiodes in the depth direction of the semiconductor substrate and an n-type semiconductor region serving as a charge storage region of each photodiode to form an overflow path in contact with the impurity ion implantation region, and an inner wall surface of the groove Forming a transfer gate electrode of the vertical transfer transistor so as to be embedded in the trench.

  In the method for manufacturing a solid-state imaging device according to the present invention, after forming an impurity ion implantation region and forming a groove portion for embedding a vertical transfer gate electrode in the impurity ion implantation region, a plurality of photodiodes and an overflow path are formed. ing. Thereby, the impurity ion implantation region along the inner wall surface of the groove can be formed. In addition, a vertical transfer gate portion facing the overflow path across the impurity ion implantation region can be formed.

An electronic apparatus according to the present invention includes an optical lens, a solid-state imaging device, and a signal processing circuit that processes an output signal of the solid-state imaging device. A solid-state imaging device includes a photodiode that is a multi-layer photoelectric conversion element formed in a depth direction of a semiconductor substrate, a vertical transfer transistor whose channel direction is perpendicular to the semiconductor substrate, and a vertical transfer the impurity ion implanted region formed around the transfer gate portion of the transistor, and a overflow path connecting the n-type semiconductor region serving as the charge accumulation region of the photodiode of the plurality of layers, the overflow path is a channel region It also serves.

According to the solid-state imaging device and the manufacturing method thereof according to the present invention, the saturation charge amount (Qs) of the unit pixel is increased, and the charge transfer is further improved and improved. A suppressed solid-state imaging device can be provided.
According to the electronic device according to the present invention, by providing the solid-state imaging device of the present invention, an electronic device with improved dynamic range and improved image quality can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a schematic configuration of an example of a solid-state imaging device applied to the present invention, that is, a CMOS solid-state imaging device. The solid-state imaging device 1 of this example includes a pixel unit (so-called imaging region) 3 in which pixels 2 including a plurality of photoelectric conversion elements are regularly arranged in a semiconductor substrate 11, for example, a silicon substrate, a peripheral circuit unit, It is comprised. The pixel 2 includes, for example, a photodiode serving as a photoelectric conversion element and a plurality of pixel transistors (so-called MOS transistors). The plurality of pixel transistors can be constituted by three transistors, for example, a transfer transistor, a reset transistor, and an amplification transistor. In addition, a selection transistor may be added to configure the transistor with four transistors. The equivalent circuit of the unit pixel is the same as usual. An example of a unit pixel will be described later.

  The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

  The control circuit 8 generates a clock signal and a control signal as a reference for operations of the vertical drive circuit 4, the column signal processing circuit 5, and the horizontal drive circuit 6 based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock, These signals are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.

  The vertical drive circuit 4 is configured by, for example, a shift register, and selectively scans each pixel 2 of the pixel unit 3 in the vertical direction sequentially in units of rows, and serves as a photoelectric conversion element of each pixel 2 through the vertical signal line 9, for example, in a photodiode. A pixel signal based on the signal charge generated according to the amount of received light is supplied to the column signal processing circuit 5.

  The column signal processing circuit 5 is arranged, for example, for each column of the pixels 2, and signals output from the pixels 2 for one row are generated from black reference pixels (formed around the effective pixel region) for each pixel column. The signal processing such as noise removal is performed by the signal. That is, the column signal processing circuit 5 performs signal processing such as CDS for removing fixed pattern noise unique to the pixel 2 and signal amplification. A horizontal selection switch (not shown) is connected to the horizontal signal line 10 at the output stage of the column signal processing circuit 5.

The horizontal drive circuit 6 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order. 10 to output.
The output circuit 7 performs signal processing and outputs the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10.

  FIG. 2 shows an example of an equivalent circuit of the unit pixel. The unit pixel 2 according to this circuit example includes a photodiode PD that is one photoelectric conversion element, and three pixel transistors that are a transfer transistor Tr1, a reset transistor Tr2, and an amplification transistor Tr3. These pixel transistors Tr1 to Tr3 are n-channel MOS transistors in this example.

  The transfer transistor Tr1 is connected between the cathode of the photodiode PD and the floating diffusion (FD). The signal charges (electrons in this example) that have been photoelectrically converted by the photodiode PD are transferred to the floating diffusion (FD) by applying a transfer pulse to the transfer gate.

  The reset transistor Tr2 has a drain connected to the selected power supply SELVDD and a source connected to the floating diffusion (FD). Prior to the transfer of signal charges from the photodiode PD to the floating diffusion (FD), a reset pulse is applied to the reset gate to reset the potential of the floating diffusion (FD). The selected power supply SELVDD is a power supply that selectively takes a VDD level and a GND level as a power supply voltage.

  The amplification transistor Tr3 has a source follower configuration in which a floating diffusion (FD) is connected to the amplification gate, a drain is connected to the selection power source SELVDD, and a source is connected to the vertical signal line 9. When the selected power source SELVDD becomes the VDD level, the pixel 2 is selected in the operating state. The potential of the floating diffusion (FD) after being reset by the reset transistor Tr2 is output to the vertical signal line 9 as a reset level. Further, the potential of the floating diffusion (FD) after the signal charge is transferred by the transfer transistor Tr1 is output to the vertical signal line 9 as a signal level.

  In the above-described solid-state imaging device, when configured as a backside illumination type in which light is incident from the backside of the substrate, an interlayer insulating film is interposed above the surface side of the semiconductor substrate on which the pixel unit 3 and the peripheral circuit unit are formed. A multilayer wiring layer is formed, and the back surface side becomes a light incident surface (so-called light receiving surface). An on-chip color filter is formed on the pixel portion 3 on the back surface through a planarizing film, and an on-chip microlens is further formed thereon.

  In the above-described solid-state imaging device, when configured to be a surface irradiation type in which light is incident from the substrate surface side, a multilayer is formed above the surface side of the substrate on which the pixel portion 3 and the peripheral circuit portion are formed via an interlayer insulating film. A wiring layer is formed. In the pixel unit 3, an on-chip color filter is formed on the multilayer wiring layer via a planarizing film, and an on-chip microlens is further formed thereon.

<First Embodiment>
[Configuration of solid-state imaging device]
FIG. 3 shows a first embodiment of a solid-state imaging device according to the present invention. FIG. 3 shows a cross-sectional structure of the main part of the pixel unit 3. In the solid-state imaging device 101 according to the present embodiment, a pixel isolation region 21 is formed in a first conductivity type, for example, a p-type silicon semiconductor substrate 11, and a photodiode PD and a pixel are formed in a region partitioned by the pixel isolation region 21. A unit pixel 2 made of a transistor is formed.
The unit pixel 2 is configured by forming a plurality of photodiodes PD [PD1, PD2, PD3] serving as photoelectric conversion elements in a semiconductor substrate 11 and forming a transfer transistor Tr1 as a vertical transistor. That is, the multi-layer photodiode PD [PD1, PD2, PD3] includes an n-type semiconductor region that is the second conductivity type and a p-type semiconductor region that is the first conductivity type in the depth direction of the semiconductor substrate 11. It is configured by alternately stacking. The pixel isolation region 21 can be formed by, for example, a p-type semiconductor region.

  In the vertical transfer transistor Tr <b> 1, a groove 22 extending perpendicularly in the depth direction is formed in the semiconductor substrate 11, and a columnar transfer gate electrode 24 is formed in the groove 22 via a gate insulating film 23. The transfer gate electrode is formed so that its upper portion extends along the surface of the semiconductor substrate 11, and the floating diffusion (FD) 40 formed by the n-type semiconductor region on the surface of the semiconductor substrate so as to be close to the projecting portion of the transfer gate. Is formed. The transfer transistor Tr1 is formed at the end of the unit pixel 2, that is, the end of the photodiode PD [PD1 to PD3].

  The first photodiode PD1 includes an n-type semiconductor region 28 and a p-type semiconductor region 29 thereon so that a pn junction surface is formed at the deepest position of the semiconductor substrate 11. The second photodiode PD2 is configured to include an n semiconductor region 30 and a p-type semiconductor region 31 thereon so that a pn junction surface is formed at an intermediate depth position of the semiconductor substrate 11. The third photodiode PD3 includes an n-type semiconductor region 32 and a p-type semiconductor region 33 thereon so that a pn junction surface is formed at a position on the surface side of the semiconductor substrate 11.

  The third photodiode PD3 formed on the surface side of the semiconductor substrate 11 is formed close to the transfer gate electrode 24 side, leaving the p-type semiconductor well region 27 in which the reset transistor Tr2 and the amplification transistor Tr3, which are pixel transistors, are formed. Is done.

  On the back side of the semiconductor substrate 11, an n-type semiconductor region (n− region) 37 having an impurity concentration lower than that of the n-type semiconductor region 28 is formed from immediately below the n-type semiconductor region 28 of the first photodiode PD1 to directly below the transfer gate portion. Is done.

  On the surface of the semiconductor substrate immediately below the portion of the transfer gate electrode 24 that protrudes from the substrate surface, a channel region 36 that leads to the floating diffusion (FD) 40 is formed continuously to the p-type semiconductor region 33 of the third photodiode PD3. Is done. The channel region 36 is formed of, for example, an n− region or a p− region.

  The floating diffusion (FD) 40 is formed on the surface of the semiconductor substrate, and is formed by self-alignment using the sidewalls 41 formed on the portion of the transfer gate electrode 24 protruding from the substrate surface as a mask.

  Further, in the present embodiment, an overflow path 35 is formed by the n-type semiconductor region that connects the n-type semiconductor regions 28, 30, and 32 that are charge storage regions of the photodiodes PD1 to PD3. Further, an impurity ion implantation region for adjusting the gate interface is formed around the transfer gate portion, that is, at the interface between the gate insulating film 25 formed on the inner wall surface of the groove portion 22 and the semiconductor substrate 11. In this example, a p-type semiconductor region 25 for suppressing dark current is formed as the impurity ion implantation region.

  The p-type semiconductor region 25 is a dark current generated from the interface between the gate insulating film 25 and the semiconductor substrate 11 due to crystal defects or distortion when the trench 22 is formed by selective etching or the like, and electric charges (electrons that cause white scratches). ) To recombine and disappear.

  The overflow path 35 is formed in contact with the p-type semiconductor region 25 for suppressing dark current, and also serves as the channel region 34 of the transfer gate portion. The overflow path 35 has a potential shallower than the depleted potential of the n-type semiconductor regions 28, 30, and 32, which are the charge storage regions of the photodiode PD [PD1 to PD3], during charge storage. The overflow path 25 has a deep potential that functions as a channel region 34 for transferring signal charges from the photodiode PD to the floating diffusion (FD) 40 by a transfer pulse applied to the transfer gate electrode during charge transfer. .

  The overflow path 35 has a function of accumulating charges that have not been accumulated in one photodiode PD (charges exceeding the saturation charge amount) in the adjacent photodiode PD beyond the potential of the overflow path 35 during light reception. Have.

  The overflow path 35 is formed in contact with the p-type semiconductor region 25 around the transfer gate portion. An overflow path 35 is formed between the p-type semiconductor regions 29 and 31 of the first and second photodiodes PD1 and PD2 and the transfer gate portion. That is, the p-type semiconductor regions 29 and 31 of the photodiode PD are formed offset by a required distance from the transfer gate portion. That is, the p-type semiconductor regions 29 and 31 are formed away from the transfer gate portion by the width of the overflow path 35.

  In the p-type semiconductor well region 27 on the surface of the semiconductor substrate 11, n-type source / drain regions 41, 42, 43 are formed. The pair of source / drain regions 41 and 42 and the reset gate electrode 45 formed via the gate insulating film 44 constitute a reset transistor Tr2. The other pair of source / drain regions 42 and 43 and the amplification gate electrode 46 formed through the gate insulating film 44 constitute an amplification transistor Tr3. A channel stop region 47 made of a p-type semiconductor region is formed at a required position on the surface of the semiconductor substrate 11.

Further, although not shown, a multilayer wiring layer is formed on the surface of the semiconductor substrate 11 by arranging a plurality of layers of wiring via an interlayer insulating film.
In addition, the solid-state imaging device 101 of the present embodiment is configured as a backside illumination type that irradiates light from the backside of the substrate. For this reason, although not shown, a p-type semiconductor region for dark current suppression with a high impurity concentration is formed on the back surface of the semiconductor substrate 11 so as to be in contact with the n-type semiconductor region (n− region) 37. Further, a color filter and an on-chip microlens are formed on the surface of the p-type semiconductor region via a planarizing film.

[Description of operation]
Next, the operation of the solid-state imaging device 101 according to the first embodiment will be described. At the time of charge accumulation, photoelectric conversion is performed by incident light to generate signal charges. The generated signal charge (electrons in this example) moves to the n-type semiconductor region according to the potential gradient, and is accumulated in the photodiode PD when the potential energy is minimized. That is, the n-type semiconductor region 28 of the first photodiode PD1, the n-type semiconductor region 30 of the second photodiode PD2, or the n-type semiconductor region 32 of the third photodiode PD3 on the substrate surface embedded in the substrate. Accumulated. Each n-type semiconductor region 28, 30, 32 is completely depleted, and signal charges are accumulated in its potential.

  When strong light is incident, the generated signal charge increases and exceeds the saturation charge amount of the n-type semiconductor region of any one of the photodiodes PD1, PD2, and PD3. When any one of the photodiodes PD1, PD2, and PD3 reaches the saturation charge amount, the charge exceeding the saturation charge amount exceeds the potential of the overflow path 35 and the n-type semiconductor of the photodiode PD that has not reached saturation. Accumulated in the area.

  As an example, when the n-type semiconductor region 28 of the first photodiode PD1 first reaches the saturation charge amount, the charge exceeding the saturation charge amount passes through the overflow path 35 and the n-type semiconductor of the second photodiode PD2 adjacent thereto. Accumulated in area 30. When the n-type semiconductor region 30 of the second photodiode PD2 reaches the saturation charge amount, the charge exceeding the saturation charge amount is accumulated in the n-type semiconductor region 32 of the adjacent third photodiode PD3 through the overflow path 35. . Further, when the n-type semiconductor region 32 of the third photodiode PD3 reaches the saturation charge amount, the charge exceeding the saturation charge amount flows to the floating diffusion (FD) 40 through the channel region 36 and is discharged.

  At the time of charge transfer, a transfer pulse (positive voltage in this example) is applied to the transfer gate electrode 24 of the transfer transistor Tr1, thereby turning on the transfer transistor Tr1. That is, by applying the transfer pulse, the potential of the n-type semiconductor regions 28, 30, 32 of each photodiode PD [PD1, PD2, PD3] and the overflow path 35 connected to them is modulated. That is, the potential of the overflow path 35 is deepened, and a potential gradient is formed toward the transfer gate portion. According to this potential gradient, signal charges accumulated in any of the photodiodes PD [PD1 to PD3] or in all the n-type semiconductor regions (28, 30, 32) of the photodiodes PD are transferred to the transfer gate portion. The signal charges reaching the transfer gate portion are transferred to the channel region 36 below the transfer gate portion on the substrate surface side along the transfer gate portion extending in the vertical direction of the substrate, with the overflow path 35 serving as the transfer channel 34. Thereafter, the signal charge moves to the floating diffusion (FD) 40 according to the potential gradient formed in the channel region 36 under the surface transfer gate portion.

  According to the solid-state imaging device 101 according to the first embodiment, a plurality of photodiodes PD [PD1 to PD3] are stacked in the depth direction of the semiconductor substrate 11, and the photodiodes PD1 to PD3 are connected via the overflow path 35. The n-type semiconductor regions 28 to 32 are connected. When the amount of saturation charge is reached in any photodiode PD during charge accumulation, the charge exceeding the amount of saturation charge is accumulated in another non-saturated photodiode PD through the overflow path 35. With this configuration, even when the pixel size is reduced, the effective saturation charge amount (Qs) per unit pixel increases, the dynamic range can be increased, and the contrast can be improved.

  By forming the transfer transistor Tr1 as a vertical transistor and forming the transfer transistor Tr1 at the end of the pixel 2, the area of the photodiode PD [PD1 to PD3] can be increased, and the saturation charge amount per unit area (Qs) can be increased. By forming the p-type semiconductor region 25 that covers the entire transfer gate portion of the vertical transfer transistor Tr1, generation of dark current due to defects present on the side and bottom of the vertical transfer transistor Tr1 is suppressed. The occurrence of white scratches can be suppressed.

  A plurality of photodiodes PD are stacked, and an overflow path 35 is formed between the p-type semiconductor regions 29 and 31 constituting the photodiode PD and the transfer gate portion. That is, the p-type semiconductor regions 29 and 31 of the photodiode PD are formed offset from the transfer gate portion by a required distance. By adjusting the offset amount, the signal charge accumulated in the photodiode PD can be completely transferred in the vertical direction through the channel region 34 that also serves as the overflow path 35. In addition, a saturation charge amount (Qs) that can be accumulated in the photodiode PD can be secured. In addition, it is possible to design a structure that can ensure such complete transfer and a saturation charge amount (Qs).

[Method for Manufacturing Solid-State Imaging Device (1)]
4 to 11 show an example of a method for manufacturing the solid-state imaging device 101 according to the first embodiment. First, as shown in FIG. 4, a p-type semiconductor well region 27 is formed in a p-type semiconductor substrate 11. A first photodiode PD1 and a second photodiode PD2 are stacked in the depth direction of the p-type semiconductor well region 27. The first photodiode PD1 is formed by stacking an n-type semiconductor region 28 and a p-type semiconductor region 29 at the deepest portion of the semiconductor substrate 11 so as to have a pn junction surface. The second photodiode PD2 is formed by stacking an n-type semiconductor region 30 and a p-type semiconductor region 31 so that a pn junction is similarly formed in the intermediate portion of the semiconductor substrate 11. These n-type semiconductor regions 28 and 30 and p-type semiconductor regions 29 and 31 are formed so as to alternately contact each other.

  Further, an overflow path 35 is formed by the n-type semiconductor region connecting the n-type semiconductor regions 28 and 30 of the first and second photodiodes PD1 and PD2. Further, an n-type semiconductor region 37 having a lower impurity concentration than the n-type semiconductor region 28 extending to the bottom of a transfer gate portion to be formed later is formed immediately below the n-type semiconductor region 28 of the first photodiode PD1 of the semiconductor substrate 11. . Each of the above-described regions is formed using an ion implantation method.

  Next, as shown in FIG. 5, a pixel isolation region 21 by a p-type semiconductor region for partitioning a unit pixel in the semiconductor substrate 11 is formed by ion implantation. Further, a channel stop region 47 having an STI structure is formed in a required portion on the surface side of the semiconductor substrate 11. This STI (Shallow Trench Isolation) structure is formed by forming a groove having a required depth from the substrate surface by selective etching and filling the groove with a silicon oxide film. The channel stop region 47 having the STI structure corresponds to a so-called element isolation region.

  Next, as shown in FIG. 6, an insulating film, for example, a silicon oxide film 55 and a silicon nitride film 56 are sequentially formed on the surface of the semiconductor substrate 11 so as to be flush with the upper surface of the channel stop region 47. A resist mask 51 having an opening 52 is formed on the silicon nitride film 56 corresponding to the portion where the vertical transfer gate electrode is to be formed. The opening 52 is formed so as to be positioned at the end of the pixel. A p-type impurity 53 is ion-implanted through the opening 52 of the resist mask 52 to form a p-type semiconductor region 25 for suppressing dark current in the semiconductor substrate 11. The p-type semiconductor region 25 is in contact with the n-type overflow path 35 connecting the n-type semiconductor regions of the photodiodes PD [PD1, PD2, PD3] and reaches the low impurity concentration n-type semiconductor region 37. Or the vicinity thereof.

  Next, as shown in FIG. 7, isotropic etching is performed on the opening 52 of the resist mask 51. By this isotropic etching, sidewalls 56a made of the silicon nitride film 56 are formed.

  Next, as shown in FIG. 8, the resist mask 51 is removed, and using the silicon nitride film 56 having the sidewalls 56a as a mask, the p-type semiconductor region 25 is selectively etched by anisotropic etching to form the groove 22. Go. The groove 22 is formed by so-called self-alignment. The p-type semiconductor region 25 and the trench 22 are formed at the pixel end.

  Then, as shown in FIG. 9, the selective etching is advanced to form the groove 22 so that the p-type semiconductor region 25 remains with a required width on the inner wall of the groove and the lower surface of the groove. Thereafter, the silicon oxide film 55 and the silicon nitride film 56 are removed.

Next, as shown in FIG. 10, a gate insulating film 23 is formed over the inner surface of the groove 22 and the surface of the semiconductor substrate 11. As the gate insulating film 23, for example, a silicon oxide (SiO ₂ ) film can be used. Thereafter, a gate electrode material, for example, a polysilicon film is formed over the surface of the semiconductor substrate 11 so as to be embedded in the trench 22 and patterned. As a result, a columnar transfer gate electrode 24 is formed which partially projects on the substrate surface and is embedded in the groove 22. Further, a reset gate electrode 45 and an amplification gate electrode 46 made of, for example, a similar polysilicon film are formed on the p-type semiconductor well region 27 on the substrate surface via the gate insulating film 23.

  Next, as shown in FIG. 11, sidewalls 48 are formed on the transfer gate electrode 24, the reset gate electrode 45, and the amplification gate electrode 46, respectively. N-type impurities are ion-implanted using each side wall 48 as a mask, and floating diffusion (FD) 40 and source / drain regions 41, 42, 43 are formed by n-type semiconductor regions by self-alignment. Thereby, the vertical transfer transistor Tr1, the reset transistor Tr2, and the amplification transistor Tr3 are formed. The vertical transfer transistor Tr1 is formed at the pixel end.

  After or before this step, the third photodiode PD3 is formed on the surface of the p-type semiconductor well region 27. The third photodiode PD3 is formed by stacking an n-type semiconductor region 32 and a p-type semiconductor region 33 thereon by ion implantation so as to form a pn junction. Further, an n − region or a p − region channel region 36 is formed which continues to the p type semiconductor region 33 and reaches the p type semiconductor region 25 for dark current suppression.

  Thereafter, as usual, a multilayer wiring layer in which a plurality of layers of wirings are arranged on the surface side of the semiconductor substrate 11 via an interlayer insulating film is formed. A p-type semiconductor region for suppressing dark current, a planarizing film, a color filter, and an on-chip microlens are sequentially formed on the back surface of the semiconductor substrate 11 so as to be in contact with the n-type semiconductor region 37. In this way, the target back-illuminated solid-state imaging device 101 is obtained.

[Method for Manufacturing Solid-State Imaging Device (2)]
12 to 18 show another example of the method for manufacturing the solid-state imaging device 101 according to the first embodiment. First, as shown in FIG. 12, a p-type semiconductor well region 27 is formed in a p-type semiconductor substrate 11, and an n-type semiconductor region 37 having a low impurity concentration is formed thereunder. A pixel isolation region 21 is formed in the p-type semiconductor well region 27 by a p-type semiconductor region for partitioning a unit pixel.

  Then, an insulating film, for example, a silicon oxide film 55 and a silicon nitride film 56 are sequentially formed on the surface of the semiconductor substrate 11 so as to be flush with the upper surface of the channel stop region 47. A resist mask 51 having an opening 52 is formed on the silicon nitride film 56 corresponding to the portion where the vertical transfer gate electrode is to be formed. The opening 52 is formed so as to be positioned at the end of the pixel. A p-type impurity 53 is ion-implanted through the opening 52 of the resist mask 52 to form a p-type semiconductor region 25 for suppressing dark current in the semiconductor substrate 11. The p-type semiconductor region 25 is formed up to or near the low impurity concentration n-type semiconductor region 37.

  Next, as shown in FIG. 13, isotropic etching is performed on the opening 52 of the resist mask 51. By this isotropic etching, sidewalls 56a made of the silicon nitride film 56 are formed.

  Next, as shown in FIG. 14, the resist mask 51 is removed, and the p-type semiconductor region 25 is selectively etched by anisotropic etching using the silicon nitride film 56 having the sidewalls 56a as a mask to form the groove 22. Go. The groove 22 is formed by so-called self-alignment. The p-type semiconductor region 25 and the trench 22 are formed at the pixel end.

  Then, as shown in FIG. 15, the selective etching is advanced to form the groove 22 so that the p-type semiconductor region 25 remains with a required width on the groove inner wall and the groove lower surface. Thereafter, the silicon oxide film 55 and the silicon nitride film 56 are removed.

  Next, as shown in FIG. 16, a first photodiode PD1 and a second photodiode PD2 are stacked in the depth direction of the p-type semiconductor well region 27 partitioned by the pixel isolation regions 21. The first photodiode PD1 is formed by stacking an n-type semiconductor region 28 and a p-type semiconductor region 29 at the deepest portion of the semiconductor substrate 11 so as to have a pn junction surface. The second photodiode PD2 is formed by stacking an n-type semiconductor region 30 and a p-type semiconductor region 31 so that a pn junction is similarly formed in the intermediate portion of the semiconductor substrate 11. These n-type semiconductor regions 28 and 30 and p-type semiconductor regions 29 and 31 are formed so as to alternately contact each other.

  Further, an overflow path 35 is formed by the n-type semiconductor region connecting the n-type semiconductor regions 28 and 30 of the first and second photodiodes PD1 and PD2. The n-type semiconductor region 28 and the overflow path 35 located at the deepest portion are formed in contact with the lower n-type semiconductor region 37 having a low impurity concentration. Each of the above-described regions is formed using an ion implantation method.

  Next, as shown in FIG. 17, a channel stop region 47 made of a high impurity concentration p-type semiconductor region is formed in a required portion on the surface side of the semiconductor substrate 11. The channel stop region 47 of the p-type semiconductor region corresponds to a so-called element isolation region.

Further, a gate insulating film 23 is formed over the inner surface of the trench 22 and the surface of the semiconductor substrate 11. As the gate insulating film 23, for example, a silicon oxide (SiO ₂ ) film can be used. Thereafter, a gate electrode material, for example, a polysilicon film is formed over the surface of the semiconductor substrate 11 so as to be embedded in the trench 22 and patterned. As a result, a columnar transfer gate electrode 24 is formed which partially projects on the substrate surface and is embedded in the groove 22. Further, a reset gate electrode 45 and an amplification gate electrode 46 made of, for example, a similar polysilicon film are formed on the p-type semiconductor well region 27 on the substrate surface via the gate insulating film 23.

  Next, as shown in FIG. 18, sidewalls 48 are formed on the transfer gate electrode 24, the reset gate electrode 45, and the amplification gate electrode 46, respectively. N-type impurities are ion-implanted using the respective side walls 48 as masks, and floating diffusion (FD) 40 and source / drain regions 41, 42, and 43 are formed by n-type semiconductor regions by self-alignment. Thereby, the vertical transfer transistor Tr1, the reset transistor Tr2, and the amplification transistor Tr3 are formed. The vertical transfer transistor Tr1 is formed at the pixel end.

  After or before this step, the third photodiode PD3 is formed on the surface of the p-type semiconductor well region 27. The third photodiode PD3 is formed by stacking an n-type semiconductor region 32 and a p-type semiconductor region 33 thereon by ion implantation so as to form a pn junction. Further, an n − region or a p − region channel region 36 is formed which continues to the p type semiconductor region 33 and reaches the p type semiconductor region 25 for dark current suppression.

  Thereafter, as usual, a multilayer wiring layer in which a plurality of layers of wirings are arranged on the surface side of the semiconductor substrate 11 via an interlayer insulating film is formed. A p-type semiconductor region for suppressing dark current, a planarizing film, a color filter, and an on-chip microlens are sequentially formed on the back surface of the semiconductor substrate 11 so as to be in contact with the n-type semiconductor region 37. In this way, the target back-illuminated solid-state imaging device 101 is obtained.

  As another method of forming the p-type semiconductor region 25, the groove portion 22 can be formed first, and then the p-type semiconductor region 25 can be formed on the inner wall surface of the groove portion 22 by an oblique ion implantation method.

  According to the method for manufacturing the solid-state imaging device described above, dark current suppression covering the plurality of photodiodes PD stacked in the depth direction of the semiconductor substrate 11, the overflow path 35, and the transfer gate portion of the vertical transfer transistor Tr1. A p-type semiconductor region 25 can be formed. That is, in each example, the solid-state imaging device 101 in which the saturation charge amount (Qs) is increased and the generation of white current is suppressed by suppressing the generation of dark current can be manufactured.

  In the manufacturing method of the present embodiment, n-type impurities are ion-implanted by self-alignment using the side walls 48 of the side walls of the gate electrodes 24, 45, and 56 as masks to form source / drain regions (n + regions) 41, 42, 43, and FD. Form. For this reason, the photodiode (FD) 40 due to the n + region does not flow under the transfer gate portion, and the dark current caused by GIDL can be suppressed. In addition, since the floating diffusion (FD) 40 is formed using the side wall 48 as a mask, the floating diffusion (FD) 40 can be used for vertical transfer even if a mask shift occurs when the vertical transfer transistor Tr1 is formed. It can be formed at a constant distance from the gate portion.

  In the p-type semiconductor region 25 around the vertical transfer gate portion, the p-type semiconductor region 25 is formed by ion implantation through the resist mask 51, and then the sidewall 54 is formed by isotropic etching with respect to the mask opening 52. Then, a part of the p-type semiconductor region 25 is selectively etched by self-alignment. For this reason, the p-type semiconductor region 22 corresponding to the wall surface of the groove portion 22 having a high aspect ratio can be formed with high accuracy.

  First, the p-type semiconductor region 25 is formed, and then the p-type semiconductor region 25 is selectively etched to form the groove 22. Therefore, the p-type semiconductor region 25 is formed at the bottom of the groove 22. Therefore, it is possible to suppress dark current caused by defects generated at the bottom of the vertical transfer transistor Tr1, and to suppress the occurrence of white scratches.

<Second Embodiment>
[Configuration of solid-state imaging device]
FIG. 19 shows a second embodiment of the solid-state imaging device according to the present invention. The solid-state imaging device 102 according to the present embodiment is the same as the solid-state imaging device 101 according to the first embodiment, except that the n-type semiconductor region 32 and the p-type semiconductor region 33 that are the third photodiodes PD3 on the substrate surface side, and the channel region. 36 is omitted. In this configuration, the p-type semiconductor well region under the transfer gate portion between the second photodiode PD2 and the substrate surface acts as the channel region 361. Since other configurations are the same as those of the first embodiment, portions corresponding to those in FIG.

  The operation of the solid-state imaging device 102 in the present embodiment is the same as that described in the first embodiment.

  According to the solid-state imaging device 102 according to the second embodiment, since the third photodiode PD3 on the substrate surface side is omitted, it is suitable when the pixel size is further miniaturized. In other words, even if the pixel size is reduced to the extent that it is difficult to form the third photodiode PD3 on the substrate surface, the first and second photodiodes PD1 and PD2 are formed in the depth direction, so that saturation occurs. The amount of charge (Qs) can be secured and dark current can be suppressed. In addition, the same effects as described in the first embodiment can be obtained.

<Third Embodiment>
[Configuration of solid-state imaging device]
FIG. 20 shows a third embodiment of the solid-state imaging device according to the present invention. The solid-state imaging device 103 according to the present embodiment has two photodiodes as a plurality of photodiodes, a first photodiode PD1 embedded in the substrate and a third photodiode PD3 on the substrate surface side. Configured. That is, the second photodiode PD2 in the first embodiment is omitted. Also in this example, an overflow path 35 is formed by an n-type semiconductor region that connects the n-type semiconductor regions 28 and 32 that are charge storage regions of the first photodiode PD1 and the third photodiode PD3. The overflow path 35 also serves as the channel region 34 of the transfer gate portion. Since the other configuration is the same as that of the first embodiment described above, the same reference numerals are given to the portions corresponding to those in FIG. 3 in FIG.

  The solid-state imaging device 103 according to the third embodiment is configured to include two photodiodes PD, that is, a first photodiode PD1 embedded in the substrate and a third photodiode PD2 on the substrate surface side. Yes. With this configuration, the saturation charge amount (Qs) can be ensured and dark current can be suppressed. By using a two-layer structure of the photodiodes PD1 and PD3, the depth of the vertical transfer transistor Tr1 can be reduced. Thereby, the transfer efficiency can be improved by shortening the transfer path, and the occurrence of white scratches can be suppressed by reducing the area of the interface. In addition, the same effects as described in the first embodiment can be obtained.

<Fourth embodiment>
[Configuration of solid-state imaging device]
Although not shown, the solid-state imaging device according to the fourth embodiment is configured by forming only one photodiode PD as a photodiode. That is, the solid-state imaging device according to the present embodiment has a configuration in which the second photodiode PD2, the third photodiode PD3, and the channel region 36 are omitted from the configuration of the solid-state imaging device 101 of the first embodiment. A p-type semiconductor well region 27 under the transfer gate portion between the first photodiode PD1 and the substrate surface functions as a channel region. Other configurations are the same as those in FIG.

  Also in the solid-state imaging device according to the fourth embodiment, since the transfer transistor Tr1 is formed at the pixel end, the area of the photodiode PD can be increased, and the saturation charge amount (Qs) can be increased. . In addition, since the p-type semiconductor region 25 is formed around the vertical transfer gate portion, the generation of dark current can be suppressed and the occurrence of white scratches can be suppressed.

  In the solid-state imaging device according to the fourth embodiment, an n-type semiconductor region may be formed around the transfer gate portion of the vertical transfer transistor instead of the p-type semiconductor region. In the case of this configuration, the charge transfer efficiency can be further improved.

<Fifth embodiment>
[Configuration of solid-state imaging device]
21 to 22 show a fifth embodiment of the solid-state imaging device according to the present invention. In the solid-state imaging device 106 according to the present embodiment, a pixel configuration (hereinafter referred to as a shared pixel) 61 in which other pixel transistors excluding a transfer transistor are shared with respect to a plurality of photodiodes, in this example, two photodiodes. It is composed of a dimensional array.

  FIG. 23 shows a circuit configuration of the shared pixel 61 sharing the two pixels of the present embodiment. Two photodiodes PD (A) and PD (B) are connected to the sources of the corresponding two transfer transistors Tr1A and Tr1B, respectively. The drains of the transfer transistors Tr1A and Tr1B are connected to the source of one reset transistor Tr2. A common floating diffusion (FD) 40 between the transfer transistors Tr1A and Tr1B and the reset transistor Tr12 is connected to the gate of one amplification transistor Tr3. The drain of the reset transistor Tr2 and the drain of the amplification transistor Tr are connected to the above-described selection power source SELVDD, and the source of the amplification transistor Tr3 is connected to the vertical signal line 9.

  FIG. 21 shows a schematic planar structure of the shared pixel 61. In the shared pixel 61, a common floating diffusion (FD) 40 is disposed at the center, and two photodiodes PD (A) and PD (B) are disposed with the floating diffusion (FD) 40 interposed therebetween. Each of the transfer transistors Tr1A and Tr1B is disposed to face the end of each pixel, that is, a position corresponding to the corner portion of the photodiodes PD (A) and PD (B). The respective transfer gate electrodes 24A and 24B are formed between the photodiodes PD (A) and PD (B) and the floating diffusion (FD) 40. As shown in FIG. 22, the reset transistor Tr2 and the amplification transistor Tr3 are formed on the substrate surface side on the photodiode.

  Then, as shown in FIG. 22, the solid-state imaging device 105 according to the present embodiment includes two sets of vertical transfer transistors and photodiodes symmetrically across the floating diffusion (FD) 40 at the center. A configuration is formed. That is, the configuration of the vertical transfer transistor Tr1A and the photodiode PD (A) is arranged on one side, and the configuration of the vertical transfer transistor Tr1B and the photodiode PD (B) is arranged on the other side. The reset transistor Tr2 and the amplification transistor Tr3 are formed in the p-type semiconductor well region 27.

  The configuration of the vertical transfer transistors Tr1A and Tr1B, the configuration of the first to third photodiodes PD1 to PD3, and the photodiodes PD (A) and PD (B) having the overflow path 35 are the same as those shown in FIG. is there. Detailed description is omitted.

  According to the pixel sharing solid-state imaging device 106 according to the fifth embodiment, the saturation charge amount (Qs) of the unit pixel increases, and the pixel sharing further increases the photodiode area due to the pixel sharing. The quantity (Qs) increases. In addition, since the p-type semiconductor region 25 is formed around the vertical transfer gate portion, dark current due to defects existing beside the vertical transfer gate portion is suppressed, and the occurrence of white scratches can be suppressed. it can. In addition, the same effects as described in the first embodiment can be obtained.

<Sixth embodiment>
[Configuration of solid-state imaging device]
FIG. 24 shows a sixth embodiment of the solid-state imaging device according to the present invention. In the solid-state imaging device 106 according to the present embodiment, as described above, a plurality of photodiodes PD [PD1, PD2, PD3] are formed in the depth direction of the semiconductor substrate 11, and the transfer transistor Tr1 has a channel direction in the semiconductor substrate. It is formed in a vertical shape perpendicular to the above. In addition, an overflow path 35 is formed by the n-type semiconductor region that connects the n-type semiconductor regions 28, 30, and 32 serving as charge storage regions of the photodiodes PD1 to PD3. In this example, the overflow path 35 is configured also as the channel region 34.

  Furthermore, in the present embodiment, an impurity ion implantation region for adjusting the gate interface is formed around the transfer gate portion, that is, at the gate interface between the gate insulating film 25 formed on the inner wall surface of the trench 22 and the semiconductor substrate 11. . In this example, an n-type semiconductor region 58 is formed as an impurity ion implantation region. The n-type semiconductor region 58 is formed by an ion implantation process different from the formation of the overflow path 35 and the n-type semiconductor regions 28, 30, and 32 of the photodiode PD, and is used for improving charge transfer efficiency. The n-type semiconductor region 58 is not formed at the bottom of the groove portion 22 but is formed of a p-type semiconductor region. The n-type semiconductor region 58 is formed by applying the same method as the formation of the dark current suppressing p-type semiconductor region 25 of the first embodiment described above, and then implanting the n-type impurity into the semiconductor substrate and then forming the groove 22. As it is formed, it can be formed. Alternatively, the n-type semiconductor region 58 can be formed by a method of implanting oblique ions into the sidewall of the groove after forming the groove. Since other configurations are the same as those of the first embodiment, portions corresponding to those in FIG.

  According to the solid-state imaging device 106 according to the sixth embodiment, a plurality of photodiodes PD [PD1 to PD3] are stacked in the depth direction of the semiconductor substrate 11, and the photodiodes PD1 to PD3 are connected via the overflow path 35. The n-type semiconductor regions 28 to 32 are connected. When the amount of saturation charge is reached in any photodiode PD during charge accumulation, the charge exceeding the amount of saturation charge is accumulated in another non-saturated photodiode PD through the overflow path 35. With this configuration, even when the pixel size is reduced, the effective saturation charge amount (Qs) per unit pixel increases, the dynamic range can be increased, and the contrast can be improved.

  Furthermore, since the n-type impurity ion implantation region 58 is formed at the gate interface around the vertical transfer gate portion, the charge transfer efficiency can be further improved.

  By configuring the transfer transistor Tr1 as a vertical transistor and forming the transfer transistor Tr1 at the end of the pixel 2, the area of the photodiode PD [PD1 to PD3] can be increased, and the saturation charge per unit area The amount (Qs) can be increased.

  In addition, as described in the first embodiment, a plurality of photodiodes PD are stacked, and an overflow path 35 is formed between the p-type semiconductor regions 29 and 31 constituting the photodiode PD and the transfer gate portion. The That is, the p-type semiconductor regions 29 and 31 of the photodiode PD are formed offset by a required distance from the transfer gate portion. By adjusting the offset amount, the signal charge accumulated in the photodiode PD can be completely transferred in the vertical direction through the channel region 34 that also serves as the overflow path 35. In addition, a saturation charge amount (Qs) that can be accumulated in the photodiode PD can be secured. In addition, it is possible to design a structure that can ensure such complete transfer and a saturation charge amount (Qs).

  The configuration in which the n-type semiconductor region 58 is provided around the vertical transfer gate portion in the sixth embodiment is the same as the solid-state imaging device having the photodiode configuration shown in the second, third, and fifth embodiments. Can also be applied.

  In the above embodiments, the solid-state imaging device using electrons as signal charges has been described. The present invention can also be applied to a solid-state imaging device using holes as signal charges. In this case, the conductivity type of each semiconductor region is configured such that the first conductivity type is n-type and the second conductivity type is p-type, contrary to the above example.

<Seventh embodiment>
[Configuration of electronic equipment]
The solid-state imaging device according to the present invention is applied to an electronic device such as a camera system such as a digital camera or a video camera provided with the solid-state imaging device, a mobile phone having an imaging function, or another device having an imaging function. Can do.

  FIG. 25 shows a fifth embodiment applied to a camera as an example of an electronic apparatus according to the invention. The camera according to the present embodiment is an example of a video camera that can shoot a still image or a moving image. The camera 91 according to the present embodiment includes a solid-state imaging device 92, an optical lens (optical system) 93, a shutter device 94, a drive circuit 95, and a signal processing circuit 96.

  As the solid-state imaging device 92, any one of the above-described first to sixth embodiments is applied. Preferably, the solid-state imaging devices of the first, second, third, fifth, and sixth embodiments are applied. The optical lens 93 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 92. Thus, the optical lens 93 in which signal charges are accumulated in the solid-state imaging device 92 for a certain period may be an optical lens system including a plurality of optical lenses. The shutter device 94 controls a light irradiation period and a light shielding period for the solid-state imaging device 92. The drive circuit 95 supplies a control signal for controlling the transfer operation and the shutter operation of the solid-state imaging device 92. Signal transfer of the solid-state imaging device 92 is performed by a drive signal (timing signal) supplied from the drive circuit 95. The signal processing circuit 96 performs various signal processing. The video signal subjected to the signal processing is stored in a recording medium such as a memory or output to a monitor.

  In the camera 90 of the present embodiment, the saturation charge amount (Qs) can be increased, the dynamic range can be improved, and the generation of white current can be suppressed by suppressing the generation of dark current, and the pixel size can be reduced. To. For this reason, it is possible to reduce the size of the electronic device and to obtain an electronic device with high image quality.

It is a schematic block diagram which shows an example of the solid-state imaging device applied to this invention. FIG. 2 is an equivalent circuit diagram illustrating an example of a unit pixel in FIG. 1. It is a block diagram of the principal part which shows 1st Embodiment of the solid-state imaging device concerning this invention. It is a manufacturing process figure (the 1) which shows an example of the manufacturing method of the solid-state imaging device concerning the present invention. It is a manufacturing process figure (the 2) which shows an example of the manufacturing method of the solid-state imaging device which concerns on this invention. It is a manufacturing process figure (the 3) which shows an example of the manufacturing method of the solid-state imaging device which concerns on this invention. It is a manufacturing process figure (the 4) which shows an example of the manufacturing method of the solid-state imaging device which concerns on this invention. It is a manufacturing process figure (the 5) which shows an example of the manufacturing method of the solid-state imaging device which concerns on this invention. It is a manufacturing process figure (the 6) which shows an example of the manufacturing method of the solid-state imaging device which concerns on this invention. It is a manufacturing process figure (the 7) which shows an example of the manufacturing method of the solid-state imaging device which concerns on this invention. It is a manufacturing process figure (the 8) which shows an example of the manufacturing method of the solid-state imaging device which concerns on this invention. It is manufacturing process figure (the 1) which shows the other example of the manufacturing method of the solid-state imaging device which concerns on this invention. It is a manufacturing process figure (the 2) which shows the other example of the manufacturing method of the solid-state imaging device which concerns on this invention. It is a manufacturing-process figure (the 3) which shows the other example of the manufacturing method of the solid-state imaging device which concerns on this invention. It is a manufacturing process figure (the 4) which shows the other example of the manufacturing method of the solid-state imaging device which concerns on this invention. It is a manufacturing process figure (the 5) which shows the other example of the manufacturing method of the solid-state imaging device which concerns on this invention. It is a manufacturing process figure (the 6) which shows the other example of the manufacturing method of the solid-state imaging device which concerns on this invention. It is a manufacturing process figure (the 7) which shows the other example of the manufacturing method of the solid-state imaging device which concerns on this invention. It is a block diagram of the principal part which shows 2nd Embodiment of the solid-state imaging device which concerns on this invention. It is a block diagram of the principal part which shows 3rd Embodiment of the solid-state imaging device which concerns on this invention. It is a top view of the principal part which shows 5th Embodiment of the solid-state imaging device concerning this invention. It is sectional drawing on the AA line of FIG. It is an equivalent circuit diagram which shows an example of the shared pixel of the solid-state image sensor which concerns on 5th Embodiment. It is a block diagram of the principal part which shows 6th Embodiment of the solid-state imaging device concerning this invention. It is a block diagram of 5th Embodiment which applied the electronic device which concerns on this invention to the camera. It is a block diagram of the principal part which shows an example of the conventional solid-state imaging device.

Explanation of symbols

  1 .... Solid-state imaging device 2 .... Pixel 3 .... Pixel unit 4 .... Vertical drive circuit 5 .... Column signal processing circuit 6 .... Horizontal drive circuit 7 .... Output unit 8 .... Control Circuits 9... Vertical signal lines 10... Horizontal signal lines 101... Solid state imaging device PD1 to PD3... Photodiode, Tr1 .. Vertical transfer transistor, Tr2 .. Reset transistor, Tr3. Transistors 11... Semiconductor substrate 21... Pixel isolation region 22.. Groove portion 23.. Gate insulating film 24.. Transfer gate electrode 25.. P-type semiconductor region 28, 30, 32. .. type semiconductor region 29, 31, 33... P-type semiconductor region 34 .. channel region 35 .. overflow path 36 .. channel region 40 .. floating diffusion 47 .. channel stop Frequency (isolation), 48 ... side wall, 58 ... n-type semiconductor region

Claims (16)

A photodiode serving as a multi-layer photoelectric conversion element formed in the depth direction of the semiconductor substrate; a vertical transfer transistor having a channel direction perpendicular to the semiconductor substrate;
An overflow path connecting n-type semiconductor regions that are charge storage regions of the multiple-layer photodiode;
An impurity ion implantation region for gate interface adjustment formed around the transfer gate portion of the vertical transfer transistor ,
A solid-state imaging device in which the overflow path also serves as a channel region . The overflow path of the second conductivity type, p-type solid-state imaging device according to claim 1, wherein the semiconductor region is formed between the transfer gate portion of the photodiode. The solid-state imaging device according to claim 1, wherein the impurity ion implantation region for gate interface adjustment is an n-type semiconductor region. The solid-state imaging device according to claim 1, wherein the impurity ion implantation region for adjusting the gate interface is a p-type semiconductor region for suppressing dark current. The solid-state imaging device according to claim 1, wherein the vertical transfer transistor is disposed at a pixel end. The solid-state imaging device according to claim 5, further comprising a floating diffusion region of an n-type semiconductor region on a surface of the semiconductor substrate. The floating diffusion region is shared with other pixel transistors except the transfer transistor for a plurality of photodiodes,
Said transfer transistor, the solid-state imaging device according to claim 1 wherein formed at the end of each unit pixel. Forming an overflow path connecting a plurality of layers of photodiodes in the depth direction of the semiconductor substrate and an n-type semiconductor region serving as a charge storage region of each photodiode;
Forming a required conductivity type impurity ion implantation region in contact with the overflow path in a depth direction of the semiconductor substrate;
Forming a groove extending in the depth direction of the semiconductor substrate in the impurity ion implantation region;
A method of manufacturing a solid-state imaging device, comprising: forming a gate insulating film on an inner wall surface of the groove and forming a transfer gate electrode of a vertical transfer transistor so as to be embedded in the groove. The method for manufacturing a solid-state imaging device according to claim 8, wherein the vertical transfer transistor is formed at a pixel end. The sidewalls formed at a portion protruding on the surface of the semiconductor substrate of the transfer gate electrode in a self-aligned mask, claim 8, further comprising a step of forming a floating diffusion region of the semiconductor region of n-type to the semiconductor substrate Manufacturing method of solid-state imaging device. Forming a required conductivity type impurity ion implantation region in the depth direction of the semiconductor substrate;
Forming a groove extending in the depth direction of the semiconductor substrate in the impurity ion implantation region;
Forming a plurality of photodiodes in the depth direction of the semiconductor substrate and an n-type semiconductor region serving as a charge storage region of each photodiode to form an overflow path in contact with the impurity ion implantation region;
A method of manufacturing a solid-state imaging device, comprising: forming a gate insulating film on an inner wall surface of the groove and forming a transfer gate electrode of a vertical transfer transistor so as to be embedded in the groove. The method for manufacturing a solid-state imaging device according to claim 11, wherein the vertical transfer transistor is formed at a pixel end. The sidewalls formed at a portion protruding on the surface of the semiconductor substrate of the transfer gate electrode in a self-aligned mask, according to claim 11, comprising the step of forming a floating diffusion region of the semiconductor region of n-type to the semiconductor substrate Manufacturing method of solid-state imaging device. An optical lens,
A solid-state imaging device;
A signal processing circuit for processing an output signal of the solid-state imaging device;
The solid-state imaging device
A photodiode serving as a multi-layer photoelectric conversion element formed in the depth direction of the semiconductor substrate; a vertical transfer transistor having a channel direction perpendicular to the semiconductor substrate;
An impurity ion implantation region formed around a transfer gate portion of the vertical transfer transistor;
An overflow path that connects n-type semiconductor regions that serve as charge storage regions of the plurality of layers of photodiodes ;
An electronic device in which the overflow path also serves as a channel region . The solid in the imaging device, prior Symbol electronic device of claim 14 further comprising a floating diffusion region of n-type semiconductor region in the semiconductor substrate surface. The electronic device according to claim 14 , wherein in the solid-state imaging device, the vertical transfer transistor is disposed at a pixel end.

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