JP2012175067A - Image pickup device, and manufacturing method therefor, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image pickup device with superior pixel performance.SOLUTION: A solid state image pickup device 21A comprises: a semiconductor substrate 22 that is constituted by a semiconductor and has a front surface and a back surface that face away from each other, a gate insulating film 25A deposited in a trench formed on the semiconductor substrate 22 so as to penetrate through the front surface and the back surface, and a gate electrode 26A buried in the trench via the gate insulating film 25 so as to be exposed on the back surface of the semiconductor substrate 22. The gate insulating film 25A and the gate electrode 26A are formed so as to protrude from the back surface, thereby providing an unevenness between a face of the back surface side of the semiconductor substrate 22 and an apical face of the back surface side of the gate electrode 26A. For example, the invention can be applied to an electronic device having an imaging function.

Description

  The present invention relates to an imaging device, a manufacturing method, and an electronic device, and more particularly, to an imaging device, a manufacturing method, and an electronic device that can have better pixel characteristics.

  Conventionally, in an amplification type solid-state imaging device typified by a CMOS (Complementary Metal Oxide Semiconductor) image sensor, charges are transferred to the vicinity of the surface from a photoelectric conversion device (photodiode) located deep from the surface of the semiconductor substrate.

  For example, Patent Document 1 proposes using a vertical transistor as one of methods for transferring charges. A vertical transistor is formed by forming a trench (vertical hole) from the semiconductor substrate surface side by dry etching, forming a gate insulating film, and then embedding a gate electrode.

  Patent Document 2 discloses that by using a vertical transistor, photoelectrically converted charges can be efficiently pumped from a photodiode at a deep position and transferred to a floating diffusion. .

  Further, by using a vertical transistor, the area of the pixel size can be reduced as compared with a structure in which a well having the same conductivity type as that of the photodiode disclosed in Patent Document 3 is used as a transfer path. . In particular, in a vertical spectral imaging device, it is necessary to pump out and transfer charges from a photodiode located at a deep position. Therefore, in order to realize a vertical spectral imaging device with a small pixel, application of a vertical transistor structure is effective. is there.

  The structure of a conventional vertical transistor will be described with reference to FIG. FIG. 1 is a cross-sectional view illustrating a configuration example of a solid-state imaging device in which a vertical transistor is formed. The upper side of FIG. 1 is the front side of the solid-state imaging device, and the lower side of FIG. It is said.

  As shown in FIG. 1A, in the solid-state imaging device 11, a PD (Photodiode) 13 is disposed deep in the semiconductor substrate 12, and an FD (Floating diffusion) 14 is provided on the surface side of the semiconductor substrate 12. Is arranged. A gate insulating film 15 is formed on the surface of the semiconductor substrate 12 and a trench formed from the surface side of the semiconductor substrate 12, and a gate electrode 16 is embedded in the trench. An antireflection film 17 and an oxide film 18 are stacked on the back side of the semiconductor substrate 12.

  In such a solid-state imaging device 11, the vertical transistor 19 is configured with a structure in which, by applying a voltage to the gate electrode 16, charges accumulated in the PD 13 by photoelectric conversion are transferred to the FD 14.

  By the way, in the manufacturing process of the vertical transistor 19, it is difficult to control the depth of the trench when forming the trench in the semiconductor substrate 12, and the depth of the trench may vary from pixel to pixel. As a result, as shown in FIG. 1B, the distance between the gate electrode 16 constituting the vertical transistor 19 and the back surface of the semiconductor substrate 12 varies, and this variation may adversely affect the pixel characteristics.

  That is, the variation in the distance between the vertical transistor 19 and the back surface of the semiconductor substrate 12 is caused by the variation in depth control in the dry etching process when the vertical transistor 19 is processed and the variation in the film thickness of the semiconductor substrate 12 itself. . Furthermore, the film thickness variation of the semiconductor substrate 12 is emphasized in the semiconductor substrate thinning process in the back-illuminated semiconductor manufacturing process. Further, the variation in the distance between the vertical transistor 19 and the back surface of the semiconductor substrate 12 can be said to be a variation in the distance between the PD 13 located deep from the front surface side of the semiconductor substrate 12 and the bottom of the vertical transistor 19 or the amount of covering. . Since the distance between the PD 13 and the bottom of the vertical transistor 19 greatly affects the transfer efficiency of photoelectrically converted charges, it is necessary to suppress variations as much as possible.

  For this reason, in a back-illuminated imaging device that irradiates light from the back surface of the semiconductor substrate 12, a through vertical transistor structure that is a structure in which the gate transistor 16 is penetrated to the back surface of the semiconductor substrate 12 to constitute the vertical transistor 19. It is useful to adopt.

  Next, the through vertical transistor structure will be described with reference to FIG. FIG. 2 is a cross-sectional view illustrating a configuration example of a solid-state imaging device having a penetrating vertical transistor structure. The upper side of FIG. 2 is the front side of the solid-state imaging device, and the lower side of FIG. Is done.

  As shown in FIG. 2A, in a solid-state imaging device 11 ′ having a through vertical transistor structure, a through vertical transistor 19 ′ is formed by embedding a gate electrode 16 ′ in a trench formed so as to penetrate to the back surface of the semiconductor substrate 12. Is configured. With this configuration, in the through vertical transistor 19 ′, the depth of the gate electrode 16 ′ is the same for each pixel, and the above-described variation is eliminated.

  However, in the solid-state imaging device 11 ′, since the trench penetrates, the gate insulating film 15 ′ is not formed on the distal end side of the gate electrode 16 ′, and the distal end surface of the gate electrode 16 ′ is the antireflection film 17. It becomes the structure which contacts. As a result, as shown in FIG. 2B, in the solid-state imaging device 11 ′ having the through vertical transistor structure, the semiconductor substrate 12 and the gate electrode 16 ′ are disposed at the tip portion of the through vertical transistor 19 ′ via the antireflection film 17. Current (gate leakage current) may flow between the two.

  In particular, as shown in FIG. 2C, in the manufacturing process, the gate insulating film 15 ′ at the front end portion of the through-type vertical transistor 19 ′ recedes and is sandwiched between the semiconductor substrate 12 and the gate electrode 16 ′. An antireflection film 17 may be formed on the back side of the substrate 12. In this case, a gate leakage current is more likely to flow between the semiconductor substrate 12 and the gate electrode 16 '. Similarly, when the oxide film 18 is formed between the semiconductor substrate 12 and the gate electrode 16 ′, the gate leakage current easily flows.

  The generation of such a gate leakage current is caused by poor film quality of the antireflection film 17 and the oxide film 18 formed on the back side. That is, the material deposited on the back side is rate-determined by the heat resistance temperature of the adhesive on the metal wiring layer and the wafer bonding surface and cannot be deposited at a high temperature. Compared with, current flows easily. As a result, when an antireflection film 17 or an oxide film 18 is formed in or near a region where an electric field is applied between the semiconductor substrate 12 and the gate electrode 16 ′, a gate leak occurs between the semiconductor substrate 12 and the gate electrode 16 ′. An electric current will be generated.

JP 2008-258316 A JP 2010-114274 A JP 2006-278466 A

  As described above, in the configuration of the conventional through vertical transistor, a gate leakage current is generated between the semiconductor substrate and the gate electrode. As a result, a large amount of carriers are generated at the tip of the through-type vertical transistor, and the carrier characteristics flow into the photodiode during charge accumulation or charge transfer, resulting in white dots or dark current, resulting in poor pixel characteristics. There was something to do.

  The present invention has been made in view of such a situation, and makes it possible to provide better pixel characteristics.

  A solid-state imaging device according to one aspect of the present invention is configured by a semiconductor and has a substrate having first and second surfaces facing opposite sides, and the first surface and the second surface. A gate insulating film formed in a trench formed for the substrate, and a gate electrode embedded in the trench through the gate insulating film so as to be exposed on the second surface side of the substrate And a step is formed between the second surface of the substrate and the tip surface of the gate electrode on the second surface side.

  According to another aspect of the invention, there is provided an electronic apparatus that includes a semiconductor and includes a substrate having first and second surfaces facing opposite sides, and the first surface and the second surface. A gate insulating film formed in a trench formed with respect to the substrate; and a gate electrode embedded in the trench through the gate insulating film so as to be exposed on the second surface side of the substrate; And a solid-state imaging device in which a step is formed from the second surface of the substrate to a tip surface on the second surface side of the gate electrode.

  According to another aspect of the present invention, there is provided a method of manufacturing a solid-state imaging device, which is formed of a semiconductor and penetrates the first surface and the second surface of a substrate having first and second surfaces facing opposite to each other. A gate insulating film is formed in the trench formed with respect to the substrate, and a gate electrode is exposed to the second surface side of the substrate in the trench through the gate insulating film. Embedding and forming a step between the second surface of the substrate and the tip surface of the gate electrode on the second surface side.

  In one aspect of the present invention, the semiconductor substrate is formed with respect to the substrate so as to penetrate the first surface and the second surface of the substrate having first and second surfaces facing each other. A gate insulating film is formed in the trench. A gate electrode is embedded in the trench through the gate insulating film so as to be exposed on the second surface side of the substrate. A step is formed between the second surface of the substrate and the tip surface on the second surface side of the gate electrode.

  According to one aspect of the present invention, better pixel characteristics can be provided.

It is sectional drawing which shows the structure of the conventional vertical transistor. It is sectional drawing which shows the structure of the conventional penetration vertical transistor structure. It is sectional drawing which shows the structural example of embodiment of the solid-state image sensor to which this invention is applied. It is a figure which shows the modification of the solid-state image sensor provided with the penetration vertical transistor. It is a figure which shows the modification of the solid-state image sensor provided with the penetration vertical transistor. It is a figure explaining the manufacturing process of a solid-state image sensor. It is a figure explaining the other manufacturing process of a solid-state image sensor. It is a figure which shows the modification of the solid-state image sensor provided with the penetration vertical transistor. It is a figure explaining the modification of the solid-state image sensor provided with the penetration vertical transistor, and its manufacturing process. It is a block diagram which shows the structural example of the imaging device mounted in an electronic device.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.

  FIG. 3 is a cross-sectional view showing a configuration example of the first to third embodiments of the solid-state imaging device to which the present invention is applied.

  3A shows a solid-state imaging device 21A according to the first embodiment, FIG. 3B shows a solid-state imaging device 21B according to the second embodiment, and FIG. The solid-state image sensor 21C which is 3rd Embodiment is shown. Also, the upper side of FIG. 3 is the front side of the solid-state image sensor, and the lower side of FIG. 3 is the back side of the solid-state image sensor.

  As shown in FIG. 3A, the solid-state imaging device 21A includes a semiconductor substrate 22, a PD 23, an FD 24, a gate insulating film 25A, a gate electrode 26A, an antireflection film 27A, and an oxide film 28A. Further, in the solid-state imaging device 21A, the through vertical transistor 29A is configured in such a structure that charges accumulated in the PD 23 by photoelectric conversion are transferred to the FD 24 by applying a voltage to the gate electrode 26A.

  In the solid-state imaging device 21A, the semiconductor substrate 22 is, for example, a thin silicon substrate made of a semiconductor. In FIG. 3, the upper side is the surface side (first surface side) of the semiconductor substrate 22, The lower side is the back surface side (second surface side) of the semiconductor substrate 22. The PD 23 is provided for each of a plurality of pixels arranged along the surface direction of the solid-state image sensor 21A, is disposed at a deep position when viewed from the front surface side of the semiconductor substrate 22, and is irradiated from the back surface side of the solid-state image sensor 21A. Photoelectric conversion is performed by light. The FD 24 is formed on the front surface side of the semiconductor substrate 22, and charges accumulated by photoelectric conversion by the PD 23 are transferred to the FD 24.

  The gate insulating film 25A is a film for insulating between the semiconductor substrate 22 and the gate electrode 26A, and the gate electrode 26A is an electrode for controlling charge transfer from the PD 23 to the FD 24. The antireflection film 27A is a film for reducing the reflection of light applied to the solid-state imaging device 21A and increasing the transmittance of the light into the semiconductor substrate 22, and the oxide film 28A is a semiconductor substrate. 22 is a film for insulating the back side of 22.

  In the solid-state imaging device 21A, unlike the solid-state imaging device 11 ′ shown in FIG. 2, the penetrating vertical transistor 29A is formed so that the gate insulating film 25A and the gate electrode 26A protrude from the back surface side of the semiconductor substrate 22. The front end portion of the back surface side is configured.

  Thus, since the gate insulating film 25A and the gate electrode 26A have a step so that they protrude from the surface on the back surface side of the semiconductor substrate 22, the antireflection film 27A formed on the back surface of the semiconductor substrate 22 It forms into a film so that it may become convex shape with respect to the back surface of 21 A of solid-state image sensors. That is, the antireflection film 27A is formed on the back surface of the semiconductor substrate 22 and the front end surface on the back surface side of the gate insulating film 25A and the gate electrode 26A, and is formed along the outer peripheral surface of the gate insulating film 25A. The

  Therefore, in the solid-state imaging device 21A, the antireflection film 27A is formed along the outer peripheral surface of the gate insulating film 25A rather than the leakage path through which the gate leakage current flows in the solid-state imaging device 11 ′ shown in FIG. Accordingly, the leak path becomes longer. Thereby, in the solid-state imaging device 21A, generation of a leakage current between the semiconductor substrate 22 and the gate electrode 26A can be suppressed.

  Furthermore, as described with reference to FIG. 2C, in the solid-state imaging device 11 ′, when the antireflection film 17 is formed so as to be sandwiched between the semiconductor substrate 12 and the gate electrode 16 ′, a gate leakage current is generated. It was easy to flow. On the other hand, in the solid-state imaging device 21A, the penetrating vertical transistor 29A is configured such that the gate insulating film 25A and the gate electrode 26A protrude from the back surface of the semiconductor substrate 22. With this configuration, in the manufacturing process of the solid-state imaging device 21A, the antireflection film 27A and the like are not sandwiched between the semiconductor substrate 22 and the gate electrode 26A, and the solid-state imaging device 21A more reliably generates the gate leakage current. Can be suppressed.

  As shown in FIG. 3B, the solid-state imaging device 21B includes a semiconductor substrate 22, a PD 23, an FD 24, a gate insulating film 25B, a gate electrode 26B, an antireflection film 27B, and an oxide film 28B. Further, in the solid-state imaging device 21B, the gate electrode 26B penetrates to the back surface side of the semiconductor substrate 22, and a through vertical transistor 29B is configured. In the following description, description of parts common to the solid-state imaging element 21A is omitted.

  In the solid-state imaging device 21B, the tip portion on the back surface side of the through vertical transistor 29B is formed so that the gate insulating film 25B is formed up to the surface on the back surface side of the semiconductor substrate 22, and the gate electrode 26B is the surface on the back surface side of the semiconductor substrate 22. It has the structure which has a level | step difference so that it may become more depressed (dent). That is, in the solid-state imaging device 21B, the gate insulating film 25B is formed so as to extend to the back surface side than the gate electrode 26B.

  With such a configuration, in the solid-state imaging device 21B, the antireflection film 27B formed on the back surface of the semiconductor substrate 22 is formed in a concave shape with respect to the back surface of the solid-state imaging device 21B. That is, the antireflection film 27B is formed on the back surface of the semiconductor substrate 22 and the front end surface on the back surface side of the gate electrode 26B and the front end surface on the back surface side of the gate electrode 26B, and the inner peripheral surface of the gate insulating film 25B. Is formed.

  Therefore, in the solid-state imaging device 21B, the leak path becomes longer according to the amount of the antireflection film 27B formed along the inner peripheral surface of the gate insulating film 25B, similarly to the solid-state imaging device 21A. Thereby, in the solid-state imaging device 21B, generation of a gate leakage current between the semiconductor substrate 22 and the gate electrode 26B can be suppressed. Further, in the manufacturing process of the solid-state imaging device 21B, the antireflection film 27B or the like is not sandwiched between the semiconductor substrate 22 and the gate electrode 26B, and the solid-state imaging device 21B more reliably suppresses the generation of gate leakage current. can do.

  As shown in FIG. 3C, the solid-state imaging device 21C includes a semiconductor substrate 22, PD23, FD24, gate insulating film 25C, gate electrode 26C, antireflection film 27C, and oxide film 28C. Further, in the solid-state imaging device 21C, the gate electrode 26C penetrates to the back surface side of the semiconductor substrate 22, and the through vertical transistor 29C is configured. In the following description, description of parts common to the solid-state imaging element 21A is omitted.

  In the solid-state imaging device 21C, the back end side portion of the through-type vertical transistor 29C has a gate electrode 26C formed up to the surface on the back surface side of the semiconductor substrate 22, and the gate insulating film 25C is a surface on the back surface side of the semiconductor substrate 22. It has the structure which has a level | step difference so that it may protrude more. That is, in the solid-state imaging device 21C, the gate insulating film 25C is formed so as to protrude from the rear surface of the semiconductor substrate 22 and the gate electrode 26C.

  With such a configuration, in the solid-state imaging device 21C, the antireflection film 27C formed on the back surface of the semiconductor substrate 22 is formed so as to have an annular convex shape along the gate insulating film 25C. That is, the antireflection film 27C is formed on the back surface of the semiconductor substrate 22 and the front end surface on the back surface side of the gate electrode 26C and the front end surface on the back surface side of the gate electrode 26C, and the outer peripheral surface of the gate insulating film 25C and A film is formed along the inner peripheral surface.

  Accordingly, in the solid-state image pickup device 21C, the antireflection film 27C is formed along the outer peripheral surface and the inner peripheral surface of the gate insulating film 25C, that is, about twice as much as the solid-state image pickup devices 21A and 21B. The route becomes longer. Thereby, in the solid-state imaging device 21C, generation of a gate leakage current between the semiconductor substrate 22 and the gate electrode 26C can be further suppressed as compared with the solid-state imaging devices 21A and 21B. Further, in the manufacturing process of the solid-state imaging device 21C, the antireflection film 27C or the like is not sandwiched between the semiconductor substrate 22 and the gate electrode 26C, and the solid-state imaging device 21C more reliably suppresses the generation of gate leakage current. can do.

  Furthermore, in the solid-state imaging device 21C, the gate insulating film 25C is formed so as to protrude from the back surface side of the semiconductor substrate 22 and the gate electrode 26C, whereby a voltage is generated between the semiconductor substrate 22 and the gate electrode 26C. Is not applied linearly. That is, in the solid-state imaging device 21C, the antireflection film 27C and the oxide film 28C are formed so that a linear leak path does not occur between the semiconductor substrate 22 and the gate electrode 26C due to the protrusion of the gate insulating film 25C. Has been. Thus, since it is the structure which does not generate | occur | produce a linear leak path | route, generation | occurrence | production of a gate leak current can be suppressed more reliably in solid-state image sensor 21C than solid-state image sensor 21A or 21B. For example, in the solid-state imaging device 21A or 21B, when the gate insulating film 25A or 25B is retracted microscopically, a linear leak path may occur. On the other hand, in the solid-state imaging device 21C, since the gate insulating film 25C protrudes sufficiently, a linear leakage path does not occur, and the generation of the gate leakage current can be reliably suppressed.

  In the following description, the gate insulating films 25A to 25C, the gate electrodes 26A to 26C, the antireflection films 27A to 27C, the oxide films 28A to 28C, and the through vertical transistors 29A to 29C need not be distinguished from each other. The gate insulating film 25, the gate electrode 26, the antireflection film 27, the oxide film 28, and the through vertical transistor 29 are referred to.

  Here, materials constituting the gate insulating film 25, the gate electrode 26, the antireflection film 27, and the oxide film 28 will be described.

  The gate insulating film 25 is a silicon oxide film obtained by thermally oxidizing silicon, silicon oxynitride, or a high dielectric insulating film. As the high dielectric insulating film, hafnium oxide, hafnia silicate, nitrogen-added hafnium aluminate, tantalum oxide, titanium dioxide, zirconium oxide, praseodymium oxide, yttrium oxide, or the like is used.

  The gate electrode 26 is made of a doped silicon material such as PDAS (Phosphorus Doped Amorphous Silicon) or a metal material such as aluminum, tungsten, titanium, cobalt, hafnium, or tantalum.

  The antireflection film 27 is an oxide insulating film such as aluminum, tantalum, hafnium, titanium, or lanthanum, and another insulating film having a negative fixed charge can also be used. For the insulating film having a negative fixed charge, hafnium oxide, tantalum oxide, aluminum oxide, zirconium oxide, or titanium oxide can be used.

  The oxide film 28 is a deposited oxide film such as an HDP (High Density Plasma) oxide film.

  Next, with reference to FIG. 4 and FIG. 5, a modified example of the solid-state imaging device including the through vertical transistor 29 will be described. 4 and 5, the plan view of the solid-state imaging device is shown on the upper side, and the cross-sectional view taken along the alternate long and short dash line shown in the plan view is shown on the lower side. 4 and 5, the FD 24, the gate insulating film 25, the antireflection film 27, and the oxide film 28 are not shown.

  FIG. 4A shows a solid-state imaging device 21-1 as a first modification. In the solid-state imaging device 21-1, the gate electrode 26-1 is formed in a cylindrical shape.

  FIG. 4B shows a solid-state imaging device 21-2 as a second modification. In the solid-state imaging device 21-2, the gate electrode 26-2 is formed in an elongated prismatic shape along one side of the PD 23. That is, in the solid-state imaging device 21-2, the gate electrode 26-2 is formed so that the transfer gate area when transferring charges from the PD 23 is widened. Thereby, the charge transfer efficiency can be improved.

  FIG. 4C shows a solid-state imaging device 21-3 as a third modification. In the solid-state imaging device 21-3, the gate electrode 26-3 is formed in a square shape as viewed in plan so as to surround the outer periphery of the PD 23. That is, the PD 23 is provided for each pixel, and the solid-state imaging device 21-3 has a function of separating the pixels by forming the gate electrode 26-3 so as to surround the PD 23. Furthermore, in the solid-state imaging device 21-3, since the transfer gate area when transferring charges from the PD 23 is widened, charge transfer efficiency can be improved.

  FIG. 5A shows a solid-state imaging device 21-4 as a fourth modification. In the solid-state imaging device 21-4, the two PDs 23a and 23b are disposed in the semiconductor substrate 22 at different depths. In the solid-state imaging device 21-4, a gate electrode 26-4a constituting the through vertical transistor 29-4a that transfers the charge of the PD 23a and a through vertical transistor 29-4b that transfers the charge of the PD 23b are formed. A gate electrode 26-4b is provided.

  FIG. 5B shows a solid-state imaging device 21-5 that is a fifth modification. In the solid-state imaging device 21-5, the two PDs 23a and 23b are arranged in the semiconductor substrate 22 at different depths. In the solid-state imaging device 21-5, the gate electrode 26-5a constituting the vertical transistor 29-5a for transferring the charge of the PD 23a and the gate constituting the through vertical transistor 29-5b for transferring the charge of the PD 23b. An electrode 26-5b is provided.

  As described above, in the solid-state imaging device 21, a plurality of (two in the example of FIG. 5) PDs 23 have a depth corresponding to the wavelength dependency of the light absorption coefficient of light incident on the semiconductor substrate 22 in a single pixel. Can be arranged. A plurality of through vertical transistors 29 are provided corresponding to the respective PDs 23.

  At this time, it is only necessary that at least a part of the plurality of through vertical transistors 29 protrude from the rear surface of the semiconductor substrate 22 as described with reference to FIG. That is, in the solid-state imaging device 21-4 of FIG. 5A, the tip portions of both the penetrating vertical transistors 29-4a and 29-4b protrude from the back surface of the semiconductor substrate 22. On the other hand, in the solid-state imaging device 21-5 of FIG. 5B, only the tip portion of the through vertical transistor 29-5a protrudes from the back surface of the semiconductor substrate 22. As described above, in the solid-state imaging device 21, the depth of the through vertical transistor 29 can be appropriately adjusted according to the configuration of the PD 23 and the like.

  In the modification of the solid-state imaging device 21 shown in FIGS. 4 and 5, the gate electrode 26 protrudes from the surface on the back side of the semiconductor substrate 22, that is, the through vertical transistor 29A shown in FIG. 3A. Although the structure is shown, it is not limited to this. That is, the structure of the penetrating vertical transistor 29B or 29C can be applied to each modification of the solid-state imaging device 21.

  Next, a manufacturing process of the solid-state imaging device 21 will be described with reference to FIG.

  In the first step, a trench for forming the through vertical transistor 29 is formed in the first conductivity type, for example, a p-type semiconductor substrate 22. Although not shown, the PD 23 is formed before the step of forming the trench in the semiconductor substrate 22. The PD 23 has a second conductivity type n-type semiconductor region and a first conductivity type p-type semiconductor region at a depth corresponding to the wavelength dependence of the light absorption coefficient of light incident on the semiconductor substrate 22. The plurality of layers are alternately stacked by an ion implantation method. Each pixel is separated by a semiconductor substrate 22 having the first conductivity type.

  In the second step, the gate insulating film 25 is formed on the surface of the semiconductor substrate 22 and inside the trench formed in the first step. For example, the gate insulating film 25 is a silicon oxide film obtained by thermally oxidizing silicon, silicon oxynitride, or a high dielectric insulating film. Examples of the high dielectric insulating film include hafnium oxide, hafnia silicate, nitrogen-added hafnium aluminate, tantalum oxide, titanium dioxide, zirconium oxide, praseodymium oxide, and yttrium oxide.

  In the third step, a material that becomes the gate electrode 26 is buried in the trench through the gate insulating film 25. Here, as a material for the gate electrode 26, a doped silicon material such as PDAS (Phosphorus Doped Amorphous Silicon) or a metal material such as aluminum, tungsten, titanium, cobalt, hafnium, or tantalum is used.

  In the fourth step, a resist mask (not shown) corresponding to a region for forming the gate electrode 26 is formed, and the gate electrode 26 is processed by anisotropic etching using this resist as a mask. Thereafter, annealing is performed in a chlorine atmosphere in order to terminate the interface state between the gate electrode 26 and the semiconductor substrate 22.

  In the fifth step, an oxide film, a nitride film, or the like is deposited on the surface of the semiconductor substrate 22, and isotropic etching is performed thereafter, whereby the sidewall 30 is formed. Note that after the formation of the sidewalls 30, a plurality of wiring layers (not shown) with an interlayer insulating film are formed on the surface side of the semiconductor substrate 22 in the same manner as in a normal solid-state imaging device. Further, a semiconductor substrate (not shown) that supports the semiconductor substrate 22 is bonded to the uppermost layer on the surface side of the semiconductor substrate 22.

  In the sixth step, for example, by polishing the back surface side of the semiconductor substrate 22, the front end portion of the back surface side of the gate electrode 26 has a desired film thickness that is exposed on the back surface side of the semiconductor substrate 22. Thin film processing is performed. For example, the thickness of the semiconductor substrate 22 is about 0.1 μm to 100 μm, more preferably about 1 μm to 10 μm.

  In the seventh step, a solution for etching back the semiconductor substrate 22 and the gate electrode 26, for example, an SC1 solution that is an aqueous solution of ammonium hydroxide and hydrogen peroxide solution, and the gate electrode The front end surface of the back surface side of 26 is retracted. Thus, the gate insulating film 25 protrudes because the surface on the back surface side of the semiconductor substrate 22 and the front end surface on the back surface side of the gate electrode 26 recede. Here, the gate insulating film 25 protrudes from about 0.1 nm to about 300 nm, for example. Note that the process of projecting the gate insulating film 25 may be performed by CMP (Chemical Mechanical Polishing).

  In the eighth step, an antireflection film 27 is deposited on the back side of the semiconductor substrate 22. Further, after the antireflection film 27 is formed, an oxide film 28 (FIG. 3) is deposited. The antireflection film 27 is an oxide insulating film such as aluminum, tantalum, hafnium, titanium, or lanthanum. The antireflection film 27 can be an insulating film having other negative fixed charges. For the insulating film having a negative fixed charge, hafnium oxide, tantalum oxide, aluminum oxide, zirconium oxide, or titanium oxide can be used. The antireflection film 27 may be formed by, for example, ALD (Atomic Layer Deposition) and then thickened by HDP (High Density Plasma).

  Further, after the eighth step, a light shielding film (not shown) is deposited in a region where light is not irradiated inside the semiconductor substrate 22. The light shielding film is formed of, for example, tungsten, titanium, aluminum, or the like. Further, a planarizing film, a color filter, and an on-chip microlens (each not shown) are sequentially formed.

  Through such a manufacturing process, the through vertical transistor 29C having a structure in which the gate insulating film 25C is formed so as to protrude from the back surface of the semiconductor substrate 22 as shown in FIG. 3C can be formed.

  Next, another manufacturing process of the solid-state imaging device 21 will be described with reference to FIG. This manufacturing process is different from the manufacturing process described with reference to FIG. 6 in that an SOI (Silicon On Insulator) substrate is used as the semiconductor substrate 22.

  In the first step, a trench for forming the through vertical transistor 29 is formed in the first conductivity type, for example, a p-type semiconductor substrate 22. At this time, the trench is processed so as to reach the BOX layer 31 of the SOI substrate. Note that when the mask formed on the surface of the semiconductor substrate 22 is removed in order to form the trench, a part of the BOX layer 31 existing on the front end side of the trench recedes. Thereby, as shown in FIG. 7, a space is formed in a part of the BOX layer 31 on the tip side of the trench.

  Although not shown, the PD 23 is formed before the step of forming the trench in the semiconductor substrate 22. The PD 23 has a second conductivity type n-type semiconductor region and a first conductivity type p-type semiconductor region at a depth corresponding to the wavelength dependence of the light absorption coefficient of light incident on the semiconductor substrate 22. The plurality of layers are alternately stacked by an ion implantation method. Each pixel is separated by a semiconductor substrate 22 having the first conductivity type.

  Thereafter, the second to fifth steps are performed. The second to fifth steps are the same as the second to fifth steps described with reference to FIG.

  In the sixth step, thin film processing is performed on the semiconductor substrate 22. This thin film processing is performed by removing the semiconductor substrate on the back side (lower side in FIG. 7) of the BOX layer 31 of the semiconductor substrate 22 by polishing and then removing the BOX layer 31 by wet etching or dry etching. Is called. Note that CMP (Chemical Mechanical Polishing) may be used to remove the BOX layer 31, or a combination of these processing methods may be used.

  Thereafter, the seventh and eighth steps are performed. The seventh and eighth steps are the same as the seventh and eighth steps described with reference to FIG.

  The solid-state imaging device 21 having the through vertical transistor 29 is manufactured through the processes as described above. Then, a step is formed between the back surface side surface of the semiconductor substrate 22 and the back surface side tip surface of the gate electrode 26 at the front end portion of the through vertical transistor 29. That is, in the configuration of the solid-state imaging device 21A of FIG. 3A, a step is formed by the gate insulating film 25A and the gate electrode 26A projecting from the rear surface of the semiconductor substrate 22. 3B, the gate insulating film 25B is formed up to the surface on the back surface side of the semiconductor substrate 22, and the gate electrode 26B is formed to be recessed from the surface on the back surface side of the semiconductor substrate 22. As a result, a step is formed. 3C, the gate electrode 26C is formed to the surface on the back surface side of the semiconductor substrate 22, and the gate insulating film 25C protrudes from the surface on the back surface side of the semiconductor substrate 22. As a result, a step is formed.

  By forming such a step, there is a gap between the region where the electric field between the semiconductor substrate 22 and the gate electrode 26 is strong and the film formed in the back surface process such as the antireflection film 27 and the oxide film 28. An interval corresponding to the step is provided. Further, in this manufacturing process, it is avoided that the antireflection film 27 and the like are sandwiched between the semiconductor substrate 22 and the gate electrode 26. Therefore, in the solid-state imaging device 21, the generation of the gate leak current can be suppressed.

  In addition, the solid-state imaging device 21 to which the through vertical transistor 29 having such a configuration is applied does not generate a white spot or a dark current due to a gate leakage current, and can obtain stable pixel characteristics. Further, the margin for process variation is improved, and variations in characteristics between pixels do not occur. Therefore, the solid-state image sensor 21 can obtain a better image.

  FIG. 8 shows a solid-state imaging device 21-6 that is a sixth modification.

  In the solid-state imaging device 21-6, the gate insulating film 25-6 is formed so as to protrude from the back surface of the semiconductor substrate 22 and the gate electrode 26-6. In the solid-state imaging device 21-6, the metal material 32 and the gate electrode 26-6 disposed on the back side of the semiconductor substrate 22 are secured while ensuring the insulation between the semiconductor substrate 22 and the gate electrode 26-6. Connected.

  The metal material 32 is a wiring electrically connected to the gate electrode 26-6, and a voltage is applied to the metal material 32 through the gate electrode 26-6, or the gate electrode 26-6 through the metal material 32. A voltage is applied to For example, in the solid-state imaging device 21-6, a configuration in which different materials and structures are further laminated on the back surface side of the metal material 32 is assumed. Specifically, in a configuration in which a structure in which an upper transparent electrode and a lower transparent electrode are arranged so as to sandwich a photoelectric conversion film is laminated on the back side of the metal material 32, the gate electrode 26-6 and the metal material 32 are interposed. Thus, by applying a voltage to the upper transparent electrode and fixing the voltage of the lower transparent electrode, the charges generated in the photoelectric conversion film are transferred to the substrate.

  Further, the metal material 32 is formed so as to open corresponding to the PD 23, and also has a function as a light shielding film that shields a region where the semiconductor substrate 22 is not irradiated with light. The metal material 32 is made of aluminum, tungsten, titanium, cobalt, hafnium, tantalum, various silicide materials, or the like.

  If light shielding is not necessary, a transmissive conductive film (not shown) may be employed as the wiring electrically connected to the gate electrode 26-6 instead of the metal material 32. Good. This transparent conductive film is made of ITO (Indium-tin-oxide), ZnO, In2O3, SnO2, graphene, or the like.

  FIG. 9 shows a solid-state imaging device 21-7 as a seventh modification and a part of the manufacturing process.

  The solid-state imaging device 21-7 is manufactured by the SOI substrate described in the manufacturing process of FIG. As described with reference to FIG. 7, the first to fifth steps are performed, and the gate electrode 26-7 is embedded in the trench formed in the semiconductor substrate 22 as shown on the left side of FIG. 9. It is. At this time, as described above, a space is formed in a part of the BOX layer 31 on the front end side of the trench, and the front end portion 26-7A of the gate electrode 26-7 is filled in the space.

  When performing thin film processing from such a state, the BOX layer 31 is formed so that the tip end portion 26-7A is not deleted and the tip end portion 26-7A remains without being deleted at the tip of the back side of the gate electrode 26-7. Removed. At this time, the BOX layer 31 is removed so that the flange portion 25-7A is also formed at the tip on the back surface side of the gate insulating film 25-7.

  Then, an antireflection film 27-7 is formed on the back side of the semiconductor substrate 22, and an oxide film 28-7 is formed. Thereafter, a through hole is formed in the antireflection film 27-7 and the oxide film 28-7 so as to penetrate to the gate electrode 26-7, and is connected to the tip portion 26-7A of the gate electrode 26-7. 32 is disposed.

  Thus, by using the tip portion 26-7A formed on the gate electrode 26-7, the area of the tip portion 26-7A is larger than the area of the gate electrode 26-7 when viewed from the back side. Wiring work when connecting the metal material 32 can be easily performed.

  The solid-state imaging device 21 as described above is used in various electronic devices such as an imaging system such as a digital still camera or a digital video camera, a mobile phone having an imaging function, or other devices having an imaging function. Can be applied.

  FIG. 10 is a block diagram illustrating a configuration example of an imaging device mounted on an electronic device.

  As shown in FIG. 10, the imaging device 101 includes an optical system 102, a shutter device 103, an imaging device 104, a drive circuit 105, a signal processing circuit 106, a monitor 107, and a memory 108, and a still image and a moving image. Can be imaged.

  The optical system 102 includes one or more lenses, guides image light (incident light) from a subject to the image sensor 104, and forms an image on a light receiving surface (sensor unit) of the image sensor 104.

  The shutter device 103 is disposed between the optical system 102 and the image sensor 104, and controls a light irradiation period and a light shielding period for the image sensor 104 according to the control of the drive circuit 105.

  As the imaging device 104, any of the solid-state imaging device 21 according to the embodiment and the modification described above is applied. In the imaging element 104, signal charges are accumulated for a certain period according to an image formed on the light receiving surface via the optical system 102 and the shutter device 103. The signal charge accumulated in the image sensor 104 is transferred in accordance with a drive signal (timing signal) supplied from the drive circuit 105.

  The drive circuit 105 outputs a drive signal for controlling the transfer operation of the image sensor 104 and the shutter operation of the shutter device 103 to drive the image sensor 104 and the shutter device 103.

  The signal processing circuit 106 performs various types of signal processing on the signal charges output from the image sensor 104. An image (image data) obtained by performing signal processing by the signal processing circuit 106 is supplied to the monitor 107 and displayed, or supplied to the memory 108 and stored (recorded).

  In the imaging apparatus 101 configured as described above, the image quality can be improved by applying the solid-state imaging element 21 having good pixel characteristics as described above as the imaging element 104.

  In the above-described embodiment, a configuration example in which a back-illuminated CMOS solid-state image sensor is employed as the solid-state image sensor 21 is shown. However, the structure of the solid-state image sensor 21 is a front-illuminated CMOS type. The present invention can be applied to a solid-state image sensor, a CCD solid-state image sensor, and the like.

  The embodiments of the present invention are not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

  21 Solid-state imaging device, 22 Semiconductor substrate, 23 PD, 24 FD, 25 Gate insulating film, 26 Gate electrode, 27 Antireflection film, 28 Oxide film, 29 Through vertical transistor, 30 Side wall, 31 BOX layer, 32 Metal material , 101 imaging device, 102 optical system, 103 shutter device, 104 imaging device, 105 drive circuit, 106 signal processing circuit, 107 monitor, 108 memory

Claims (15)

A substrate made of a semiconductor and having first and second surfaces facing away from each other;
A gate insulating film formed in a trench formed in the substrate so as to penetrate the first surface and the second surface;
A gate electrode embedded in the trench through the gate insulating film so as to be exposed on the second surface side of the substrate;
A step is formed between the second surface of the substrate and a tip surface of the gate electrode on the second surface side. 2. The solid-state imaging device according to claim 1, wherein the step is configured by projecting a front end surface on the second surface side of the gate electrode and the gate insulating film from the second surface of the substrate. 2. The solid-state imaging device according to claim 1, wherein the step is formed by a tip surface on the second surface side of the gate electrode being recessed from the second surface of the substrate. 2. The solid-state imaging device according to claim 1, wherein the step is configured by the gate insulating film projecting from the second surface of the substrate and a tip surface of the gate electrode on the second surface side. . A photodiode provided for each of a plurality of pixels arranged in a surface direction along the first or second surface;
The solid-state imaging device according to claim 1, wherein the gate electrode is formed so as to surround the photodiode for each of the plurality of pixels. A plurality of pixel units arranged in a plane direction along the first or second surface, further comprising photodiodes arranged at a plurality of locations having different depths in the substrate;
The solid-state imaging device according to claim 1, wherein the gate electrode is provided for each of the photodiodes, and at least one of the gate electrodes has a configuration in which the step is formed. The solid-state imaging device according to claim 1, further comprising: a wiring arranged on the second surface side of the substrate and connected to the gate electrode. The solid-state imaging device according to claim 1, further comprising an antireflection film in contact with the substrate on the second surface of the substrate. The solid-state imaging device according to claim 8, wherein the antireflection film is an oxide insulating film of silicon, aluminum, hafnium, tantalum, titanium, or lanthanum. The solid-state imaging device according to claim 1, wherein the gate insulating film is a silicon oxide film or silicon oxynitride. The solid-state imaging device according to claim 1, wherein the gate electrode is PDAS (Phosphorus Doped Amorphous Silicon), aluminum, tungsten, titanium, cobalt, hafnium, or tantalum. The solid-state imaging device according to claim 7, wherein the wiring is a metal material including aluminum, tungsten, titanium, cobalt, hafnium, tantalum, or a silicide material. The solid-state imaging device according to claim 7, wherein the wiring is ITO (Indium-tin-oxide), ZnO, In 2 O 3, SnO 2, or a conductive film including graphene and having transparency. A substrate made of a semiconductor and having first and second surfaces facing away from each other;
A gate insulating film formed in a trench formed in the substrate so as to penetrate the first surface and the second surface;
A gate electrode embedded in the trench through the gate insulating film so as to be exposed on the second surface side of the substrate, and from the second surface of the substrate, the gate electrode An electronic apparatus comprising: a solid-state imaging device in which a step is formed between the second surface side and the front end surface. A gate is formed in a trench formed with respect to the substrate so as to penetrate the first surface and the second surface of the substrate made of a semiconductor and having first and second surfaces facing opposite to each other. Insulating film is formed,
A gate electrode is embedded in the trench through the gate insulating film so as to be exposed on the second surface side of the substrate,
A method of manufacturing a solid-state imaging device, including a step of forming a step between the second surface of the substrate and a tip surface on the second surface side of the gate electrode.

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