CN105826331B

CN105826331B - Method for manufacturing back side illumination type image sensor adopting back side deep groove isolation

Info

Publication number: CN105826331B
Application number: CN201510000564.XA
Authority: CN
Inventors: 赵立新; 王永刚; 李�杰
Original assignee: Geke Microelectronics Shanghai Co Ltd
Current assignee: Geke Microelectronics Shanghai Co Ltd
Priority date: 2015-01-04
Filing date: 2015-01-04
Publication date: 2020-06-02
Anticipated expiration: 2035-01-04
Also published as: CN105826331A

Abstract

The invention provides a method for manufacturing a back-side illuminated image sensor with back deep groove isolation, wherein a device wafer, a first bearing wafer and a second bearing wafer are provided; repairing the defects of the deep trench isolation structure through a thermal process in a subsequent process; carrying out first wafer bonding on the first surface of the device wafer and the first bearing wafer, thinning the device wafer to form a second surface of the device wafer, and manufacturing a device and metal interconnection on the surface; and carrying out wafer bonding for the second time with the second bearing wafer to form the back-illuminated image sensor with the back deep trench isolation structure. In the back-illuminated deep trench isolation, a deep trench isolation structure is formed firstly, and defects generated in the deep trench isolation forming process can be repaired by adopting a high-temperature thermal process in the subsequent process, so that dark current and white spots are reduced, and the level of no deep trench isolation can be achieved.

Description

Method for manufacturing back side illumination type image sensor adopting back side deep groove isolation

Technical Field

The invention relates to the field of image sensors, in particular to a back-illuminated image sensor adopting back deep groove isolation.

Background

An image sensor is a semiconductor device that converts an optical signal into an electrical signal, and has a photoelectric conversion element.

Image sensors can be further classified into Complementary Metal Oxide (CMOS) image sensors and Charge Coupled Device (CCD) image sensors. The CCD image sensor has advantages of high image sensitivity and low noise, but the integration of the CCD image sensor with other devices is difficult and the power consumption of the CCD image sensor is high. In contrast, the CMOS image sensor has the advantages of simple process, easy integration with other devices, small volume, light weight, low power consumption, low cost, and the like. Therefore, as the technology is developed, CMOS image sensors are increasingly used in various electronic products instead of CCD image sensors. At present, CMOS image sensors are widely used in still digital cameras, camera phones, digital video cameras, medical imaging devices (e.g., gastroscopes), vehicle imaging devices, and the like.

The existing CMOS image sensor respectively adopts a front-illuminated type (FSI) and a back-illuminated type (BSI), wherein the BSI can effectively prevent Crosstalk (Crosstalk) caused by light entering because a plurality of layers such as metal layers are positioned on the back of the light entering direction, and provides incident light flux, so that the CMOS image sensor is widely applied to the field of medium and high pixel image sensors at present; in the process of manufacturing the BSI, the pixel units arranged in the array of the pixel region need to be physically and electrically isolated by the trench, and in the prior art, a method of firstly manufacturing an image sensor device and then manufacturing the deep trench isolation is often adopted, but the method can cause the defect of the deep trench isolation to be difficult to remove, and if the method is adopted for removing by a high-temperature thermal oxidation process, the function of the image sensor device can be damaged due to the fact that the heating temperature is often higher than 800 ℃, and the image sensor can fail. In addition, in the BSI method, it is also a subject widely sought in the industry to improve carrier transfer efficiency, prevent dark current, and improve signal-to-noise ratio.

Disclosure of Invention

The invention provides a method for manufacturing a back-side illuminated image sensor by adopting back deep groove isolation, which at least comprises the following steps:

providing a device wafer, a first bearing wafer and a second bearing wafer;

forming a plurality of deep trench isolation structures on the first surface of the device wafer;

repairing the defects of the deep trench isolation structure through a thermal process in a subsequent process;

carrying out first wafer bonding on the first surface of the device wafer and the first bearing wafer, thinning the device wafer to form a second surface of the device wafer, and manufacturing a device and metal interconnection on the surface;

and carrying out wafer bonding for the second time with the second bearing wafer to form the back-illuminated image sensor with the back deep trench isolation structure.

Preferably, the doping is performed prior to the surface (BSI surface) of the device wafer, and the doped regions are activated in a subsequent thermal process.

Preferably, the forming of the deep trench isolation structure includes: forming a thermal oxide film on the surface of the deep trench isolation structure; and depositing a covering layer on the thermal oxide film to at least protect the interface of the silicon and the thermal oxide film in the deep trench isolation structure from being damaged in the subsequent process, and keeping a perfect interface structure, thereby reducing dark current.

Preferably, the covering layer is a conductive material layer or a dielectric layer.

Preferably, the conductive material layer is made of polysilicon, metal or a combination of polysilicon and metal, and negative pressure is applied to the conductive material layer to form a surface pinning layer of the deep trench isolation structure.

In the back deep trench isolation, a deep trench isolation structure is formed firstly, and defects generated in the deep trench isolation forming process can be repaired by adopting a high-temperature thermal process in a subsequent process, so that the number of defective pixels can be greatly reduced and the level of no deep trench isolation can be achieved; in addition, because the deep photodiode can be formed before the image sensor device is formed, the process difficulty of the other surface of the wafer is reduced; meanwhile, the wafer thickness of the back-illuminated image sensor can be increased from 2.1um to 3um, the light sensitivity of red light can be improved by about 15%, the light sensitivity of green light can be improved by 5%, the full-well capacitance of a photodiode can be improved by more than 50%, and the performance of the back-illuminated image sensor is improved. In addition, the inside of the deep trench isolation structure is selectively filled with conductive materials, and the region close to the deep trench isolation structure can be inverted by applying negative voltage to form a pinning layer so as to well reduce surface defects; and a charged medium layer can be laid on the surface of the interface selectively, so that a pinning layer is also formed inside the interface; further reducing surface defects and dark current.

Drawings

Other features and advantages of the present invention will be apparent from, or are set forth in more detail in, the accompanying drawings, which together with the description serve to explain certain principles of the invention.

Fig. 1 to 15 are schematic structural diagrams corresponding to steps of a method for manufacturing a back side illuminated image sensor using back side deep trench isolation according to an embodiment of the present invention;

fig. 1 to 5A, 5B, and 6 to 15 are schematic structural diagrams corresponding to steps of a method for manufacturing a backside deep trench isolated backside illuminated image sensor according to an embodiment of the present invention;

fig. 16 to 30 are schematic structural diagrams corresponding to steps of a method for manufacturing a back side illuminated image sensor using back side deep trench isolation according to an embodiment of the present invention;

fig. 31 is a flowchart of a method for fabricating a backside illuminated image sensor using backside deep trench isolation according to an embodiment of the present invention.

Detailed Description

The deep trench isolation structure of the existing back-illuminated image sensor is formed after an image sensor device is formed, and because a key device is formed, consideration of various factors of temperature and environment is required in the subsequent deep trench isolation structure forming process, the interface of the surface of the isolation structure needs to be ensured, and the device needs to be prevented from being damaged. Because surface defects are caused in the process of forming the isolation structure, the surface defects can cause attachment of current carriers, dark current can be increased, various special environments such as high temperature and the like are generally required for repairing the defects, and the performance of an image sensor device can be influenced or even damaged.

Therefore, the invention provides a back side deep trench isolated back side illumination type image sensor and a manufacturing method thereof. Namely: providing a device wafer, and defining a pixel area and a peripheral area; forming a plurality of deep trench isolation structures on a device wafer; repairing damage in the step of forming the deep trench isolation structure; forming an image sensor device, the deep trench isolation structure separating adjacent pixel cells. The invention can repair the surface defect of the deep groove isolation structure and greatly improve the performance of the image sensor.

The invention is described in detail below with reference to the drawings and the following embodiments: referring to fig. 1 to 15, fig. 1 to 15 are schematic structural diagrams corresponding to steps of a method for manufacturing an image sensor using deep trench isolation according to an embodiment of the present invention.

In fig. 1, a device wafer 100 is provided defining a pixel region C and a peripheral region D. The device wafer is a carrier for manufacturing the image sensor device, and can be an epitaxial wafer or an SOI wafer, wherein the epitaxial wafer can adopt a substrate of a P type, and the epitaxial layer is of an N type or a P type; the epitaxial layer is P type or N type. The pixel region C is a region for forming pixel units of the image sensor, and transistor structures and other structures in the pixel units are formed in the region; the peripheral area D is mainly an analog circuit, a digital circuit, an analog-digital processing circuit, and the like that may be involved.

In fig. 2, an etching barrier layer 200 is laid on the back side of the device wafer 100, the etching barrier layer 200 uses a hard mask layer or a photoresist layer, the hard mask layer may use silicon dioxide or silicon nitride, and the thickness is: 2000A to 5000A; the thickness of the photoresist layer is: 1um to 5 um. In fig. 3, a mask is provided, wet etching or dry etching or a combination of both is used to form a plurality of deep trench isolation structures 101, and the etch stop layer 200 laid in fig. 2 plays a role in stopping partial region etching. In fig. 4, the interface of the device wafer 100 is repaired by thermal oxidation, the etching barrier layer 200 on the surface is removed by wet etching, and then the damage of the interface of the device wafer 100 at this time is repaired by thermal process, it should be noted that physical damage can inevitably be caused to the interface in the etching process, at this time, since the image sensor device is not yet manufactured, the repair can be performed by using various environments with controllable temperature and pressure, and it is not necessary to consider influencing key devices, and in this embodiment, the repair is performed by thermal oxidation, etching, and thermal process. In addition, after forming the deep trench isolation structures 101, a desired doped well region may be doped from the back side a of the device wafer 100, and an N-type doped region 102 may be doped in the manufactured image sensor, where the depth of the N-type doped region 102 is: 1-2 um; the concentration is 1e 14-5 e 16; it should be noted that the N-type doped region 102 formed in the present invention can have a deeper depth and a higher concentration than the conventional one, in this embodiment, the N-type doped region 102 is a partial region of the photodiode; because the conventional photodiode is formed by doping on the reverse side of the back surface of the device wafer, i.e., the second surface B, the doping process is complicated due to the long distance, and the effect is poor. Thermal activation after the formation of the photodiode 102 may also be used in the present invention to better distribute the doping concentration in the photodiode 102, since thermal activation, if used in conventional processes, affects other regions of the device and does not need to be considered in the present invention. Referring to fig. 4, a thermal oxide layer (not labeled) is formed after fig. 4 to cover the back surface a of the device wafer, the thickness of the thermal oxide layer (not labeled) is 20 angstroms to 40 angstroms, and the thermal oxide layer can protect the interface of the deep trench isolation structure 101. In fig. 5A, a conductive material layer 300 is deposited on the thermal oxide layer (not labeled) to cover the deep trench isolation structure 101. The conductive material layer 300 fills the deep trench isolation structure 101 region and covers the pixel region C and the peripheral region D of the device wafer; the conductive material layer 300 is an N-type doped polysilicon material in the present embodiment, and a metal or a combination of a metal and a polysilicon material may be used in another embodiment. In fig. 6, a capping layer 400 is deposited to cover the surface of the conductive material layer 300. In this embodiment, the covering layer 400 is a silicon dioxide layer, the covering layer 400 plays a role of protecting the conductive material layer 300 on one hand, and prepares for bonding a subsequent device wafer and a first carrier wafer on the other hand, and the thickness of the covering layer 400 is 1um to 3 um. In fig. 7, a first carrier wafer 500 is provided for first bonding to the device wafer 100 through the cover layer 400; the first carrier wafer 500 is a device-less wafer, and mainly performs the steps of carrying and assisting the subsequent processes. In fig. 8, the bonding apparatus is turned over, and the second surface B of the device wafer 100 is thinned by chemical mechanical polishing or physical mechanical polishing. In fig. 9, a standard image sensor process is performed to fabricate and form an image sensor device. Referring to fig. 10 to 13, a second carrier wafer 600 is provided to be bonded to the second side B of the device wafer 100 for a second time; polishing and thinning the first carrier wafer 500 to the cap layer 400, wherein the thickness of the cap layer 400 is 3000-20000 angstroms; further thinning the covering layer 400 by chemical mechanical polishing or physical mechanical polishing to expose the upper surface of the conductive material layer 300; and removing part of the conductive material layer 300 outside the deep trench isolation structure 101 by wet etching or dry etching, wherein part of the conductive material layer 300 is still filled in the opening of the deep trench isolation structure 101, and the upper surface of the opening of the deep trench isolation structure 101 is flush with the interface of the thermal oxide layer outside the deep trench isolation structure 101 or is recessed in the interface of the thermal oxide layer outside the deep trench isolation structure 101. At this time, the opening of the deep trench isolation structure 101 is filled with the conductive material layer 300, and a thermal oxide layer (not labeled) is laid on the device wafer 100 except for the other region of the opening of the deep trench isolation structure 101. Referring to fig. 14 to fig. 15, a hafnium oxide layer 700 is deposited to cover a thermal oxide layer (not labeled) of a device wafer and cover the surface of the opening of the deep trench isolation structure 101, a portion of the hafnium oxide layer 700 on the surface of the deep trench isolation structures 101 is removed, a metal gate layer 800 is deposited on the surface of a corresponding region of the deep trench isolation structure 101, at this time, the conductive material layers 300 of the deep trench isolation structures 101 are directly connected to a portion of the metal gate layer 800, and the hafnium oxide layer 700 is still spaced between the conductive material layers 300 of the deep trench isolation structures 101 and the metal gate layer 800. Providing a specific voltage to the conductive material layer 300, optionally: the pixel region C is isolated from a negative voltage, and the peripheral region D is isolated from the ground; the inner surface of the deep trench isolation structure 101 of the pixel region C can form a hole accumulation layer due to the influence of the negative voltage, and pins the potential of the inner surface of the interface, namely, the pinning layer 103 is formed; the hafnium oxide layer 700 can also form a pinning layer 104 on the surface of the wafer device 100 due to negative charges, so as to reduce defects, the metal grid layer 800 can be made of tungsten, and the hafnium oxide layer 700 can be replaced by a tantalum oxide layer and is a charged dielectric layer; optionally, an anti-reflection layer (not shown) may be formed between the hafnium oxide layer 700 and the metal grid layer 800. Finally, a passivation layer, a color filter layer 900 and a microlens layer 1000 are formed.

Referring to fig. 1 to 5A and 5B to 15, fig. 1 to 5A and 5B to 15 are schematic structural diagrams corresponding to steps of a method for manufacturing an image sensor using backside deep trench isolation according to another embodiment of the present invention.

In fig. 2, an etching barrier layer 200 is laid on the back side of the device wafer 100, the etching barrier layer 200 uses a hard mask layer or a photoresist layer, the hard mask layer may use silicon dioxide or silicon nitride, and the thickness is: 2000A to 5000A; the thickness of the photoresist layer is: 1um to 5 um. In fig. 3, a mask is provided, wet etching or dry etching or a combination of both is used to form a plurality of deep trench isolation structures 101, and the etch stop layer 200 laid in fig. 2 plays a role in stopping partial region etching. In fig. 4, the interface of the device wafer 100 is repaired by thermal oxidation, the etching barrier layer 200 on the surface is removed by wet etching, and then the damage of the interface of the device wafer 100 at this time is repaired by thermal process, it should be noted that physical damage can be inevitably caused to the interface in the etching process, and at this time, since the image sensor device is not yet manufactured, the repair can be performed by using various environments with controllable temperature and pressure, and it is not necessary to consider influencing the key devices. In addition, after forming the deep trench isolation structures 101, a desired doped well region may be doped from the back side a of the device wafer 100, and an N-type doped region 102 may be doped in the manufactured image sensor, where the depth of the N-type doped region 102 is: 1-2 um; the concentration is 1e 14-5 e 16; it should be noted that the N-type doped region 102 formed in this embodiment of the invention can have a deeper depth and a higher concentration than the conventional one; because the conventional photodiode is formed by doping on the reverse side of the back surface of the device wafer, i.e., the second surface B, the doping process is complicated due to the long distance, and the effect is poor. Thermal activation may also be performed after the formation of the N-type doped region 102 in the present invention, so that the doping concentration profile in the N-type doped region 102 is better, since the thermal activation may affect other regions of the device in the conventional process, which is not considered in the present invention. Referring to fig. 4, a thermal oxide layer (not labeled) is formed after fig. 4 to cover the back surface a of the device wafer, the thickness of the thermal oxide layer (not labeled) is 20 angstroms to 40 angstroms, and the thermal oxide layer can protect the interface of the deep trench isolation structure 101. In fig. 5A, a conductive material layer 300 is deposited on the thermal oxide layer (not labeled) to cover the deep trench isolation structure 101. The conductive material layer 300 fills the deep trench isolation structure 101 region and covers the pixel region C and the peripheral region D of the device wafer; the conductive material layer 300 is an N-type doped polysilicon material in the present embodiment, and a metal or a combination of a metal and a polysilicon material may be used in another embodiment. In fig. 5B, the conductive dielectric layer in the peripheral region D is removed by etching to expose the thermal oxide layer. In fig. 6, a covering layer 400 is deposited to cover the surface of the conductive material layer 300, and in this embodiment, the covering layer 400 is a silicon dioxide layer. The capping layer 400 serves to protect the conductive material layer 300 on the one hand and to prepare for subsequent bonding of the device wafer to the first wafer on the other hand, and the thickness of the capping layer 400 is: 1um to 3 um. In fig. 7, a first carrier wafer 500 is provided for first bonding to the device wafer 100 through the cover layer 400; the first carrier wafer 500 is a device-less wafer, and mainly performs the steps of carrying and assisting the subsequent processes. In fig. 8, the bonding apparatus is turned over to thin the second surface of the device wafer 100, and the chemical mechanical polishing and the physical mechanical polishing are used for the thinning. In fig. 9, a standard image sensor process is performed to fabricate and form an image sensor device. Referring to fig. 10 to 13, a second wafer 600 is provided to be bonded to the second side B of the device wafer 100 for a second time; polishing and thinning the first carrier wafer 500 to the cap layer 400, wherein the thickness of the cap layer 400 is 3000-20000 angstroms; further thinning the covering layer 400 by chemical mechanical polishing or physical mechanical polishing to expose the upper surface of the conductive material layer 300; and removing part of the conductive material layer 300 in the region outside the deep trench isolation structure 101 by wet etching or dry etching, wherein part of the conductive material layer 300 is still filled in the opening of the deep trench isolation structure 101, and the upper surface of the opening of the deep trench isolation structure 101 is flush with the interface of the thermal oxide layer outside the deep trench isolation structure 101 or is recessed in the interface of the thermal oxide layer outside the deep trench isolation structure 101. At this time, the opening of the deep trench isolation structure 101 is the conductive material layer 300, and a thermal oxide layer (not labeled) is laid on the device wafer 100 except for the other region of the opening of the deep trench isolation structure 101. Referring to fig. 14 to fig. 15, a hafnium oxide layer 700 is deposited to cover a thermal oxide layer (not labeled) of a device wafer and cover the surface of the opening of the deep trench isolation structure 101, a portion of the hafnium oxide layer 700 on the surface of the deep trench isolation structures 101 is removed, a metal gate layer 800 is deposited on the surface of a corresponding region of the deep trench isolation structure 101, at this time, the conductive material layers 300 of the deep trench isolation structures 101 are directly connected to a portion of the metal gate layer 800, and a hafnium oxide layer is still spaced between the conductive material layers 300 of the deep trench isolation structures 101 and the metal gate layer 800. Providing a specific voltage to the conductive material layer 300, optionally: the pixel region C is isolated from a negative voltage, and the peripheral region D is isolated from the ground; the inner surface of the deep trench isolation structure 101 of the pixel region C can form a hole accumulation layer due to the influence of the negative voltage, and pins the potential of the inner surface of the interface, namely, the pinning layer 103 is formed; the hafnium oxide layer 700 also forms a pinning layer 104 on the surface of the wafer device 100 due to its negative charge, and the metal grid layer 800 may be made of tungsten. The hafnium oxide layer 700 can be replaced by a tantalum oxide layer, namely a charged dielectric layer; optionally, an anti-reflection layer (not shown) may be formed between the hafnium oxide layer 700 and the metal grid layer 800. Finally, a passivation layer, a color filter layer 900 and a microlens layer 1000 are formed.

Referring to fig. 16 to 30, fig. 16 to 30 are schematic structural diagrams corresponding to steps of a method for manufacturing an image sensor using backside deep trench isolation according to another embodiment of the present invention.

In fig. 16, a device wafer 100 is provided, defining a pixel region C and a peripheral region D. The device wafer is a carrier for manufacturing the image sensor device, and can be an epitaxial wafer or an SOI wafer, wherein the epitaxial wafer can adopt a substrate of a P type, and the epitaxial layer is of an N type or a P type; the epitaxial layer is P type or N type. The pixel region C is a region for forming pixel units of the image sensor, and transistor structures and other structures in the pixel units are formed in the region; the peripheral area D is mainly an analog circuit, a digital circuit, an analog-digital processing circuit, and the like that may be involved.

In fig. 17, an etching barrier layer 200 is laid on the back side of the device wafer 100, the etching barrier layer 200 is a hard mask layer or a photoresist layer, the hard mask layer may be silicon dioxide or silicon nitride, and the thickness is 2000A to 5000A; the thickness of the photoresist layer is: 1um to 5 um. In fig. 18, a mask is provided, wet etching or dry etching or a combination of both is used to form a plurality of deep trench isolation structures 101, and the etch stop layer 200 laid in fig. 17 plays a role in stopping partial region etching. In fig. 19, the interface of the device wafer 100 is repaired by thermal oxidation, the etching stop layer 200 on the surface is removed by wet etching, and then the damage of the interface of the device wafer 100 at this time is repaired by thermal process, it should be noted that physical damage can be inevitably caused to the interface in the etching process, and at this time, since the image sensor device is not yet manufactured, the repair can be performed by using various environments with controllable temperature and pressure without considering influence on the key device. In addition, after forming the deep trench isolation structures 101, a desired doped well region may be doped from the back side a of the device wafer 100, and an N-type doped region 102 may be doped in the manufactured image sensor, where the depth of the N-type doped region 102 is: 1-2 um; the concentration is 1e 14-5 e 16; it should be noted that the N-type doped region 102 formed in this embodiment of the invention can have a deeper depth and a higher concentration than the conventional one; because the conventional photodiode is doped on the reverse side of the back surface of the device wafer, i.e., the second surface B, the doping process is complicated due to the long distance, and the effect is poor. Thermal activation after formation of the photodiode 102 may also be used in the present invention to provide better doping concentration step within the photodiode 102, since thermal activation, if used in conventional processes, affects other regions of the device and is not a concern in the present invention. Referring to fig. 19, a thermal oxide layer (not labeled) is formed to cover the back side a of the device wafer after fig. 19, the thickness of the thermal oxide layer (not labeled) is 20 angstroms to 40 angstroms, and the thermal oxide layer can protect the interface of the deep trench isolation structure 101. In fig. 5A, a first dielectric layer 310 is deposited on a thermal oxide layer (not labeled), in this embodiment, a silicon dioxide layer is used to cover the deep trench isolation structure 101. The first dielectric layer 310 fills the deep trench isolation structure 101 region and covers the pixel region C and the peripheral region D of the device wafer; first dielectric layer 310 is employed in another embodiment. In fig. 21, a capping layer 400 is deposited to cover the surface of the first dielectric layer 310, in this embodiment, the capping layer 400 is a silicon dioxide layer. The capping layer 400 serves to protect the first dielectric layer 310 on the one hand and to prepare for subsequent bonding of the device wafer to the first wafer on the other hand, and the thickness of the capping layer 400 is: 1um to 3 um. In fig. 22, a first carrier wafer 500 is provided for first bonding to the device wafer 100 through the cover layer 400; the first carrier wafer 500 is a device-less wafer, and mainly performs the steps of carrying and assisting the subsequent processes. In fig. 23, the bonding apparatus is turned over to thin the second surface of the device wafer 100, and the chemical mechanical polishing and the physical mechanical polishing are used for the thinning. In fig. 24, a standard image sensor process is performed to fabricate and form an image sensor device. Referring to fig. 25 to 28, a second wafer 600 is provided to be bonded to the second side B of the device wafer 100 for a second time; grinding the first carrier wafer 500 in the direction of the first carrier wafer and thinning the thinned covering layer 400 until the upper surface of the first dielectric layer 310 is exposed; and removing the thermal oxide layer (not labeled) outside the deep trench isolation structure 101 by wet etching or dry etching, and removing a part of the first dielectric layer 310 on the upper surface of the opening of the deep trench isolation structure 101, at this time, a part of the first dielectric layer 310 is still filled in the opening of the deep trench isolation structure 101, and the upper surface of the opening of the deep trench isolation structure 101 is flush with the interface of the thermal oxide layer outside the deep trench isolation structure 101, or is recessed in the interface of the thermal oxide layer outside the deep trench isolation structure 101. At this time, the opening of the deep trench isolation structure 101 is the first dielectric layer 310, and a thermal oxide layer (not labeled) is laid on the device wafer 100 except for the other areas of the opening of the deep trench isolation structure 101. Referring to fig. 29 to fig. 30, a hafnium oxide layer 700 is deposited to cover a thermal oxide layer (not labeled) of the device wafer and cover the surface of the opening of the deep trench isolation structure 101, a portion of the hafnium oxide layer 700 on the surface of the deep trench isolation structures 101 is removed, and a metal grid layer 800 is deposited on the surface of the corresponding region of the deep trench isolation structure 101; the hafnium oxide layer 700 also forms a pinning layer 104 on the surface of the wafer device 100 due to its negative charge, and the metal grid layer 800 may be made of tungsten. The hafnium oxide layer 700 can be replaced by a tantalum oxide layer, namely a charged dielectric layer; optionally, an anti-reflection layer (not shown) may be formed between the hafnium oxide layer 700 and the metal grid layer 800. Finally, a passivation layer, a color filter layer 900 and a microlens layer 1000 are formed.

Referring to fig. 31, fig. 31 is a flowchart illustrating a method for fabricating a backside illuminated image sensor using backside illuminated deep trench isolation according to an embodiment of the present invention. The invention relates to a method for manufacturing a back side illumination type image sensor by adopting back side deep groove isolation, which comprises the steps of providing a device wafer, a first bearing wafer and a second bearing wafer; forming a plurality of deep trench isolation structures on the first surface of the device wafer; repairing the defects of the deep trench isolation structure through a thermal process in a subsequent process; carrying out first wafer bonding on the first surface of the device wafer and the first bearing wafer, thinning the device wafer to form a second surface of the device wafer, and manufacturing a device and metal interconnection on the surface; and carrying out wafer bonding for the second time with the second bearing wafer to form the back-illuminated image sensor with the back deep trench isolation structure. In the present invention, the surface (BSI surface) of the device wafer is doped prior to activating the doped region in a subsequent thermal process. And forming a deep trench isolation structure: forming a thermal oxide film on the surface of the deep trench isolation structure; and depositing a covering layer on the thermal oxide film to at least protect the interface of the silicon and the thermal oxide film in the deep trench isolation structure from being damaged in the subsequent process, and keeping a perfect interface structure, thereby reducing dark current. The covering layer is a conductive material layer or a dielectric layer. The conductive material layer is made of polysilicon, metal or a combination of polysilicon and metal, and negative pressure is applied to the conductive material layer to form a surface pinning layer of the deep trench isolation structure.

In the embodiment, the deep trench isolation structure is formed firstly, and the defects generated in the deep trench isolation forming process can be repaired by adopting a high-temperature thermal process in the subsequent process, so that the number of defective pixels can be greatly reduced and the level of no deep trench isolation can be achieved; in addition, because the deep photodiode can be formed before the image sensor device is formed, the process difficulty of the other surface of the wafer is reduced; meanwhile, the thickness of the wafer can be increased from 2.1um to 3um in the prior art, the light sensitivity of red light can be improved by about 15%, the light sensitivity of green light can be improved by 5%, and the full-well capacitance of the photodiode can be improved by more than 50%. The performance of the back-illuminated image sensor is improved. In addition, a charged medium layer can be laid on the surface of the interface optionally, so that a pinning layer is also formed inside the interface; further reducing surface defects and dark current.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method for manufacturing a back side illuminated image sensor by adopting back side deep groove isolation is characterized by at least comprising the following steps:

providing a device wafer, a first bearing wafer and a second bearing wafer;

carrying out surface doping on the first surface of the device wafer;

forming a thermal oxide film on the surface of the deep trench isolation structure;

depositing a covering layer on the thermal oxide film, at least protecting the interface of silicon and the thermal oxide film in the deep trench isolation structure from being damaged in the subsequent process, and keeping a perfect interface structure so as to reduce dark current;

carrying out wafer bonding for the second time with a second bearing wafer to form a back-side illuminated image sensor with a back deep groove isolation structure;

and thinning the substrate to the covering layer from the direction of the first bearing wafer.

2. The method of manufacturing of claim 1, wherein the steps include: doping is performed prior to the surface of the device wafer, and the doped region is activated in a subsequent thermal process.

3. The method of manufacturing of claim 1, wherein the steps further comprise: the covering layer is a conductive material layer or a dielectric layer.

4. The method of claim 3, wherein the conductive material layer is made of polysilicon, metal or a combination of polysilicon and metal, and a negative pressure is applied to the conductive material layer to form a surface pinning layer of the deep trench isolation structure.