JP2017055050A - Solid state image sensor and manufacturing method of solid state image sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state image sensor which allows for enhancement of the signal charge transfer characteristics from a charge storage region to a floating diffusion, and to provide a manufacturing method of a solid state image sensor.SOLUTION: A solid state image sensor includes a charge storage region, a floating diffusion, and a columnar trench gate. The charge storage region is provided in a semiconductor layer, and stores signal charges subjected to photoelectric conversion by the incident light. The floating diffusion is provided in the surface layer of the semiconductor layer. The columnar trench gate is provided adjacently to the floating diffusion, and reaches the charge storage region from the surface of the semiconductor layer. The width of the side face facing the floating diffusion, and the width of the side face facing the side face are larger than the width of the other side face.SELECTED DRAWING: Figure 3

Description

  Embodiments described herein relate generally to a solid-state imaging device and a method for manufacturing the solid-state imaging device.

  2. Description of the Related Art Conventionally, there is a solid-state imaging device that includes a photoelectric conversion element having a charge accumulation region that photoelectrically converts light incident on a semiconductor layer into signal charge and accumulates, and a floating diffusion provided on a surface layer of the semiconductor layer.

  Such a solid-state imaging device includes a trench gate that extends from the surface of the semiconductor layer to the inside of the charge storage region at a position adjacent to the floating diffusion, and applies a voltage to the trench gate to transfer signal charges from the charge storage region to the floating diffusion. Forward.

JP 2013-26264 A

  An object of one embodiment is to provide a solid-state imaging device and a method of manufacturing the solid-state imaging device that can improve the transfer characteristics of signal charges from a charge accumulation region to a floating diffusion.

  According to one embodiment, a solid-state imaging device is provided. The solid-state imaging device includes a charge accumulation region, a floating diffusion, and a columnar trench gate. The charge accumulation region is provided in the semiconductor layer and accumulates signal charges photoelectrically converted by incident light. The floating diffusion is provided on the surface layer of the semiconductor layer. A columnar trench gate is provided adjacent to the floating diffusion, reaches from the surface of the semiconductor layer to the charge storage region, and the width of the side surface facing the floating diffusion and the width of the side surface facing the side surface are the other side surfaces. Greater than the width of

FIG. 1 is a block diagram illustrating a schematic configuration of a digital camera including the solid-state imaging device according to the embodiment. FIG. 2 is a block diagram illustrating a schematic configuration of the solid-state imaging device according to the embodiment. FIG. 3 is an explanatory diagram of the trench gate according to the embodiment. FIG. 4 is an explanatory diagram illustrating a schematic cross section of a pixel according to the embodiment. FIG. 5 is an explanatory diagram showing a schematic cross section of the pixel along the line AA ′ in FIG. 4. FIG. 6 is an explanatory diagram illustrating a manufacturing process of the solid-state imaging device according to the embodiment. FIG. 7 is an explanatory diagram illustrating a manufacturing process of the solid-state imaging device according to the embodiment. FIG. 8 is an explanatory diagram illustrating a manufacturing process of the solid-state imaging device according to the embodiment. FIG. 9 is an explanatory diagram of a trench gate according to Modification 1 of the embodiment. FIG. 10 is an explanatory diagram of a trench gate according to the second modification of the embodiment.

  Exemplary embodiments of a solid-state imaging device and a method for manufacturing the solid-state imaging device will be described below in detail with reference to the accompanying drawings. In addition, this invention is not limited by this embodiment.

  FIG. 1 is a block diagram illustrating a schematic configuration of a digital camera 1 including a solid-state imaging device 14 according to the embodiment. As shown in FIG. 1, the digital camera 1 includes a camera module 11 and a post-processing unit 12.

  The camera module 11 includes an imaging optical system 13 and a solid-state imaging device 14. The imaging optical system 13 takes in light from a subject and forms a subject image. The solid-state imaging device 14 captures a subject image formed by the imaging optical system 13 and outputs an image signal obtained by the imaging to the post-processing unit 12. In addition to the digital camera 1, the camera module 11 is applied to an electronic device such as a mobile terminal with a camera.

  The post-processing unit 12 includes an ISP (Image Signal Processor) 15, a storage unit 16, and a display unit 17. The ISP 15 performs signal processing of the image signal input from the solid-state imaging device 14. The ISP 15 performs high image quality processing such as noise removal processing, defective pixel correction processing, and resolution conversion processing.

  Then, the ISP 15 outputs the image signal after the signal processing to the signal processing circuit 21 (see FIG. 2) described later provided in the storage unit 16, the display unit 17, and the solid-state imaging device 14 in the camera module 11. An image signal fed back from the ISP 15 to the camera module 11 is used for adjustment and control of the solid-state imaging device 14.

  The storage unit 16 stores the image signal input from the ISP 15 as an image. In addition, the storage unit 16 outputs an image signal of the stored image to the display unit 17 according to a user operation or the like. The display unit 17 displays an image according to an image signal input from the ISP 15 or the storage unit 16. The display unit 17 is, for example, a liquid crystal display.

  Next, the solid-state imaging device 14 included in the camera module 11 will be described with reference to FIG. FIG. 2 is a block diagram illustrating a schematic configuration of the solid-state imaging device 14 according to the embodiment. As shown in FIG. 2, the solid-state imaging device 14 includes an image sensor 20 and a signal processing circuit 21.

  Here, the image sensor 20 is a so-called backside illumination type CMOS (Complementary Metal Oxide Semiconductor) image sensor in which a wiring layer is formed on the side opposite to the surface on which incident light is incident in a pixel that photoelectrically converts incident light. The case will be described. Note that the image sensor 20 according to the embodiment is not limited to the backside illumination type CMOS image sensor, and may be a front side illumination type CMOS image sensor.

  The image sensor 20 includes a peripheral circuit 22 and a pixel array 23. The peripheral circuit 22 includes a vertical shift register 24, a timing control unit 25, a CDS (correlated double sampling) 26, an ADC (analog / digital conversion unit) 27, and a line memory 28, and these are mainly configured by analog circuits. Is done.

  The pixel array 23 is provided in the imaging region of the image sensor 20. In the pixel array 23, a plurality of photoelectric conversion elements corresponding to each pixel of the captured image are arranged in a two-dimensional array (matrix) in the horizontal direction (row direction) and the vertical direction (column direction).

  In the pixel array 23, the photoelectric conversion element of each pixel generates a signal charge (for example, electrons) corresponding to the amount of incident light, and accumulates it in a charge accumulation region in each pixel. Each pixel includes a floating diffusion (hereinafter referred to as “FD”) provided in the surface layer of the semiconductor layer in which the charge storage region is provided, and a trench gate that is adjacent to the FD and reaches the inside of the charge storage region. Prepare.

  When a voltage is applied to the trench gate, each pixel transfers a signal charge from the charge storage region to the FD, and a voltage signal corresponding to the amount of the signal charge transferred to the FD is displayed in the captured image. The pixel signal indicating the luminance of each pixel is output.

  In the solid-state imaging device according to the present embodiment, the signal charge transfer characteristic from the charge accumulation region to the FD is improved by improving the shape of the trench gate provided in each pixel. The configuration of each pixel will be described in detail later with reference to FIGS.

  The timing control unit 25 is a processing unit that outputs a pulse signal serving as a reference for operation timing to the vertical shift register 24, the CDS 26, the ADC 27, and the line memory 28. The vertical shift register 24 is a processing unit that outputs, to the pixel array 23, a selection signal for sequentially selecting pixels for reading signal charges from a plurality of pixels that are two-dimensionally arranged in an array (matrix). .

  The pixel array 23 outputs a pixel signal corresponding to the signal charge accumulated in each pixel from each pixel selected in units of rows by the selection signal input from the vertical shift register 24 to the CDS 26.

  The CDS 26 is a processing unit that removes noise from the pixel signal input from the pixel array 23 by correlated double sampling and outputs the noise to the ADC 27. The ADC 27 is a processing unit that converts an analog pixel signal input from the CDS 26 into a digital pixel signal and outputs the digital pixel signal to the line memory 28. The line memory 28 is a processing unit that temporarily holds the pixel signal input from the ADC 27 and outputs the pixel signal to the signal processing circuit 21 for each row of pixels in the pixel array 23.

  The signal processing circuit 21 is a processing unit that performs predetermined signal processing on the pixel signal input from the line memory 28 and outputs the processed signal to the subsequent processing unit 12, and is mainly configured by a digital circuit. The signal processing circuit 21 performs signal processing such as lens shading correction, flaw correction, and noise reduction processing on the pixel signal.

  As described above, in the image sensor 20, a plurality of pixels arranged in the pixel array 23 photoelectrically converts incident light into signal charges of an amount corresponding to the amount of received light, and accumulates the peripheral circuit 22 in each pixel. Imaging is performed by reading a pixel signal corresponding to the signal charge.

  Next, the arrangement and shape of each pixel of the trench gate 32 according to the embodiment will be described with reference to FIG. FIG. 3 is an explanatory diagram of the trench gate 32 according to the embodiment. 3 selectively shows the charge storage region 31, the trench gate 32, and the FD 33 provided in one pixel. A detailed configuration of one pixel including components other than the charge storage region 31, the trench gate 32, and the FD 33 will be described later with reference to FIGS.

  In FIG. 3, for convenience, each surface of the charge storage region 31, the trench gate 32, and the FD 33 is described as a plane, and a corner between each surface and a surface adjacent to each surface is described as a right angle. It is not a perfect plane and the corners are not perfectly right but rounded somewhat.

  As shown in FIG. 3, each pixel includes a charge storage region 31 of the second conductivity type (here, N type) inside the semiconductor layer of the first conductivity type (here, P type). And a second conductivity type (N-type here) FD 33 is provided on the surface layer of the P-type semiconductor layer. Each pixel includes a trench gate 32 that extends from a position adjacent to the FD 33 on the surface layer of the P-type semiconductor layer to the inside of the charge storage region 31.

  The N-type charge accumulation region 31 forms a photodiode as a photoelectric conversion element by a PN junction with a P-type semiconductor layer, and light incident from the light receiving surface (here, the lower surface) side is a signal charge corresponding to the amount of light. This is an area for photoelectric conversion and accumulation.

  The trench gate 32 is, for example, a gate that transfers signal charges from the charge storage region 31 to the FD 33 by forming a channel serving as a signal charge transfer path in the vicinity of the peripheral surface when a predetermined voltage is applied. . The FD 33 is a region that holds signal charges transferred from the charge accumulation region 31. Each pixel amplifies the signal charge held in the FD 33 and outputs it to the CDS 26 (see FIG. 2) as a pixel signal.

  Here, a general trench gate has a pillar shape in which a cross section in a plane direction of a P-type semiconductor layer is substantially square or circular. In the trench gate having such a shape, when a voltage is applied, the potential of the entire side peripheral surface becomes uniform, and a potential gradient is hardly formed in the side peripheral surface.

  For this reason, in a pixel including a trench gate having such a shape, even if a voltage is applied to the trench gate, a channel serving as a signal charge transfer path is not sufficiently formed between the charge accumulation region and the FD. Transfer characteristics may deteriorate. For example, in the pixel, the transfer rate of the signal charge may decrease, or the signal charge may remain in the charge accumulation region without being transferred to the FD.

  Therefore, in the trench gate 32 according to the embodiment, as shown in FIG. 3, the width d1 of the side surface 41 facing the FD 33 and the width d1 of the side surface 42 facing the side surface 41 are The column shape was larger than the width d2.

  The direction of the width here is, for example, a direction parallel to the plane direction of the plane whose normal direction is the extending direction of the trench gate 32 from the surface of the semiconductor layer where the trench gate 32 is formed toward the charge storage region 31. It is.

  Thereby, when a predetermined voltage is applied to the trench gate 32, the potential of the side surface 41 facing the FD 33 and the potential of the side surface 42 facing the side surface 41 are higher than the potentials of the other side surfaces 43 and 44. Also gets higher.

  That is, of the four side surfaces 41, 42, 43, 44, the trench gate 32 has a higher potential on the side surface 41, 42 with the larger area than on the side surface 43, 44 with the smaller area. Thereby, the trench gate 32 can form a potential gradient from the side surfaces 43 and 44 side not facing the FD 33 toward the side surface 41 side facing the FD 33.

  Therefore, according to the trench gate 32, as indicated by a thick line arrow in FIG. 3, the charge accumulation region 31 goes to the FD 33 via the side surfaces 43 and 44 that do not face the FD 33 and the side surface 41 that faces the FD 33. It is possible to form a signal charge transfer path having high transfer characteristics.

  As described above, since the pixel including the trench gate 32 can form a channel with higher charge transfer efficiency than the pixel including the trench gate having the general shape described above, the charge storage region 31 to the FD 33 can be formed. Signal charge transfer characteristics can be improved.

  In addition, as the difference between the width d1 of the side surfaces 41 and 42 and the width d2 of the side surfaces 43 and 44 increases, the trench gate 32 has a potential difference between the side surfaces 41 and 42 and the side surfaces 43 and 44 when a voltage is applied. Therefore, the signal charge transfer characteristics can be improved.

  Next, the overall configuration of each pixel will be described with reference to FIGS. 4 and 5. FIG. 4 is an explanatory diagram illustrating a schematic cross section of a pixel according to the embodiment. FIG. 5 is an explanatory diagram showing a schematic cross section of the pixel along the line AA ′ in FIG. 4.

  As shown in FIG. 4, each pixel provided in the pixel array 23 includes a microlens 51 on the lower side where light enters, and a color filter 52, an antireflection film 53, P, which are sequentially stacked on the microlens 51. A semiconductor layer 54 of a type, a multilayer wiring layer 56, and a support substrate 59 are provided.

  The microlens 51 is a plano-convex lens that collects light incident from the lower surface serving as a light receiving surface. For example, the color filter 52 is a filter that selectively transmits light of any one of red, green, and blue.

  Each pixel is provided with a color filter 52 of any one of red, green, and blue. For example, the three color filters 52 are arranged in a Bayer array. The antireflection film 53 is formed of, for example, silicon nitride, and prevents reflection of light incident through the microlens 51 and the color filter 52.

  The P-type semiconductor layer 54 is a silicon layer doped with a P-type impurity such as boron, for example. The P-type semiconductor layer 54 includes an N-type charge accumulation region 31 inside, and an N-type FD 33 on the surface layer. These charge storage regions 31 and FD 33 are silicon regions doped with N-type impurities such as phosphorus.

  Further, the P-type semiconductor layer 54 includes a pixel isolation region 55 that electrically isolates each pixel. The pixel isolation region 55 is, for example, DTI (Deep Trench Isolation) penetrating the front and back of the P-type semiconductor layer 54 and is formed of silicon oxide.

  The pixel isolation region 55 is not limited to DTI, and may be a semiconductor region in which a P-type impurity such as boron is doped at a higher concentration than the P-type semiconductor layer 54. A combination of a semiconductor region doped with impurities and DTI may be used. For example, as illustrated in FIG. 5, the pixel isolation region 55 is provided in a grid pattern that partitions the P-type semiconductor layer 54 for each pixel.

  As shown in FIG. 4, each pixel includes a trench gate 32 that extends from the top of the P-type semiconductor layer 54 to the inside of the charge storage region 31 at a position adjacent to the FD 33. The trench gate 32 is made of, for example, polysilicon. A gate insulating film 34 is provided at the interface between the trench gate 32 and the P-type semiconductor layer 54 and the charge storage region 31. The gate insulating film 34 is, for example, a silicon oxide film.

  The multilayer wiring layer 56 includes an interlayer insulating film 57 and a multilayer wiring 58 provided inside the interlayer insulating film 57. The interlayer insulating film 57 is, for example, a TEOS (tetraethoxysilane) film. The multilayer wiring 58 is, for example, a copper wiring. The support substrate 59 is, for example, a silicon substrate, and becomes a supported portion when the P-type semiconductor layer 54 is thinned to form a light receiving surface of a pixel.

  Each pixel photoelectrically converts light incident from the microlens 51 into a signal charge corresponding to the amount of light received at the interface between the P-type semiconductor layer 54 and the N-type charge accumulation region 31 and accumulates it in the charge accumulation region 31. . Then, when a predetermined voltage is applied to the trench gate 32, each pixel transfers the signal charge from the charge accumulation region 31 to the FD 33 via a path indicated by a thick line arrow in FIG.

  Here, as shown in FIG. 5, the cross section of the trench gate 32 has a rectangular shape in which the side facing the FD 33 has a long side and the side not facing the FD 33 has a short side. Thus, in each pixel, when a predetermined voltage is applied to the trench gate 32, a potential gradient is formed from the side surface on the short side view in section to the side surface on the long side view in section shown in FIG.

  Therefore, as shown by the thick arrows in FIG. 5, each pixel easily forms a signal charge transfer path from the outside of both side surfaces on the short side in cross section to the FD 33 through the trench gate 32. It is possible to improve the transfer characteristics.

  Next, with reference to FIGS. 6-8, the manufacturing method of the solid-state imaging device 14 which concerns on embodiment is demonstrated. 6-8 is explanatory drawing by the cross sectional view which shows the manufacturing process of the solid-state imaging device 14 concerning embodiment.

  In addition, in the manufacturing process of the solid-state imaging device 14 according to the embodiment, the manufacturing process of the solid-state imaging device is the same as that of the general solid-state imaging device except for the manufacturing process of each pixel portion. Therefore, here, the manufacturing process of one pixel portion shown in FIG. 4 will be described, and the description of the other processes will be omitted. In the following description, the same components as those shown in FIG. 4 are denoted by the same reference numerals as those shown in FIG.

  When manufacturing the pixel array 23, first, as shown in FIG. 6A, a P-type semiconductor layer 54 is formed on the non-doped silicon layer 60. Here, for example, a P-type semiconductor that reaches from a surface of the silicon substrate to a predetermined depth position where a pixel is formed later by performing ion implantation of boron into the silicon substrate from the surface of the silicon substrate and performing an annealing process. Layer 54 is formed.

  Subsequently, for example, RIE (Reactive Ion Etching) is performed on the P-type semiconductor layer 54 at a position where a region where each pixel is to be formed later is separated, thereby forming a trench 61 having a lattice shape in plan view. Thereafter, as shown in FIG. 6B, the pixel isolation region 55 is formed by depositing silicon oxide in the trench 61 by, for example, CVD (Chemical Vapor Deposition).

  Thereafter, as shown in FIG. 6C, the N-type charge accumulation region 31 is formed inside the P-type semiconductor layer 54 separated by the pixel separation region 55. Here, the charge storage region 31 is formed by ion-implanting phosphorus from the surface of the P-type semiconductor layer 54 into the inside and performing an annealing process.

  Subsequently, as shown in FIG. 7A, for example, by performing RIE on the surface of the P-type semiconductor layer 54 where the trench gate 32 (see FIGS. 4 and 5) is formed, P An opening 62 having a rectangular shape in plan view extending from the surface of the semiconductor layer 54 to the inside of the charge storage region 31 is formed.

  At this time, of the four inner surfaces of the opening 62, the width of the inner surface on the side facing the FD 33 to be formed later and the width of the inner surface on the side facing the inner surface are the widths of the remaining two inner surfaces. A larger opening 62 is formed.

  Thereafter, as shown in FIG. 7B, the gate insulating film 34 is formed on the inner peripheral surface of the opening 62 and the upper surfaces of the P-type semiconductor layer 54 and the pixel isolation region 55. Here, for example, the gate insulating film 34 is formed by thermal oxidation. Note that the gate insulating film 34 may be formed by CVD.

  Subsequently, as shown in FIG. 7C, after polysilicon is deposited on the gate insulating film 34 by, for example, CVD to fill the opening 62 with polysilicon, unnecessary portions of polysilicon and gate insulation are formed. The film 34 is removed and a trench gate 32 is formed.

  Thereafter, phosphorus is ion-implanted into the surface layer of the P-type semiconductor layer 54 and adjacent to the larger side surface of the four side surfaces of the trench gate 32 to perform N-type FD33. Form. Here, the FD 33 is formed at a position (see FIG. 5) adjacent to the side surface closer to the pixel isolation region 55 among the two side surfaces having the wider width of the trench gate 32.

  Subsequently, as shown in FIG. 8A, a multilayer wiring layer 56 is formed on the P-type semiconductor layer 54. Here, for example, an interlayer insulating film 57 is formed, a groove for the multilayer wiring 58 is patterned in the interlayer insulating film 57, and a series of steps of embedding copper in the groove is repeated to form the multilayer wiring layer 56. .

  Thereafter, as shown in FIG. 8B, a support substrate 59 is bonded onto the multilayer wiring layer 56. The support substrate 59 is supported, and the back surface of the P-type semiconductor layer 54 and the pixel isolation region 55 is exposed by grinding and polishing the non-doped silicon layer 60 from the back surface, for example, by CMP (Chemical Mechanical Polishing). To form a light receiving surface of the pixel.

  Subsequently, as shown in FIG. 8C, an antireflection film 53 and a color filter 52 are sequentially formed on the light receiving surface of the pixel. Here, the antireflection film 53 is formed on the light receiving surface (here, the lower surface) of the pixel by, for example, depositing silicon nitride by CVD, and red, green, and blue colors are formed on the light receiving surface of the antireflection film 53. The color filter 52 is formed by sequentially forming a resist. Finally, the microlens 51 is formed on the light receiving surface of the color filter 52 to complete the pixel shown in FIG.

  As described above, each pixel of the solid-state imaging device according to the embodiment includes a charge accumulation region that accumulates the incident light by photoelectric conversion inside the semiconductor layer, and includes an FD on the surface layer of the semiconductor layer. Further, each pixel includes a trench gate that extends from a position adjacent to the FD to the inside of the charge storage region. In the trench gate, the width of the side surface facing the FD and the width of the side surface facing this side surface are larger than the widths of the other side surfaces.

  Thus, each pixel can easily form a signal charge transfer path from the charge accumulation region to the FD via the side peripheral surface of the transfer gate when a voltage is applied to the trench gate. Therefore, each pixel can improve the signal charge transfer efficiency by increasing the transfer rate of the signal charge from the charge storage region to the FD and suppressing the signal charge transfer leakage.

  Note that the shape of the trench gate 32 according to the embodiment is not limited to the shape described above. Hereinafter, modified examples 1 and 2 of the trench gate according to the embodiment will be described with reference to FIGS. 9 and 10. FIG. 9 is an explanatory diagram of a trench gate 32a according to Modification 1 of the embodiment, and FIG. 10 is an explanatory diagram of a trench gate 32b according to Modification 2 of the embodiment.

  Here, among the components shown in FIGS. 9 and 10, the same components as those shown in FIG. 3 are denoted by the same reference numerals as those shown in FIG. To do.

  As shown in FIG. 9, in the trench gate 32 a according to the first modification, the width of the side surface 41 a facing the FD 33 and the width of the side surface 42 a facing the side surface 41 a go to the deep layer of the P-type semiconductor layer 54. As it gets smaller. In addition, the width of the two side surfaces 43a and 44a that do not face the FD 33 of the trench gate 32a decreases toward the deep layer of the P-type semiconductor layer 54.

  As a result, when a voltage is applied to the trench gate 32a, a potential gradient in which the potential on the surface on the deep layer side in the P-type semiconductor layer 54 is higher than the potential on the surface on the surface layer side is generated, and charge is accumulated around the side surface. A signal charge transfer path from the region 31 to the FD 33 is easily formed.

  Moreover, in the trench gate 32a, similarly to the trench gate 32 shown in FIG. 3, the width of the side surface 41a facing the FD 33 and the width of the side surface 42a facing the side surface 41a are larger than the widths of the other side surfaces 43a and 44a. large. Therefore, according to the trench gate 32a, the signal charge transfer characteristics can be further improved.

  Here, the case where the four side surfaces 41a, 42a, 43a, 44a of the trench gate 32a become smaller toward the deep layer of the P-type semiconductor layer 54 has been described, but the side surface shape of the trench gate 32a is It is not limited.

  For example, the trench gate 32 a may have a shape in which the two side surfaces 41 a and 42 a facing the FD 33 or the two side surfaces 43 a and 44 a not facing the FD 33 become smaller toward the deep layer of the P-type semiconductor layer 54. . Even in such a shape, the trench gate 32a can easily form a signal charge transfer path from the charge accumulation region 31 to the FD 33 around the side surface, thereby improving the signal charge transfer efficiency.

  As shown in FIG. 10, the trench gate 32b according to Modification 2 is different from the trench gate 32a according to Modification 1 in that the cross-sectional shape in the plane direction of the P-type semiconductor layer 54 is elliptical. In the trench gate 32b, the width of the side surface 41b facing the FD 33 and the width of the side surface 42b facing the side surface 41b are larger than the widths of the other side surfaces 43b and 44b.

  That is, the trench gate 32b is arranged so that the side surface on the relatively loose side among the side surfaces faces the FD 33. Further, the trench gate 32 b has a tapered shape that tapers toward the deep layer of the P-type semiconductor layer 54.

  Thereby, when a voltage is applied to the trench gate 32b, a potential gradient substantially the same as that of the first modification can be formed on the side surface, so that a charge transfer path from the charge accumulation region 31 to the FD 33 is easily formed, and the signal charge It is possible to improve the transfer characteristics.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 Digital camera, 11 Camera module, 12 Subsequent processing part, 13 Imaging optical system, 14 Solid-state imaging device, 15 ISP, 16 Memory | storage part, 17 Display part, 20 Image sensor, 21 Signal processing circuit, 22 Peripheral circuit, 23 Pixel array 24 vertical shift register, 25 timing control unit, 26 CDS, 27 ADC, 28 line memory, 32, 32a, 32b trench gate, 34 gate insulating film, 51 microlens, 52 color filter, 53 antireflection film, 54 P type Semiconductor layer, 55 pixel isolation region, 56 multilayer wiring layer, 57 interlayer insulating film, 58 multilayer wiring, 59 support substrate, 60 silicon layer, 61 trench, 62 opening.

Claims (6)

A charge storage region that is provided in the semiconductor layer and stores signal charges photoelectrically converted by incident light;
A floating diffusion provided in a surface layer of the semiconductor layer;
A columnar shape adjacent to the floating diffusion, reaching the charge storage region from the surface of the semiconductor layer, and having a width of a side surface facing the floating diffusion and a width of a side surface facing the side surface larger than the width of the other side surface A solid-state imaging device comprising: a trench gate. The trench gate is
2. The solid-state imaging device according to claim 1, wherein an area of a side surface facing the floating diffusion and an area of a side surface facing the side surface are larger than areas of other side surfaces. The trench gate is
The solid-state imaging device according to claim 1, wherein a cross section of the semiconductor layer in a surface direction is substantially rectangular. The trench gate is
The solid-state imaging device according to claim 1, wherein a cross section of the semiconductor layer in a plane direction is elliptical. The trench gate is
5. The solid-state imaging according to claim 1, wherein a width of a side surface facing the floating diffusion and a width of a side surface facing the side surface become smaller as going to a deep layer of the semiconductor layer. apparatus. Forming a second conductivity type charge storage region inside the first conductivity type semiconductor layer;
From the surface of the semiconductor layer to the charge storage region, forming a trench in which the width of one side surface and the width of the side surface facing the side surface are larger than the width of the other side surface;
Forming a gate insulating film on the inner peripheral surface of the trench;
Filling the trench formed with an inner peripheral surface of the gate insulating film with a conductive member to form a trench gate;
Forming a second-conductivity-type floating diffusion at a position adjacent to the one side surface of the trench gate in the surface layer of the semiconductor layer.

Images