CN111933651A - Pixel structure of image sensor and forming method thereof - Google Patents
Pixel structure of image sensor and forming method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
- H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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Abstract
A pixel structure of an image sensor and a forming method thereof comprise: providing a substrate; forming a groove in the substrate; forming a storage region in the substrate, wherein the storage region is provided with first doped ions and is positioned on the side wall and the bottom surface of the groove; and forming a storage gate structure on the substrate, wherein part of the storage gate structure is positioned on the surface of the storage region and in the groove. A groove is formed in the substrate, a storage grid structure is formed on the substrate, part of the storage grid structure is located on the surface of the storage region and located in the groove, the pixel area occupied by the storage grid structure is reduced, the forming area of the photosensitive region is increased in the subsequent manufacturing process, the filling factor of pixels is further improved, meanwhile, the sensitivity and the quantum efficiency of the image sensor are also improved, and the performance of the finally formed image sensor is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a pixel structure of an image sensor and a forming method thereof.
Background
Image sensors are classified into Complementary Metal Oxide (CMOS) image sensors and Charge Coupled Device (CCD) image sensors, and are generally used to convert optical signals into corresponding electrical signals. The CCD image sensor has advantages of high image sensitivity and low noise, but the integration of the CCD image sensor with other devices is difficult and the power consumption of the CCD image sensor is high. In contrast, the CMOS image sensor has the advantages of simple process, easy integration with other devices, small volume, light weight, low power consumption, low cost, and the like. At present, CMOS image sensors are widely used in still digital cameras, camera phones, digital video cameras, medical imaging devices (e.g., gastroscopes), vehicle imaging devices, and the like.
The CMOS image sensor may be classified into a line-by-line exposure CMOS image sensor and a global exposure CMOS image sensor according to an exposure method. A CMOS image sensor of line-by-line exposure (Rolling Shutter) has the defects of moving image inclination, distortion and the like due to different starting points of line exposure time; and all pixels in a frame of image of the CMOS image sensor with global exposure start exposure at a certain moment and end exposure at another moment, and the global exposure mode can eliminate the defects of line-by-line exposure and realize image output with high frame rate.
However, the performance of the image sensor of the related art still remains to be improved.
Disclosure of Invention
The invention aims to provide a pixel structure of an image sensor and a forming method thereof, which can effectively improve the performance of the finally formed image sensor.
To solve the above problems, the present invention provides a pixel structure of an image sensor, including: a substrate; a recess in the substrate; the storage region is positioned in the substrate, first doping ions are arranged in the storage region, and the storage region is positioned on the side wall and the bottom surface of the groove; and the storage gate structure is positioned on the substrate, and part of the storage gate structure is positioned on the surface of the storage region and in the groove.
Optionally, the depth of the groove is 0.1 μm to 5 μm.
Optionally, the depth-to-width ratio of the groove ranges from 0.2 to 20.
Optionally, the dimension at the top of the groove is larger than the dimension at the bottom of the groove, and the directions of the top dimension and the bottom dimension are parallel to the top surface of the substrate.
Optionally, an included angle between the sidewall of the groove and the top surface of the substrate is 45 ° to 90 °.
Optionally, the storage gate structure includes: the gate structure comprises a gate dielectric layer and a gate electrode layer positioned on the gate dielectric layer.
Optionally, the material of the gate dielectric layer includes silicon oxide.
Optionally, the thickness of the gate dielectric layer is 1nm to 10 nm.
Optionally, the material of the gate layer includes polysilicon.
Optionally, the method further includes: and the light shielding layer is positioned on the storage region and covers part of the side wall and the top surface of the storage grid structure.
Optionally, the material of the light shielding layer includes tungsten.
Optionally, the first doping ions include N-type ions, and the N-type ions include: phosphorus or arsenic.
Optionally, the method further includes: and the first passivation layer is positioned on the surface of the storage region, and second doped ions are arranged in the first passivation layer and have a different conductivity type from the first doped ions.
Optionally, the second doping ions include P-type ions, and the P-type ions include: boron or boron difluoride.
Optionally, the method further includes: and the photosensitive area is positioned in the substrate and is mutually separated from the storage area, the photosensitive area is adjacent to the storage grid structure, and the first doped ions are arranged in the photosensitive area.
Optionally, the method further includes: and the second passivation layer is positioned on the surface of the photosensitive area, and second doping ions are arranged in the second passivation layer and have different conductivity types from the first doping ions.
Optionally, the method further includes: a transfer gate structure on the substrate, the transfer gate structure adjacent to the storage region.
Optionally, the method further includes: and the floating diffusion region and the storage region are respectively positioned at two sides of the transmission grid structure.
Optionally, the light shielding layer is further located on a portion of the top surface of the transmission gate structure.
Correspondingly, the invention also provides a forming method of the pixel structure of the image sensor, which comprises the following steps: providing a substrate; forming a groove in the substrate; forming a storage region in the substrate, wherein the storage region is provided with first doped ions and is positioned on the side wall and the bottom surface of the groove; and forming a storage gate structure on the substrate, wherein part of the storage gate structure is positioned on the surface of the storage region and in the groove.
Optionally, the depth of the groove is 0.1 μm to 5 μm.
Optionally, the depth-to-width ratio of the groove ranges from 0.2 to 20.
Optionally, the dimension at the top of the groove is larger than the dimension at the bottom of the groove, and the directions of the top dimension and the bottom dimension are parallel to the top surface of the substrate.
Optionally, an included angle between the sidewall of the groove and the top surface of the substrate is 45 ° to 90 °.
Optionally, the storage gate structure includes: the gate structure comprises a gate dielectric layer and a gate electrode layer positioned on the gate dielectric layer.
Optionally, the material of the gate dielectric layer includes silicon oxide.
Optionally, the thickness of the gate dielectric layer is 1nm to 10 nm.
Optionally, the material of the gate layer includes polysilicon.
Optionally, after the forming the storage gate structure, the method further includes: and forming a light shielding layer on the storage region, wherein the light shielding layer covers part of the side wall and the top surface of the storage grid structure.
Optionally, the material of the light shielding layer includes tungsten.
Optionally, the first doping ions include N-type ions, and the N-type ions include: phosphorus or arsenic.
Optionally, the method for forming the storage region includes: and carrying out ion implantation treatment of the first doping ions on the substrate exposed by the groove to form the storage region.
Optionally, the parameters of the ion implantation process of the first doping ions include: the implantation dose of the first doping ions is 3E11atm/cm2～2E13atm/cm2(ii) a The implantation angle of the first doped ions is 0-45 degrees.
Optionally, before forming the storage gate structure, the method further includes: and forming a first passivation layer on the storage region, wherein the first passivation layer is internally provided with second doped ions, and the second doped ions are different from the first doped ions in conductivity type.
Optionally, before forming the storage gate structure, the method further includes: and forming a photosensitive area separated from the storage area in the substrate, wherein the photosensitive area is adjacent to the storage grid structure, and the photosensitive area is internally provided with the first doped ions.
Optionally, after the forming the photosensitive region, the method further includes: and forming a second passivation layer on the surface of the photosensitive area, wherein the second passivation layer is internally provided with the second doping ions.
Optionally, the second doping ions include P-type ions, and the P-type ions include: boron or boron difluoride.
Optionally, the first passivation layer and the second passivation layer are formed at the same time, and the method for forming the first passivation layer and the second passivation layer includes: and carrying out ion implantation treatment on the second doped ions on the substrate to form the first passivation layer and the second passivation layer.
Optionally, the doping of the ion implantation treatment of the second doping ions includes: the second doping ion implantation dosage is 3E11atm/cm2～5E13atm/cm2(ii) a The implantation energy of the second doped ions is 5 KeV-120 KeV; the implantation angle of the second doped ions is 0-45 degrees.
Optionally, in the process of forming the storage gate structure, the method further includes: forming a transfer gate structure on the substrate, the transfer gate structure being adjacent to the storage region.
Optionally, after the forming of the transfer gate structure, the method further includes: and forming a floating diffusion region in the substrate, wherein the floating diffusion region and the storage region are respectively positioned at two sides of the transmission grid structure.
Optionally, the light shielding layer is further located on a portion of the top surface of the transmission gate structure.
Optionally, the storage region is formed before or after forming the gate dielectric layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the structure of the technical scheme, the groove is formed in the substrate, the storage grid structure is arranged on the substrate, and part of the storage grid structure is arranged on the surface of the storage region and in the groove, so that the pixel area occupied by the storage grid structure is reduced, the forming area of the photosensitive region is increased in the subsequent manufacturing process, the filling factor of the pixel is further improved, meanwhile, the sensitivity and the quantum efficiency of the image sensor are also improved, and the performance of the finally formed image sensor is improved.
Further, still include: and the light shielding layer is positioned on the storage region. The light shielding layer can reduce the light from irradiating the storage area, and the parasitic light sensitivity performance of the image sensor is improved.
Further, still include: a first passivation layer located on the surface of the storage region, wherein the first passivation layer is internally provided with second doped ions, and the second doped ions are different from the first doped ions in conductivity type; and the second passivation layer is positioned on the surface of the photosensitive area, and second doping ions are arranged in the second passivation layer and have different conductivity types from the first doping ions. The defects on the surfaces of the storage region and the photosensitive region can be passivated through the first passivation layer and the second passivation layer, and dark current is reduced.
In the technical scheme forming method, the groove is formed in the substrate, the storage grid structure is formed on the substrate, part of the storage grid structure is positioned on the surface of the storage region and in the groove, so that the pixel area occupied by the storage grid structure is reduced, the forming area of the photosensitive region is increased in the subsequent manufacturing process, the filling factor of the pixel is further improved, meanwhile, the sensitivity and the quantum efficiency of the image sensor are also improved, and the performance of the finally formed image sensor is improved.
Further, still include: a light shielding layer formed on the storage region. The light shielding layer can reduce the light from irradiating the storage area, and the parasitic light sensitivity performance of the image sensor is improved.
Further, still include: forming a first passivation layer on the surface of the storage region, wherein the first passivation layer is internally provided with second doped ions, and the second doped ions are different from the first doped ions in conductivity type; and forming a second passivation layer on the surface of the photosensitive area, wherein the second passivation layer is internally provided with second doped ions, and the second doped ions are different from the first doped ions in conductivity type. The defects on the surfaces of the storage region and the photosensitive region can be passivated through the first passivation layer and the second passivation layer, and dark current is reduced.
Drawings
FIG. 1 is a schematic diagram of a globally exposed pixel structure of an image sensor;
fig. 2 to 11 are schematic structural diagrams of steps of a pixel structure forming method of an image sensor according to another embodiment of the invention.
Detailed Description
As mentioned in the background, the performance of the image sensor in the prior art needs to be improved, and will be described with reference to the accompanying drawings.
Referring to fig. 1, a substrate 100 is provided; forming a storage region 101 in the substrate 100, wherein the storage region 101 has first doping ions therein; a storage gate structure 102 is formed on the surface of the substrate 100.
In this embodiment, since the area of the substrate is constant, when the Storage Gate structures 102(Storage Gate) are all formed in a tiled manner on the top surface of the substrate 100, the Storage Gate structures 102 occupy a large portion of the pixel area. When the pixel area occupied by the storage gate structure is large, the area of the photosensitive region formed in the subsequent process is reduced, and thus the fill factor (the ratio of the photosensitive area of the photodiode of the image sensor to the pixel area) of the finally formed image sensor is not high.
With the rapid development of semiconductor technology, the area of a single pixel of an image sensor is smaller and smaller, and at this time, the existence of the storage gate structure 102 further reduces the fill factor of the pixel, so that the sensitivity and Quantum Efficiency (QE Quantum Efficiency; the ratio of the number of electrons collected by a photodiode to the number of incident photons) of the image sensor are seriously reduced.
On the basis, the invention provides a pixel structure of an image sensor and a forming method thereof, wherein a groove is formed in a substrate, a storage grid structure is formed on the substrate, and part of the storage grid structure is positioned on the surface of a storage region and in the groove, so that the pixel area occupied by the storage grid structure is reduced, the forming area of a photosensitive region is increased in the subsequent process, the filling factor of the pixel is further improved, meanwhile, the sensitivity and the quantum efficiency of the image sensor are also improved, and the performance of the finally formed image sensor is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 11 are schematic structural diagrams illustrating a process of forming a pixel structure of an image sensor according to an embodiment of the invention.
Referring to fig. 2, a substrate 200 is provided.
In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium.
Referring to fig. 3, a groove 201 is formed in the substrate 200.
In this embodiment, the method for forming the groove 201 includes: forming a first patterning layer (not shown) on the substrate 200, the first patterning layer exposing a portion of a top surface of the substrate 200; etching the substrate 200 by using the first patterning layer as a mask to form the groove 201; after the recess 201 is formed, the first patterned layer is removed.
In this embodiment, the process of etching the substrate 200 with the first patterning layer as the mask adopts a wet etching process, and since the etching rate of the wet etching process decreases with the increase of the etching depth, the dimension of the top of the groove 201 is larger than the dimension of the bottom of the groove 201, and the directions of the top dimension and the bottom dimension are parallel to the top surface of the substrate 200.
In this embodiment, an included angle between the sidewall of the groove 201 and the top surface of the substrate 200 is 45 ° to 90 °.
In this embodiment, the depth of the groove 201 is 0.1 μm to 5 μm.
In the embodiment, the depth-to-width ratio of the groove 201 ranges from 0.2 to 20.
Referring to fig. 4, after the groove 201 is formed, a storage region 202 is formed in the substrate 200, the storage region 202 has first doping ions therein, and the storage region 202 is located on the sidewall and the bottom surface of the groove 201.
In the present embodiment, the storage region 202 is a charge storage node of a subsequently formed storage gate structure, and after the storage gate structure is turned on, charges are transferred from a subsequently formed photosensitive region to the storage region 202.
In this embodiment, the method for forming the memory region 202 includes: the substrate 200 exposed by the groove 201 is subjected to the ion implantation process of the first doping ion to form the storage region 202.
The first dopant ions comprise N-type ions, the N-type ions comprising: phosphorus or arsenic. In this embodiment, arsenic is used as the first doping ion.
In this embodiment, the first stepParameters of an ion implantation process for doping ions include: the implantation dose of the first doping ions is 3E11atm/cm2～2E13atm/cm2(ii) a The implantation angle of the first doped ions is 0-45 degrees.
Referring to fig. 5, after the storage region 202 is formed, a photosensitive region 203 separated from the storage region 202 is formed in the substrate 200, wherein the photosensitive region 203 has the first doping ions therein.
In the present embodiment, the photosensitive region 203 is used for receiving and collecting the generated photo-generated voltage, the photosensitive region 203 is adjacent to a storage gate structure formed later, and after the storage gate structure is turned on, charges are transferred from the photosensitive region 203 to the storage region 202.
The first dopant ions comprise N-type ions, the N-type ions comprising: phosphorus or arsenic. In this embodiment, arsenic is used as the first doping ion.
Referring to fig. 6, after forming the photosensitive region 203 and the storage region 202, forming a first passivation layer 204 on the storage region 202, wherein the first passivation layer 204 has second doped ions therein, and the second doped ions have a different conductivity type from the first doped ions; forming a second passivation layer 205 on the surface of the photosensitive region 203, wherein the second passivation layer 205 has the second doping ions therein.
The second dopant ions comprise P-type ions, the P-type ions comprising: boron or boron difluoride. In this embodiment, the second doping ion is boron difluoride.
In this embodiment, the first passivation layer 204 and the second passivation layer 205 are formed simultaneously, and the method for forming the first passivation layer 204 and the second passivation layer 205 includes: performing ion implantation treatment of the second dopant ions on the substrate 200 to form the first passivation layer 204 and the second passivation layer 205.
In this embodiment, the doping of the ion implantation process of the second doping ions includes: the second doping ion implantation dosage is 3E11atm/cm2～5E13atm/cm2(ii) a The implantation energy of the second doped ions is 5 KeV-120 KeV; second dopingThe implantation angle of the impurity ions is 0-45 degrees.
In this embodiment, in order to ensure that the second doping ions can be uniformly doped around the groove 201, multiple times of implantation are required.
In this embodiment, the first passivation layer 204 and the second passivation layer 205 are formed to remove defects on the surfaces of the storage region 202 and the photosensitive region 203, thereby reducing dark current; in other embodiments, instead of forming the first passivation layer and the second passivation layer, a negative voltage may be applied to the storage gate structure during charge storage to reduce dark current in the storage region.
After forming the first passivation layer 204 and the second passivation layer 205, further comprising: forming a storage gate structure on the substrate 200, wherein a part of the storage gate structure is located on the surface of the storage region 202 and in the groove 201; in the process of forming the storage gate structure, the method further comprises the following steps: a transfer gate structure is formed on the substrate 200, the transfer gate structure being adjacent to the storage region 202. Please refer to fig. 7 to 9 for a specific process of forming the storage gate structure and the transfer gate structure.
Referring to fig. 7, an initial gate dielectric layer 206 is formed in the recess 201 and on the substrate 200.
In this embodiment, the material of the initial gate dielectric layer 206 includes silicon oxide.
In this embodiment, the process of forming the initial gate dielectric layer 206 is a thermal growth process.
In this embodiment, the thickness of the initial gate dielectric layer 206 is 1nm to 10 nm.
In this embodiment, the storage region 202 is formed before the initial gate dielectric layer 206 is formed; in other embodiments, the storage region may also be formed after the initial gate dielectric layer is formed.
Referring to fig. 8, an initial gate layer 207 is formed on the initial gate dielectric layer 206.
In this embodiment, the material of the initial gate layer 207 includes polysilicon.
Referring to fig. 9, a second patterning layer (not shown) is formed on the initial gate layer 207, wherein the second patterning layer exposes a portion of the top surface of the initial gate layer 207; and etching the initial gate layer 207 and the initial gate dielectric layer 206 by using the second patterning layer as a mask until the top surface of the substrate 200 is exposed, thereby forming the storage gate structure 208 and the transmission gate structure 209.
In this embodiment, a groove 201 is formed in the substrate 200, a storage gate structure 208 is formed on the substrate 200, and a portion of the storage gate structure 208 is located on the surface of the storage region 202 and in the groove 201, so that the pixel area occupied by the storage gate structure 208 is reduced, and the formation area of the photosensitive region 203 is correspondingly increased, thereby improving the fill factor of the pixel, and simultaneously improving the sensitivity and quantum efficiency of the image sensor, and improving the performance of the finally formed image sensor.
In this embodiment, the storage gate structure 208 and the transmission gate structure 209 respectively include a gate dielectric layer and a gate layer (not labeled) on the gate dielectric layer.
In the present embodiment, the photosensitive region 203 is formed before the storage gate structure 208 is formed; in other embodiments, the photosensitive region may also be formed after forming the storage gate structure.
In the present embodiment, after the storage gate structure 208 and the transfer gate structure 209 are formed, the second patterning layer is removed.
Referring to fig. 10, after the storage gate structure 208 and the transfer gate structure 209 are formed, a light-shielding layer 210 is formed on the storage region 202, and the light-shielding layer 210 covers a portion of the sidewall and the top surface of the storage gate structure 208.
In this embodiment, the light shielding layer 210 can reduce the light from being irradiated onto the storage region 202, thereby improving the parasitic photosensitivity of the image sensor.
In this embodiment, the light shielding layer 210 is also located on a portion of the top surface of the transfer gate structure 209.
In this embodiment, the material of the light-shielding layer 210 includes tungsten.
Referring to fig. 11, a floating diffusion region 211 is formed in the substrate 200, and the floating diffusion region 211 and the storage region 202 are respectively located at two sides of the transfer gate structure 209.
In this embodiment, the floating diffusion region 211 is formed by an ion implantation process, and the floating diffusion region 211 functions as a capacitor, so that when the transfer gate structure 209 is turned on, the charges in the storage region 202 are transferred to the floating diffusion region 211, thereby completing the conversion from the charge signal to the voltage signal.
Accordingly, an embodiment of the present invention further provides a pixel structure of an image sensor, please refer to fig. 11, including: a liner, 200; a recess 201 in the substrate 200; a storage region 202 located in the substrate 200, the storage region 202 having a first doping ion therein, the storage region 202 being located on a sidewall and a bottom surface of the groove 201; a storage gate structure 208 located on the substrate 200, wherein a portion of the storage gate structure 208 is located on the surface of the storage region 202 and located in the groove 201.
In this embodiment, through the groove 201 located in the substrate 200 and the storage gate structure 208 located on the substrate 200, part of the storage gate structure 208 is located on the surface of the storage region 202 and located in the groove 201, so that the pixel area occupied by the storage gate structure 208 is reduced, the formation area of the photosensitive region 203 is correspondingly increased, the fill factor of the pixel is further increased, meanwhile, the sensitivity and the quantum efficiency of the image sensor are also improved, and the performance of the finally formed image sensor is improved
In this embodiment, the depth of the groove 201 is 0.1 μm to 5 μm.
In the embodiment, the depth-to-width ratio of the groove 201 ranges from 0.2 to 20.
In this embodiment, the top dimension of the groove 201 is larger than the bottom dimension of the groove 201, and the directions of the top dimension and the bottom dimension are parallel to the top surface of the substrate 200.
In this embodiment, an included angle between the sidewall of the groove 201 and the top surface of the substrate 200 is 45 ° to 90 °.
In this embodiment, the storage gate structure 208 includes: the gate structure comprises a gate dielectric layer and a gate electrode layer positioned on the gate dielectric layer.
In this embodiment, the material of the gate dielectric layer includes silicon oxide.
In this embodiment, the thickness of the gate dielectric layer is 1nm to 10 nm.
In this embodiment, the material of the gate layer includes polysilicon.
In this embodiment, the method further includes: a light-shielding layer 210 is disposed on the storage region 202, and the light-shielding layer 210 covers a portion of the sidewall and the top surface of the storage gate structure 208. The light shielding layer 210 can reduce the light from irradiating the storage region 202, thereby improving the parasitic light sensitivity of the image sensor.
In this embodiment, the material of the light-shielding layer 210 includes tungsten.
In this embodiment, the first doping ions include N-type ions, and the N-type ions include: phosphorus or arsenic.
In this embodiment, the method further includes: a first passivation layer 204 on the surface of the storage region 202, wherein the first passivation layer 204 has second doped ions therein, and the second doped ions have a different conductivity type from the first doped ions.
In this embodiment, the second doping ions include P-type ions, and the P-type ions include: boron or boron difluoride.
In this embodiment, the method further includes: a photosensitive region 203 located in the substrate 200 and separated from the storage region 202, the photosensitive region 203 being adjacent to the storage gate structure 208, the photosensitive region 203 having the first doping ions therein.
In this embodiment, the method further includes: and a second passivation layer 205 on the surface of the photosensitive region 203, wherein the second passivation layer 205 has second doped ions therein, and the second doped ions have a different conductivity type from the first doped ions. The defects on the surfaces of the storage region 202 and the photosensitive region 203 can be passivated by the first passivation layer 204 and the second passivation layer 205, and the generation of dark current is reduced.
In this embodiment, the method further includes: a transfer gate structure 209 located on the substrate 200, the transfer gate structure 209 being adjacent to the storage region 202.
In this embodiment, the method further includes: a floating diffusion region 211 in the substrate 200, wherein the floating diffusion region 211 and the storage region 202 are respectively located at two sides of the transfer gate structure 209.
In this embodiment, the light shielding layer 210 is also located on a portion of the top surface of the transfer gate structure 209.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (43)
1. A pixel structure of an image sensor, comprising:
a substrate;
a recess in the substrate;
the storage region is positioned in the substrate, first doping ions are arranged in the storage region, and the storage region is positioned on the side wall and the bottom surface of the groove;
and the storage gate structure is positioned on the substrate, and part of the storage gate structure is positioned on the surface of the storage region and in the groove.
2. The pixel structure of the image sensor of claim 1, wherein the depth of the recess is 0.1 μm to 5 μm.
3. The pixel structure of claim 2, wherein the depth-to-width ratio of the recess is in the range of 0.2 to 20.
4. The pixel structure of claim 1, wherein a top dimension at said recess is greater than a bottom dimension at said recess, said top dimension and said bottom dimension being oriented parallel to said substrate top surface.
5. The pattern sensor pixel structure of claim 4, wherein the angle between the sidewalls of the recess and the top surface of the substrate is between 45 ° and 90 °.
6. The pixel structure of the image sensor of claim 1, wherein the storage gate structure comprises: the gate structure comprises a gate dielectric layer and a gate electrode layer positioned on the gate dielectric layer.
7. The pixel structure of claim 6, wherein the gate dielectric layer comprises silicon oxide.
8. The pixel structure of claim 6, wherein the gate dielectric layer has a thickness of 1nm to 10 nm.
9. The pixel structure of claim 6, wherein the gate layer comprises a material comprising polysilicon.
10. The pixel structure of the image sensor of claim 1, further comprising: and the light shielding layer is positioned on the storage region and covers part of the side wall and the top surface of the storage grid structure.
11. The pixel structure of claim 10, wherein the material of the light blocking layer comprises tungsten.
12. The pixel structure of claim 1, wherein the first dopant ions comprise N-type ions, the N-type ions comprising: phosphorus or arsenic.
13. The pixel structure of the image sensor of claim 1, further comprising: and the first passivation layer is positioned on the surface of the storage region, and second doped ions are arranged in the first passivation layer and have a different conductivity type from the first doped ions.
14. The pixel structure of claim 13, wherein said second dopant ions comprise P-type ions, said P-type ions comprising: boron or boron difluoride.
15. The pixel structure of the image sensor of claim 1, further comprising: and the photosensitive area is positioned in the substrate and is mutually separated from the storage area, the photosensitive area is adjacent to the storage grid structure, and the first doped ions are arranged in the photosensitive area.
16. The pixel structure of the image sensor of claim 15, further comprising: and the second passivation layer is positioned on the surface of the photosensitive area, and second doping ions are arranged in the second passivation layer and have different conductivity types from the first doping ions.
17. The pixel structure of the image sensor of claim 10, further comprising: a transfer gate structure on the substrate, the transfer gate structure adjacent to the storage region.
18. The pixel structure of the image sensor of claim 17, further comprising: and the floating diffusion region and the storage region are respectively positioned at two sides of the transmission grid structure.
19. The pixel structure of claim 17, wherein said light blocking layer is further on a portion of a top surface of said transfer gate structure.
20. A method for forming a pixel structure of an image sensor, comprising:
providing a substrate;
forming a groove in the substrate;
forming a storage region in the substrate, wherein the storage region is provided with first doped ions and is positioned on the side wall and the bottom surface of the groove;
and forming a storage gate structure on the substrate, wherein part of the storage gate structure is positioned on the surface of the storage region and in the groove.
21. The method of claim 20, wherein the depth of the recess is 0.1 μm to 5 μm.
22. The method as claimed in claim 21, wherein the depth-to-width ratio of the recess is in the range of 0.2 to 20.
23. The method of claim 20, wherein a top dimension of the recess is greater than a bottom dimension of the recess, and wherein the top dimension and the bottom dimension are oriented parallel to the top surface of the substrate.
24. The method of claim 23, wherein an angle between a sidewall of the recess and the top surface of the substrate is between 45 ° and 90 °.
25. The method of claim 20, wherein the memory gate structure comprises: the gate structure comprises a gate dielectric layer and a gate electrode layer positioned on the gate dielectric layer.
26. The method of claim 25, wherein the gate dielectric layer comprises silicon oxide.
27. The method of claim 25, wherein the gate dielectric layer has a thickness of 1nm to 10 nm.
28. The method of claim 25, wherein the gate layer comprises a material comprising polysilicon.
29. The method of forming a pixel structure of a graphic sensor of claim 20, further comprising, after forming the memory gate structure: and forming a light shielding layer on the storage region, wherein the light shielding layer covers part of the side wall and the top surface of the storage grid structure.
30. The method of claim 29, wherein the light-shielding layer comprises tungsten.
31. The method of claim 20, wherein the first dopant ions comprise N-type ions, the N-type ions comprising: phosphorus or arsenic.
32. The method of claim 20, wherein the method of forming the storage region comprises: and carrying out ion implantation treatment of the first doping ions on the substrate exposed by the groove to form the storage region.
33. The method of claim 32, wherein the first dopant ion is implantedThe parameters of the input process include: the implantation dose of the first doping ions is 3E11atm/cm2～2E13atm/cm2(ii) a The implantation angle of the first doped ions is 0-45 degrees.
34. The method of claim 20, further comprising, prior to forming the memory gate structure: and forming a first passivation layer on the storage region, wherein the first passivation layer is internally provided with second doped ions, and the second doped ions are different from the first doped ions in conductivity type.
35. The method of forming a pixel structure of a pattern sensor of claim 34, further comprising, prior to forming the memory gate structure: and forming a photosensitive area separated from the storage area in the substrate, wherein the photosensitive area is adjacent to the storage grid structure, and the photosensitive area is internally provided with the first doped ions.
36. The method of forming a pixel structure of a pattern sensor of claim 35, further comprising, after forming the photosensitive region: and forming a second passivation layer on the surface of the photosensitive area, wherein the second passivation layer is internally provided with the second doping ions.
37. The method of claim 34 or 36, wherein the second dopant ions comprise P-type ions, the P-type ions comprising: boron or boron difluoride.
38. The method of claim 36, wherein the first passivation layer and the second passivation layer are formed simultaneously, and wherein the method of forming the first passivation layer and the second passivation layer comprises: and carrying out ion implantation treatment on the second doped ions on the substrate to form the first passivation layer and the second passivation layer.
39. The method of claim 38, wherein the doping of the second dopant ion by the ion implantation process comprises: the second doping ion implantation dosage is 3E11atm/cm2～5E13atm/cm2(ii) a The implantation energy of the second doped ions is 5 KeV-120 KeV; the implantation angle of the second doped ions is 0-45 degrees.
40. The method of forming a pixel structure of a pattern sensor of claim 29, further comprising, during the forming of the memory gate structure: forming a transfer gate structure on the substrate, the transfer gate structure being adjacent to the storage region.
41. The method of forming a pixel structure of a graphic sensor of claim 40, further comprising, after forming the transfer gate structure: and forming a floating diffusion region in the substrate, wherein the floating diffusion region and the storage region are respectively positioned at two sides of the transmission grid structure.
42. The method as claimed in claim 40, wherein the light-shielding layer is further disposed on a portion of a top surface of the transfer gate structure.
43. The method of claim 25, wherein the storage region is formed before or after forming the gate dielectric layer.
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