CN110620125A - Structure for reducing random telegraph noise in CMOS image sensor and forming method - Google Patents
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Abstract
The invention provides a structure for reducing random telegraph noise in a CMOS image sensor and a forming method thereof, wherein a transfer tube positioned on an epitaxial layer and a photodiode positioned on one side of the transfer tube are provided; the photodiode is provided with a pinning layer, silicon oxide layers with different thicknesses are arranged below the grid electrode of the transfer tube, and the thickness of the silicon oxide layer below the grid electrode of the transfer tube close to one end of the pinning layer is smaller than that of the silicon oxide layer at the rest part below the grid electrode. The invention utilizes the method of forming different channel regions with different silicon oxide thicknesses to simultaneously meet the requirements of reducing electron generation-recombination rate by using the low consumption of the transfer tube and the pinning layer, inhibiting the current from a floating diffusion point to the photodiode, reducing the random telegraph noise and dark current in the processes of photoelectron transfer and integration time, realizing more flexible adjustment of the transfer tube, more effectively inhibiting the random telegraph noise, and improving the dynamic range of a pixel unit and the response under low light.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a structure and a forming method for reducing random telegraph noise in a CMOS image sensor.
Background
The CMOS Image Sensor (CIS) has many advantages over the existing CCD due to its compatibility with existing ic fabrication processes. The CMOS image sensor can integrate the driving circuit and the pixels, simplify the hardware design and reduce the power consumption of the system. The CIS can take out the electric signal while collecting the optical signal, and can also process image information in real time, and the speed is faster than that of a CCD image sensor. CMOS image sensors also have the advantages of low cost, large bandwidth, anti-blooming, flexibility of access, and large fill factor.
Conventional active pixels use photodiodes as image sensing devices. A typical active pixel cell is made up of three transistors and a P +/N +/P-photodiode, which is compatible with standard CMOS fabrication processes. In the spatial distribution design of doping for the photodiode, we must also keep the space charge region away from the region where recombination centers such as crystal defects are concentrated to reduce the dark current of the pixel. Fig. 1 is a schematic diagram showing a 4T pixel structure at the rear end of a back-illuminated image sensor in the prior art, and the full-well capacity (the ability of the photodiode to store charges) is improved due to the large size of the photodiode on a large-sized pixel unit, so that more electrons can be stored, the dynamic range (the ratio of the brightest to darkest condition) of the pixel unit can be improved, the influence of noise on the pixel is reduced, and the signal-to-noise ratio is improved.
With the increasing use of CIS for monitoring, automotive auxiliary systems, and night vision systems, the imaging quality of CIS at low light intensity is more and more demanding, on one hand, the area of the pixel is increased to increase the light input amount, and on the other hand, the dynamic range of the pixel is improved by design optimization to convert more low-intensity light, such as extending the exposure time, sampling many times, double conversion factors, or pixel combination schemes. However, these methods of increasing the dynamic range do not eliminate the original factors affecting the pixel quality, especially Dark Current (DC) and Random Telegraph noise (RTS), but many designs will also increase these effects, for example, increasing the exposure time increases the Dark Current, as shown in fig. 2, and there are many improvements for the effects at low light intensity, as shown in fig. 3, applying a negative voltage to the transfer tube can reduce RTS, and suspected that the negative voltage depletes the pinned layer (PPD) in the area where the transfer tube overlaps with the Photodiode, and reduces the probability of electron generation-recombination, thereby improving the corresponding RTS (inversion of Dark Current Random Photodiode Signal in Photodiode CMOS Image sensors.2011 IEEE), as shown in fig. 4a and fig. 4b, the inverted layer generated by the high negative voltage of the transfer tube during integration keeps the depletion region away from the interface, RTS is reduced; in fig. 4c, the depletion region is far away from the interface under negative pressure, but at the same time too low negative pressure causes accumulated positive charge under the transfer tube, turning on the floating diffusion point (FD) and the Photodiode (PD), creating a leakage, resulting in current entering from FD, increasing dark current or random noise during PD integration.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a structure and a forming method for reducing random telegraph noise in a CMOS image sensor, which is used to solve the problem of random telegraph noise induced by the overlapping area of the transfer tube and the photodiode pinning layer in the CMOS image sensor in the prior art for the image quality under low light.
To achieve the above and other related objects, the present invention provides a structure for reducing random telegraph noise in a CMOS image sensor, the structure comprising at least: a transfer tube on the epitaxial layer and a photodiode at one side of the transfer tube; the upper surface of the photodiode is provided with a pinning layer; silicon oxide layers with different thicknesses are arranged below the polycrystalline silicon grid of the transfer tube, wherein the thickness of the silicon oxide layer below the polycrystalline silicon grid of the transfer tube close to one end of the pinning layer is smaller than that of the silicon oxide layer below the rest part of the polycrystalline silicon grid of the transfer tube.
Preferably, the structure further comprises: a reset tube located on the epitaxial layer; two sides of the grid of the reset tube are respectively provided with an N + region; the N + regions are positioned in the P trap on the epitaxial layer, one of the N + regions is positioned in the other side region of the polysilicon grid of the transfer tube, and the N + region forms a floating diffusion point.
Preferably, the silicon oxide layer is arranged in a region between the upper part of the floating diffusion point and the polysilicon gate of the transfer tube, and the thickness of the silicon oxide layer in the region is the same as that of the silicon oxide layer under the polysilicon gate of the transfer tube.
Preferably, the upper surface of the pinning layer is provided with a silicon oxide layer with the same thickness as the silicon oxide layer of the rest part under the polysilicon gate of the transfer tube; the polycrystalline silicon grid of the transfer tube is provided with a side wall; and thin film layers are arranged on the upper surface of the silicon oxide layer exposed outside on the pinning layer, the transfer pipe polysilicon grid and the side wall thereof.
Preferably, the N + region on the floating diffusion point is connected with an amplifying tube, the amplifying tube is connected with a selection tube, and the grid electrode of the selection tube is connected with a voltage VDD; and the N + region on the other side of the reset tube is connected with a voltage VDD.
The invention also provides a forming method of the structure for reducing random telegraph noise in the CMOS image sensor, which at least comprises the following steps: providing an epitaxial layer, wherein a photodiode is arranged on the epitaxial layer; secondly, injecting nitrogen ions into one end region of the photodiode on the upper surface of the epitaxial layer; growing a silicon oxide layer on the upper surface of the epitaxial layer, wherein a thin silicon oxide layer is formed in the nitrogen ion implanted region, a thick silicon oxide layer is formed in the rest part, and the thickness of the thin silicon oxide layer is smaller than that of the thick silicon oxide layer; forming a polysilicon grid of the transfer tube covering a part of the thin layer of silicon oxide and a part of the thick layer of silicon oxide; fifthly, ion implantation is carried out on the upper surface of the photodiode and the lower surface of the silicon oxide layer to form a pinning layer; and sixthly, forming a polysilicon gate side wall of the transfer tube, and covering a thin film layer on the exposed silicon oxide layer and the polysilicon gate of the transfer tube.
Preferably, the nitrogen ion implantation in the second step is performed by doping nitrogen ions in an end region of the photodiode on the upper surface of the epitaxial layer using a photomask.
Preferably, the epitaxial layer in the first step is subjected to ion implantation for forming an N + region, wherein the N + region is positioned in a region on one side of the polysilicon gate of the transfer tube, and forms a floating diffusion point.
Preferably, when a negative voltage is applied to the polysilicon gate of the transfer pipe, the electric field of the channel region under the thin silicon oxide layer is enhanced.
As described above, the structure and the forming method for reducing random telegraph noise in the CMOS image sensor according to the present invention have the following advantages: the invention provides a method for forming different channel regions by using different silicon oxide thicknesses, which simultaneously reduces the electron generation-recombination rate by using the low consumption of a transfer tube and a pinning layer and inhibits the current from a floating diffusion point to a photodiode, thereby achieving the purposes of reducing the random telegraph noise (RTS) and the dark current in the processes of photoelectron transfer and integration time, realizing more flexible adjustment of a transfer tube, inhibiting the random telegraph noise (RTS) more effectively and improving the dynamic range of a pixel unit and the response under low light.
Drawings
FIG. 1 is a schematic diagram of a 4T pixel structure at the back end of a prior art backside illuminated image sensor;
FIG. 2 is a diagram illustrating dark current as a function of integration time in a prior art CMOS image sensor structure;
FIG. 3 is a diagram illustrating the variation of dark current with the voltage of a transfer transistor in a CMOS image sensor structure in the prior art;
FIG. 4a is a schematic structural diagram illustrating a transfer tube applying a negative high voltage in a CMOS image sensor structure according to the prior art;
FIG. 4b is a schematic diagram showing the corresponding depletion region when the gate voltage of the transfer transistor in FIG. 4a is 0V;
FIG. 4c is a schematic diagram of a depletion region corresponding to the gate voltage of the transfer transistor in FIG. 4a being a negative high voltage;
FIG. 5 is a schematic diagram of a CMOS image sensor according to the present invention;
FIG. 6 is a schematic top plan view of the CMOS image sensor structure of FIG. 5 according to the present invention;
FIG. 7 is a graph showing the thickness of silicon oxide as a function of nitrogen dose for various oxidation times in accordance with the present invention;
FIG. 8 is a graph showing the thickness of silicon oxide as a function of oxidation time for different nitrogen doses in accordance with the present invention;
FIG. 9 is a schematic diagram showing the potential of a transfer tube and a photodiode when the applied voltage of the transfer tube is 0V in a CMOS image sensor in the prior art;
FIG. 10 is a schematic diagram showing the potentials of a transfer tube and a photodiode when a negative high voltage is applied to the transfer tube in a CMOS image sensor in the prior art;
fig. 11 is a schematic diagram showing the potentials of the transfer tube and the photodiode when a negative high voltage is applied to the transfer tube in the CMOS image sensor of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 5 to 11. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The present invention provides a structure for reducing random telegraph noise in a CMOS image sensor, as shown in fig. 5, fig. 5 is a schematic structural diagram of the CMOS image sensor of the present invention. The structure at least comprises: a transfer tube on the epitaxial layer 01 and a photodiode 02 at one side of the transfer tube; the upper surface of the photodiode 02 is provided with a pinning layer 03; silicon oxide layers with different thicknesses are arranged below the polycrystalline silicon grid 04 of the transfer tube, wherein the thickness of the silicon oxide layer (thin silicon oxide 06) below the polycrystalline silicon grid 04 of the transfer tube close to one end of the pinning layer 03 is smaller than that of the silicon oxide layer (thick silicon oxide 05) below the rest part of the polycrystalline silicon grid 04 of the transfer tube. Further, the structure of the present invention further comprises: a reset tube (in fig. 5, the reset tube is shown, and see fig. 1 can be seen) located on the epitaxial layer 01; two sides of the grid of the reset tube are respectively provided with an N + region; the N + regions are located in the P-well on the epitaxial layer 01, one of the N + regions 07 is located in the other side region of the polysilicon gate 04 of the transfer tube, which forms a floating diffusion point 10.
Furthermore, the silicon oxide layer is arranged in the area between the upper part of the floating diffusion point 10 and the polysilicon gate 04 of the transfer tube, and the thickness of the silicon oxide layer in the area is the same as that of the silicon oxide layer (thick silicon oxide 05) in the rest part under the polysilicon gate 04 of the transfer tube.
Preferably, the polysilicon gate 04 of the transfer tube is provided with a side wall; and a thin film layer 08 is arranged on the upper surface of the silicon oxide layer exposed outside on the pinning layer 03, the transfer pipe polysilicon gate 04 and the side wall thereof. That is, one part of the silicon oxide layer on the pinning layer 03 is the pinning layer and the thin silicon oxide layer under the polysilicon gate of the transfer tube near the photodiode region, the other part is the thick silicon oxide layer 05, the part of the thick silicon oxide layer which is not covered by the polysilicon gate and the sidewall of the transfer tube is defined as the exposed part, the thin film layer 08 is arranged on the part, and the sidewall of the polysilicon gate of the transfer tube and the upper surface of the sidewall are both covered with the thin film layer 08.
Further, the N + region 07 on the floating diffusion point 10 is connected to an amplifier tube (fig. 5 shows a reset tube, see fig. 1), which is connected to a select tube, and the gate of the select tube is connected to a voltage VDD; and the N + region on the other side of the reset tube is connected with a voltage VDD.
As shown in fig. 6, fig. 6 is a schematic top plan view of the CMOS image sensor structure of fig. 5 according to the present invention; in the projected pattern, the pixel region 12 in the active region 11 has a portion of the thin silicon oxide 06 beside the original polysilicon region 13.
The invention also provides a method for forming the structure of random telegraph noise in the CMOS image sensor, which at least comprises the following steps:
step one, as shown in fig. 5, providing an epitaxial layer 01, wherein a photodiode 02 is arranged on the epitaxial layer 01; furthermore, the epitaxial layer 01 in the first step is subjected to ion implantation for forming an N + region 07, wherein the N + region 07 is positioned in a region on one side of the polysilicon gate of the transfer tube, and a floating diffusion point 10 is formed.
Step two, injecting nitrogen ions into one end region of the photodiode 02 on the upper surface of the epitaxial layer 01; furthermore, the nitrogen ion implantation in the second step is performed by doping nitrogen ions in an end region of the photodiode on the upper surface of the epitaxial layer using a photomask. The region doped with nitrogen ions is the polysilicon gate 04 of the transfer transistor and the thin silicon oxide 06 near the photodiode pinning layer 03 as shown in fig. 5.
Step three, referring to fig. 5, growing a silicon oxide layer on the upper surface of the epitaxial layer 01, wherein a thin silicon oxide 06 is formed in the nitrogen ion implanted region, and a thick silicon oxide 05 is formed in the rest part, wherein the thickness of the thin silicon oxide 06 is smaller than that of the thick silicon oxide 05; since the region where the thin silicon oxide layer is formed has been subjected to the nitrogen ion doping performed in step two, the oxidation rate of the region is decreased, thereby forming a thin silicon oxide layer. As shown in fig. 7 and 8, wherein fig. 7 is a graph showing the thickness of silicon oxide according to the present invention as a function of nitrogen dose at different oxidation times, and fig. 8 is a graph showing the thickness of silicon oxide according to the present invention as a function of oxidation time at different nitrogen doses.
Step four, referring to fig. 5, forming a polysilicon gate 04 of the transfer pipe covering a part of the thin silicon oxide 06 and a part of the thick silicon oxide 05. That is, a part of the finally formed thin layer of silicon oxide 06 is located under the polysilicon gate 04 of the transfer tube, and another part of the thick layer of silicon oxide 05 is located under the polysilicon gate 04 of the transfer tube.
Fifthly, ion implantation is carried out on the upper surface of the photodiode and the lower surface of the silicon oxide layer to form a pinning layer; the pinning layer is partially overlapped with the side wall area of the polysilicon grid of the transfer tube; a thin layer of silicon oxide 06 in step three is formed adjacent to the region of this partial overlap.
And sixthly, as shown in fig. 5, forming a polysilicon gate side wall of the transfer tube, and covering a thin film layer 08 on the exposed silicon oxide layer and the polysilicon gate of the transfer tube. That is, one part of the silicon oxide layer on the pinning layer 03 is a thin silicon oxide layer 06 near the overlapping region of the pinning layer and the polysilicon gate sidewall of the transfer tube, the other part is a thick silicon oxide layer 05, the part of the thick silicon oxide layer 05 which is not covered by the polysilicon gate and sidewall of the transfer tube is defined as the part exposed outside, the part is provided with a thin film layer 08, and the polysilicon gate sidewall of the transfer tube and the upper surface of the polysilicon gate sidewall of the transfer tube are both covered with the thin film layer 08.
Referring to fig. 9 to 11, fig. 9 is a schematic diagram illustrating potentials of a transfer tube and a photodiode when a voltage applied to the transfer tube is 0V in a CMOS image sensor in the prior art, and potentials of the photodiode, Tx and the Photodiode (PD) when 0V is applied to the transfer tube (Tx) in the prior art photodiode integration. Electrons entering Tx enter PD with a certain probability through generation-recombination, and become unstable factors.
Fig. 10 is a schematic diagram showing the potentials of the transfer tube and the photodiode when a negative high voltage is applied to the transfer tube in the CMOS image sensor in the prior art, and the potentials of the photodiode, Tx and PD when a negative voltage is applied to Tx in the conventional structure photodiode integration. The probability that an electron entering Tx will be generated and recombined into PD increases further, which becomes an unstable factor.
Fig. 11 is a schematic diagram showing the potentials of the transfer tube and the photodiode when a negative high voltage is applied to the transfer tube in the CMOS image sensor of the present invention. The improved structure of the invention integrates the potential of the photodiode, Tx and PD when Tx applies negative voltage. Since the thin layer regions can enhance the electric field, these regions are far away from the depletion region, thereby causing a reduction in the PD region-recombination. Meanwhile, the electric leakage from the FD to the photodiode PD can be reduced, and the random telegraph noise (RTS) can be adjusted more freely.
Further, when negative pressure is applied to the polysilicon gate of the transfer tube, the electric field of the channel region under the thin silicon oxide layer is enhanced. The oxidation speed of silicon oxide under the original polysilicon is reduced by N2 ion implantation through a mask plate, so that a thinner silicon oxide layer is formed, a stronger electric field can be realized under the same negative voltage, a depletion region is far away when a Photodiode (PD) is integrated, the probability of electron generation-recombination is reduced, and the generation of RTS is reduced. Meanwhile, an inversion layer formed by thicker silicon oxide is thin, so that the flow of electrons from a floating diffusion point (FD) to a Photodiode (PD) can be effectively blocked, and the dark current during collection is reduced.
In summary, the present invention provides a method for forming different channel regions with different thicknesses of silicon oxide to simultaneously reduce the electron generation-recombination rate with low consumption of the transfer transistor and the pinning layer, and suppress the current from the floating diffusion point to the photodiode, thereby achieving the purpose of reducing the random telegraph noise (RTS) and the dark current during the photoelectron transfer and integration time, realizing more flexible adjustment of the transfer transistor, more effectively suppressing the random telegraph noise (RTS), and improving the dynamic range of the pixel unit and the response under low light. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
1. A structure for reducing random telegraph noise in a CMOS image sensor, the structure comprising at least:
a transfer tube on the epitaxial layer and a photodiode at one side of the transfer tube; the upper surface of the photodiode is provided with a pinning layer; silicon oxide layers with different thicknesses are arranged below the polycrystalline silicon grid of the transfer tube, wherein the thickness of the silicon oxide layer below the polycrystalline silicon grid of the transfer tube close to one end of the pinning layer is smaller than that of the silicon oxide layer below the rest part of the polycrystalline silicon grid of the transfer tube.
2. The structure for reducing random telegraph noise in a CMOS image sensor according to claim 1, wherein: the structure further includes: a reset tube located on the epitaxial layer; two sides of the grid of the reset tube are respectively provided with an N + region; the N + regions are positioned in the P trap on the epitaxial layer, one of the N + regions is positioned in the other side region of the polysilicon grid of the transfer tube, and the N + region forms a floating diffusion point.
3. The structure for reducing random telegraph noise in a CMOS image sensor according to claim 2, wherein: the silicon oxide layer is arranged in a region between the upper portion of the floating diffusion point and the polycrystalline silicon grid electrode of the transfer tube, and the thickness of the silicon oxide layer in the region is the same as that of the silicon oxide layer under the other portion of the polycrystalline silicon grid electrode of the transfer tube.
4. The structure for reducing random telegraph noise in a CMOS image sensor as in claim 3, wherein: the upper surface of the pinning layer is provided with a silicon oxide layer with the same thickness as the silicon oxide layer of the rest part under the polycrystalline silicon grid of the transfer tube; the polycrystalline silicon grid of the transfer tube is provided with a side wall; and thin film layers are arranged on the upper surface of the silicon oxide layer exposed outside on the pinning layer, the transfer pipe polysilicon grid and the side wall thereof.
5. The structure for reducing random telegraph noise in a CMOS image sensor as in claim 4, wherein: the N + region on the floating diffusion point is connected with an amplifying tube, the amplifying tube is connected with a selection tube, and the grid electrode of the selection tube is connected with a voltage VDD; and the N + region on the other side of the reset tube is connected with a voltage VDD.
6. The method of forming a structure for reducing random telegraph noise in a CMOS image sensor according to any one of claims 1 to 5, wherein the method comprises at least the steps of:
providing an epitaxial layer, wherein a photodiode is arranged on the epitaxial layer;
secondly, injecting nitrogen ions into one end region of the photodiode on the upper surface of the epitaxial layer;
growing a silicon oxide layer on the upper surface of the epitaxial layer, wherein a thin silicon oxide layer is formed in the nitrogen ion implanted region, a thick silicon oxide layer is formed in the rest part, and the thickness of the thin silicon oxide layer is smaller than that of the thick silicon oxide layer;
forming a polysilicon grid of the transfer tube covering a part of the thin layer of silicon oxide and a part of the thick layer of silicon oxide;
fifthly, ion implantation is carried out on the upper surface of the photodiode and the lower surface of the silicon oxide layer to form a pinning layer;
and sixthly, forming a polysilicon gate side wall of the transfer tube, and covering a thin film layer on the exposed silicon oxide layer and the polysilicon gate of the transfer tube.
7. The structure for reducing random telegraph noise in a CMOS image sensor according to claim 6, wherein: and in the second step, nitrogen ion implantation is carried out in a mode that a photomask is utilized to carry out nitrogen ion doping on one end region of the photodiode on the upper surface of the epitaxial layer.
8. The structure for reducing random telegraph noise in a CMOS image sensor according to claim 7, wherein: and performing ion implantation for forming an N + region on the epitaxial layer in the first step, wherein the N + region is positioned in a region on one side of the polycrystalline silicon grid electrode of the transfer tube to form a floating diffusion point.
9. The structure for reducing random telegraph noise in a CMOS image sensor according to claim 8, wherein: and when negative pressure is applied to the polysilicon gate of the transfer tube, the electric field of the channel region under the thin silicon oxide layer is enhanced.
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| CN201910897870.6A CN110620125A (en) | 2019-09-23 | 2019-09-23 | Structure for reducing random telegraph noise in CMOS image sensor and forming method |
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