CN110444556B - CMOS sensor and method for forming CMOS sensor - Google Patents
CMOS sensor and method for forming CMOS sensor Download PDFInfo
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- CN110444556B CN110444556B CN201910816560.7A CN201910816560A CN110444556B CN 110444556 B CN110444556 B CN 110444556B CN 201910816560 A CN201910816560 A CN 201910816560A CN 110444556 B CN110444556 B CN 110444556B
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 230000000903 blocking effect Effects 0.000 claims abstract description 34
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 238000002955 isolation Methods 0.000 claims abstract description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
- H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
Abstract
The present invention provides a CMOS sensor comprising: the invention also provides a forming method of the CMOS sensor, which comprises the following steps: forming a semiconductor device; forming a charge blocking layer on the semiconductor device; forming a gate structure on the semiconductor device and on one side of the charge blocking layer; forming an isolation layer on the charge blocking layer and the gate structure. In the CMOS sensor and the forming method of the CMOS sensor provided by the invention, the formed charge blocking layer can block positive charges generated by the isolating layer, can block charges in the silicon nitride layer, reduces the depletion of the charges on the pinning P-type layer, strengthens the pinning P-type layer, inhibits the combination of electrons in the photodiode and a surface state, and thus can reduce dark current in the photodiode.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a CMOS (complementary metal oxide semiconductor) sensor and a forming method of the CMOS sensor.
Background
The CMOS Image Sensor (CIS) has many advantages over the existing CCD due to its compatibility with existing ic fabrication processes. The CMOS image sensor can integrate the driving circuit and the pixels, simplify the hardware design and reduce the power consumption of the system. The CMOS image sensor can take out the electric signal while collecting the optical signal, and can process the image information in real time, and the speed is faster than that of the CCD image sensor. CMOS image sensors also have the advantages of low cost, large bandwidth, anti-blooming, flexibility of access, and large fill factor.
Conventional active pixels employ photodiodes as CMOS image sensing devices. A typical active pixel cell is composed of three transistors and a P +/N +/P-photodiode, which is suitable for the standard CMOS image sensor fabrication process. In the design of the spatial distribution of doping for the photodiode, it is also necessary to keep the space charge region away from the region where recombination centers such as crystal defects are concentrated to reduce the dark current of the pixel. When illuminated, the photodiode PD generates charge, while the transfer tube TX is in the off state. The transfer tube is then opened to transfer the charge stored in the photodiode to the floating node, after which the transfer tube is closed and waits for the next light entry. The charge signal on the floating node FD is then used to adjust the amplifying transistor. After readout, a reset transistor RST with a reset gate resets the floating point to a reference voltage. Due to the fact that the size of the photodiode is large, the full-well capacity (the capacity of the photodiode for storing charges) is improved on a large-size pixel unit, more electrons can be stored, the dynamic range (the ratio of the brightest condition to the darkest condition) of the pixel unit can be improved, the influence of noise on the pixel is reduced, and the signal-to-noise ratio is improved.
In the existing structure, a certain electron hole pair is generated due to the short glow wavelength in the subsequent etching, electrons can be guided away due to good conductivity, and corresponding vacant sites are left to form a thin layer with positive charges. This region will deplete the P-type portion of the original heavily doped pinning layer through the underlying silicon oxide, resulting in a reduction in the corresponding pinning effect of this layer, generating additional dark current.
Disclosure of Invention
The invention aims to provide a CMOS sensor and a forming method of the CMOS sensor.
In order to achieve the above object, the present invention provides a CMOS sensor comprising: the semiconductor device includes a semiconductor device, a charge blocking layer and a gate structure on the semiconductor device, and an isolation layer on the gate structure and the charge blocking layer.
Optionally, in the CMOS sensor, the semiconductor device includes a substrate, a shallow trench isolation structure located in the substrate, a photodiode, and a pinned P-type layer located on the photodiode.
Optionally, in the CMOS sensor, the substrate is a P-type substrate.
Optionally, in the CMOS sensor, the charge blocking layer and the pinned P-type layer are partially opposed to each other.
Optionally, in the CMOS sensor, the isolation layer is made of silicon nitride.
The invention also provides a method for forming the CMOS sensor, which comprises the following steps:
forming a semiconductor device;
forming a charge blocking layer on the semiconductor device;
forming a gate structure on the semiconductor device and on one side of the charge blocking layer;
forming an isolation layer on the charge blocking layer and the gate structure.
Optionally, in the method for forming a CMOS sensor, the method for forming a semiconductor device includes: providing a semiconductor substrate; forming a shallow trench isolation structure in the substrate; forming a diode N-type region and a reset tube region in the substrate through ion implantation; and forming a pinned P-type layer on the diode N-type region.
Optionally, in the method for forming a CMOS sensor, the method for forming a charge blocking layer includes: and forming a polycrystalline silicon layer on the surface of the semiconductor device, and etching part of the polycrystalline silicon layer to form a charge blocking layer which is positioned on the upper part of the pinning P-type layer and is opposite to the pinning P-type layer.
Optionally, in the method for forming a CMOS sensor, the method for forming a gate structure includes: and etching the residual polysilicon layer to form a gate structure.
Optionally, in the method for forming a CMOS sensor, the method for forming a CMOS sensor further includes: and performing N-type and P-type ion implantation on the shallow layer of the photodiode.
In the CMOS sensor and the forming method of the CMOS sensor provided by the invention, the formed charge blocking layer can block positive charges generated by the isolating layer, can block charges in the silicon nitride layer, reduces the depletion of the charges on the pinning P-type layer, strengthens the pinning P-type layer, inhibits the combination of electrons in the photodiode and a surface state, and thus can reduce dark current in the photodiode.
Drawings
FIG. 1 is a flow chart of a method of forming a CMOS sensor of an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of a CMOS sensor in accordance with an embodiment of the invention;
in the figure: 110-substrate, 120-shallow trench isolation structure, 130-photodiode, 140-pinned P-type layer, 150-charge blocking layer, 160-gate structure, 170-isolation layer.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. Advantages and features of the present invention will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the following, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
The present invention provides a CMOS sensor comprising: the semiconductor device includes a semiconductor device, a charge blocking layer and a gate structure on the semiconductor device, and an isolation layer on the gate structure and the charge blocking layer.
Referring to fig. 1, the present invention also provides a method for forming a CMOS sensor, including:
s11: forming a semiconductor device;
s12: forming a charge blocking layer on the semiconductor device;
s13: forming a gate structure on the semiconductor device and on one side of the charge blocking layer;
s14: forming an isolation layer on the charge blocking layer and the gate structure.
Specifically, referring to fig. 2, a substrate 110 is provided, the substrate 110 is a P-type substrate, and a shallow trench isolation structure 120 is formed on the substrate 110.
A photodiode 130 is formed within the substrate 110, and a pinned P-type layer 140 is formed on the photodiode 130.
A gate polysilicon layer is formed on the surface of the substrate 110. The polysilicon layer may be divided into two portions, a first portion of the polysilicon layer is etched to form a charge blocking layer 150, the charge blocking layer 150 is partially opposite the pinned P-type layer 140, and a second portion of the polysilicon layer is etched to form a gate structure 160.
An isolation layer 170 is formed to cover the charge blocking layer 150 and the gate structure 160. The isolation layer 170 is made of silicon nitride, and when the isolation layer 170 made of silicon nitride generates positive charges during operation, the charge blocking layer 150 according to the embodiment of the present invention is N-type, so that the influence of the positive charges in the isolation layer 170 can be blocked, and the charge blocking layer 150 can improve the charge problem of plasma caused by a subsequent process by applying negative pressure under the condition that the subsequent process is limited. The damage of the subsequent plasma can be effectively reduced.
Finally, shallow N and P type ions are implanted into the photodiode 130.
In summary, in the CMOS sensor and the method for forming a CMOS sensor according to the embodiments of the present invention, the formed charge blocking layer can block positive charges generated by the isolation layer, block charges in the silicon nitride layer, reduce depletion of the charges on the pinned P-type layer, and enhance the pinned P-type layer, so as to suppress combination of electrons in the photodiode with a surface state, thereby reducing dark current in the photodiode.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. A CMOS sensor, comprising: the semiconductor device, a charge blocking layer and a grid structure which are positioned on the semiconductor device and an isolating layer which is positioned on the grid structure and the charge blocking layer; the charge blocking layer is a polycrystalline silicon layer and blocks the influence of charges in the isolating layer; the semiconductor device comprises a substrate, a shallow trench isolation structure positioned in the substrate, a photodiode and a pinned P-type layer positioned on the photodiode.
2. The CMOS sensor of claim 1, wherein the substrate is a P-type substrate.
3. The CMOS sensor of claim 1, wherein the charge blocking layer and the pinned P-type layer are partially opposed.
4. The CMOS sensor of claim 1, wherein the isolation layer is silicon nitride.
5. A method for forming a CMOS sensor based on the CMOS sensor as claimed in any one of claims 1 to 4, comprising:
forming a semiconductor device;
forming a charge blocking layer on the semiconductor device;
forming a gate structure on the semiconductor device and on one side of the charge blocking layer;
forming an isolation layer on the charge blocking layer and the gate structure; the method of forming a semiconductor device includes: providing a semiconductor substrate; forming a shallow trench isolation structure in the substrate; forming a diode N-type region and a reset tube region in the substrate through ion implantation; and forming a pinned P-type layer on the diode N-type region.
6. The method of forming a CMOS sensor of claim 5, wherein the method of forming a charge blocking layer comprises: and forming a polycrystalline silicon layer on the surface of the semiconductor device, and etching part of the polycrystalline silicon layer to form a charge blocking layer which is positioned on the upper part of the pinning P-type layer and is opposite to the pinning P-type layer.
7. The method of forming the CMOS sensor of claim 6, wherein the method of forming the gate structure comprises: and etching the residual polysilicon layer to form a gate structure.
8. The method of forming a CMOS sensor of claim 7, further comprising: and performing N-type and P-type ion implantation on the shallow layer of the photodiode.
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| CN201910816560.7A CN110444556B (en) | 2019-08-30 | 2019-08-30 | CMOS sensor and method for forming CMOS sensor |
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| CN201910816560.7A CN110444556B (en) | 2019-08-30 | 2019-08-30 | CMOS sensor and method for forming CMOS sensor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6534356B1 (en) * | 2002-04-09 | 2003-03-18 | Taiwan Semiconductor Manufacturing Company | Method of reducing dark current for an image sensor device via use of a polysilicon pad |
| US7071505B2 (en) * | 2003-06-16 | 2006-07-04 | Micron Technology, Inc. | Method and apparatus for reducing imager floating diffusion leakage |
| JP4867152B2 (en) * | 2004-10-20 | 2012-02-01 | ソニー株式会社 | Solid-state image sensor |
| US8018015B2 (en) * | 2005-06-29 | 2011-09-13 | Micron Technology, Inc. | Buried conductor for imagers |
| US8816462B2 (en) * | 2012-10-25 | 2014-08-26 | Omnivision Technologies, Inc. | Negatively charged layer to reduce image memory effect |
| CN103208502A (en) * | 2013-03-15 | 2013-07-17 | 上海华力微电子有限公司 | Complementary Metal-Oxide-Semiconductor Transistor (CMOS) image sensor and production method thereof |
| CN103441133B (en) * | 2013-08-30 | 2016-01-27 | 格科微电子（上海）有限公司 | The method of back side illumination image sensor and reduction back side illumination image sensor dark current |
| CN103855178B (en) * | 2014-03-11 | 2016-07-06 | 格科微电子（上海）有限公司 | Imageing sensor |
| CN105185747B (en) * | 2015-09-25 | 2018-05-01 | 上海华力微电子有限公司 | A kind of integrated technique for reducing cmos image sensor white pixel |
| CN207781597U (en) * | 2017-11-24 | 2018-08-28 | 上海华力微电子有限公司 | A kind of cmos image sensor for improving white pixel |
| CN108493206B (en) * | 2018-04-27 | 2020-10-02 | 上海集成电路研发中心有限公司 | CMOS image sensor for improving quantum efficiency |
| CN109461750A (en) * | 2018-11-13 | 2019-03-12 | 德淮半导体有限公司 | Imaging sensor and the method for manufacturing imaging sensor |
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