CN109461750A - Imaging sensor and the method for manufacturing imaging sensor - Google Patents
Imaging sensor and the method for manufacturing imaging sensor Download PDFInfo
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- CN109461750A CN109461750A CN201811342765.8A CN201811342765A CN109461750A CN 109461750 A CN109461750 A CN 109461750A CN 201811342765 A CN201811342765 A CN 201811342765A CN 109461750 A CN109461750 A CN 109461750A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14687—Wafer level processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
This disclosure relates to a kind of imaging sensor, comprising: form photodiode in the semiconductor substrate, the photodiode includes: the electric charge collecting region with the first conduction type；And the pinned surface layer with second conduction type opposite with first conduction type, the pinned surface layer is located on the electric charge collecting region, wherein, the pinned surface layer at least partly by the second conduction type in the semiconductor substrate carrier assemble and formed.Present disclosure also relates to a kind of methods for manufacturing imaging sensor.The disclosure can reduce the dark current of imaging sensor.
Description
Technical field
This disclosure relates to technical field of semiconductors, it particularly relates to a kind of imaging sensor and manufacture imaging sensor
Method.
Background technique
It include photodiode in the pixel unit of cmos image sensor.Particularly, the pixel of cmos image sensor
It include pinned photodiode in unit.Pinned photodiode can reduce dark current, can also increase the quantity of electric charge of accumulation.
Accordingly, there exist the demands to new technology.
Summary of the invention
The method that the first purpose of the disclosure is to provide the new imaging sensor of one kind and manufactures imaging sensor.
According to the disclosure in a first aspect, providing a kind of imaging sensor, comprising: form light in the semiconductor substrate
Electric diode, the photodiode include: the electric charge collecting region with the first conduction type；And there is the second conduction type
Pinned surface layer, second conduction type and first conduction type are on the contrary, institute's pinned surface layer is located at the charge
On collecting region, wherein the pinned surface layer by the second conduction type in the semiconductor substrate carrier aggregation and
It is formed.
According to the second aspect of the disclosure, a kind of method for manufacturing imaging sensor is provided, comprising: in semiconductor substrate
Middle formation photodiode, wherein forming the photodiode includes: to be formed to have first to lead in the semiconductor substrate
The electric charge collecting region of electric type；And make the carrier of the second conduction type in the semiconductor substrate, it is partly led described
Assemble in the part of body substrate being located on the electric charge collecting region, to form the pinning surface with the second conduction type
Layer, wherein second conduction type is opposite with first conduction type.
By the detailed description referring to the drawings to the exemplary embodiment of the disclosure, the other feature of the disclosure and its
Advantage will become apparent.
Detailed description of the invention
The attached drawing for constituting part of specification describes embodiment of the disclosure, and together with the description for solving
Release the principle of the disclosure.
The disclosure can be more clearly understood according to following detailed description referring to attached drawing, in which:
Figure 1A and 1B is some steps for schematically showing the method for manufacturing imaging sensor in the prior art
The schematic diagram in the section of the imaging sensor at place.
Fig. 2A and 2B is the imaging sensor schematically shown according to disclosure one or more exemplary embodiment
At least partly structure formation basic theory schematic diagram.
Fig. 3 A to 3G is to schematically show to manufacture according to disclosure one or more exemplary embodiment
The schematic diagram in the section of the imaging sensor at the exemplary some steps of the method for imaging sensor.
Note that same appended drawing reference is used in conjunction between different attached drawings sometimes in embodiments described below
It indicates same section or part with the same function, and omits its repeated explanation.In some cases, using similar mark
Number and letter indicate similar terms, therefore, once being defined in a certain Xiang Yi attached drawing, then do not needed in subsequent attached drawing pair
It is further discussed.
In order to make it easy to understand, position, size and range of each structure shown in attached drawing etc. etc. do not indicate practical sometimes
Position, size and range etc..Therefore, the disclosure is not limited to position, size and range disclosed in attached drawing etc. etc..
Specific embodiment
It is described in detail the various exemplary embodiments of the disclosure below with reference to accompanying drawings.It should also be noted that unless in addition having
Body explanation, the unlimited system of component and the positioned opposite of step, numerical expression and the numerical value otherwise illustrated in these embodiments is originally
Scope of disclosure.
Be to the description only actually of at least one exemplary embodiment below it is illustrative, never as to the disclosure
And its application or any restrictions used.That is, structure and method herein is to show in an exemplary fashion, for
The different embodiments of structures and methods in the bright disclosure.It will be understood by those skilled in the art, however, that they be merely illustrative can
Exemplary approach with the disclosure for being used to implement, rather than mode exhausted.In addition, attached drawing is not necessarily drawn to scale, it is some
Feature may be amplified to show the details of specific component.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable
In the case of, the technology, method and apparatus should be considered as authorizing part of specification.
It is shown here and discuss all examples in, any occurrence should be construed as merely illustratively, without
It is as limitation.Therefore, the other examples of exemplary embodiment can have different values.
For simplicity, when orientation described herein, such as top, bottom, upper and lower, side etc., it is with direction shown in the drawings
Reference is described.For example, referring to when referring to the upper surface of semiconductor substrate with the semiconductor in direction shown in the drawings
The upper surface of substrate, can be the surface for receiving light irradiation may not be；Similarly, when referring to semiconductor substrate
When lower surface, refer to the table that can be with the lower surface of the semiconductor substrate in direction shown in the drawings for receiving light irradiation
Face may not be.For example, when the imaging sensor of the disclosure is back illumination formula cmos image sensor, semiconductor substrate
Upper surface can not be the surface for receiving light irradiation；When the imaging sensor of the disclosure is front irradiation formula cmos image sensing
When device, the upper surface of semiconductor substrate can be the surface for receiving light irradiation.
As shown in Figure 1A, in the prior art, photodiode is formed in the P-type semiconductor substrate 11 shallowly adulterated
The N-type floating diffusion region 13 of the heavy doping of the N-type electric charge collecting region 12 and the charge for transfer charge collecting region 12 of heavy doping.
The transfer gate structure 14 for controlling electric charge transfer is formed on semiconductor substrate 11, transfer gate structure 14 includes grid
Pole electrode 141 and gate-dielectric 142.From the upper surface of semiconductor substrate 11 into semiconductor substrate 11 injecting p-type dopant
To form the pinned surface layer 15 of photodiode as shown in Figure 1B.For example, can be injected into semiconductor substrate 11 boron from
Son, Implantation Energy are 6K electron-volts, dosage 5.0E13cm-2.The inventor of the disclosure passes through research prior art discovery,
During forming the pinned surface layer of pinned photodiode, the operation for injecting dopant will cause 11 table of semiconductor substrate
The damage in face, these damages may also cause dark current.
Therefore, dark current can be reduced or eliminated in a first aspect, provide a kind of imaging sensor in the disclosure.Such as
Shown in Fig. 2A and 2B, the imaging sensor according to some embodiments of the present disclosure includes half be formed in the second conduction type
The floating diffusion with the first conduction type of photodiode in conductor substrate 21, the charge for shifting photodiode
Area 23, the transfer gate structure 24 for controlling electric charge transfer and at least part of heap for being used to form the photodiode
Stack structure 26.
Photodiode includes the electric charge collecting region 22 and tool with the first conduction type in semiconductor substrate 21
There is the pinned surface layer 25 of second conduction type opposite with the first conduction type, wherein pinned surface layer 25 is located at charge receipts
Collect on area 22.Electric charge collecting region 22 with the first conduction type can be from the semiconductor substrate 21 to the second conduction type
It injects the dopant of the first conduction type and is formed.Pinned surface layer 25 by the second conduction type in semiconductor substrate 21 load
Stream is assembled and is formed.Therefore, electric charge collecting region 22 and pinned surface layer 25 can be considered as the one of semiconductor substrate 21
Part.
In addition, the floating diffusion region 23 with the first conduction type can be the semiconductor substrate 21 to the second conduction type
It is middle injection the first conduction type dopant and formed, therefore, floating diffusion region 23 is also considered semiconductor substrate 21
A part.Transfer gate structure 24 includes gate electrode 141 and gate-dielectric 142.
Stacked structure 26 successively includes the tunnel layer 261 being formed of oxide, the capture formed by nitride from bottom to up
It layer 262, the barrier layer 263 that is formed of oxide and is formed by semiconductor material (such as polycrystalline semiconductor material of doping)
Electrode layer 264.To which semiconductor substrate 21 and stacked structure 26 form Semiconductor Oxide-nitride-oxygen from bottom to top
The structure of compound-semiconductor (SONOS).
Wherein, stacked structure 26 can be used for being formed the pinned surface layer 25 of photodiode.For example, can be tied to stacking
The electrode layer 264 of structure 26 applies voltage, so that the carrier of the first conduction type in semiconductor substrate 21 gathers prisoner
Obtain in layer 262, carry out so that the second conduction type in semiconductor substrate 21 carrier capture layer 262 potential effect
Under, it is gathered in the surface for the part of semiconductor substrate 21 being located under stacked structure 26, to form pinned surface layer 25.
In one case, as shown in Figure 2 A, the electrode layer 264 of stacked structure 26 is applied relative to semiconductor substrate 21
Positive voltage, electrons in semiconductor substrate 21 since tunneling effect passes through tunnel layer 261 hence into capture layer 262,
These electronics are captured in capture layer 262 under the blocking on barrier layer 263, as shown in Figure 2 B, 27 table of appended drawing reference therein
Show the electronics being trapped in capture layer 262.After the voltage for being applied to electrode layer 264 removes, captured in capture layer 262
Under the action of these electronics 27, the hole (being indicated with appended drawing reference 28) in semiconductor substrate 21 is gathered in semiconductor substrate 21
The surface of part under stacked structure 26, to form pinned surface layer 25.The pinned surface layer 25 that is thusly-formed with
Stacked structure 26 with there is overlapping region in the plan view of the major surfaces in parallel of imaging sensor, or even essentially coincide.So
The photodiode of formation is the pinned photodiode of positive-negative-positive.
It will be understood by those skilled in the art that the above description in conjunction with attached drawing 2A and 2B is only an example.In another feelings
Under condition, can also electrode layer 264 to stacked structure 26 apply the negative voltage relative to semiconductor substrate 21 so that semiconductor serves as a contrast
Hole in bottom 21 passes through tunnel layer 261 into capture layer 262 and is captured the capture of layer 262, so that semiconductor substrate 21
In electronics be gathered in semiconductor substrate 21 be located at stacked structure 26 under part surface, to form pinned surface layer
25.The photodiode being thusly-formed can be the pinned photodiode of NPN type.
Since the photodiode in the imaging sensor of the disclosure is pinned photodiode, pinned surface layer can
Prevent the depletion region when the electric charge collecting region of photodiode is completely depleted from expanding to the surface of semiconductor substrate, so as to
Reduce or eliminate the formation of dark current.Further, since the pinning surface in photodiode in the imaging sensor of the disclosure
Layer is not to handle to be formed by ion implanting, that is to say, that forms the process of pinned surface layer not to semiconductor substrate
Surface cause to damage, therefore compared with the prior art in pinned photodiode, can be further reduced or eliminate dark electricity
The generation of stream.
Further, in the case where photodiode is the pinned photodiode of positive-negative-positive, the pinning surface of p-type
Layer, which is more advantageous to, reduces or eliminates dark current, this is because in the processing for forming electric charge collecting region by ion implanting, it can be right
Semiconductor substrate causes to damage, and there may be some defect electrons that can cause dark current, the pinning surfaces of p-type for these damages
Layer can neutralize these a part of electronics, thus the pinned photodiode of positive-negative-positive compared with NPN type pinned photodiode more
Help to reduce or eliminate dark current.
It, can be by adjusting being applied in stacked structure in addition, the stacked structure of the imaging sensor for the disclosure
The size of the voltage of electrode layer, come adjust the first conduction type that capture layer is captured carrier quantity, so as to adjust
The quantity of the carrier for the second conduction type assembled at the surface of semiconductor substrate adjusts the inhibition to dark current with this
Amount.
Further, since being carried under the action of the pinned surface layer in the disclosure is the potential of the capture layer in stacked structure
Stream aggregation and formed, therefore, the pinned surface layer and stacked structure of formation are in the major surfaces in parallel with imaging sensor
There is overlapping region in plan view, or even essentially coincide.It, can be by the manufacturing process of imaging sensor based on the feature
The position of the stacked structure formed is adjusted, to be easily adjusted the position for the pinned surface layer to be formed.For example, as shown in Figure 2 A,
Stacked structure 26 can be formed in the surface of electric charge collecting region 22, for example, in figure the right side of stacked structure 26 edge
The edge that the right side edge of electric charge collecting region 22 or even the right side of stacked structure 26 can be exceeded extends to the pixel unit
Boundary (such as at isolation structure for defining the pixel unit), the pinned surface layer 25 being thusly-formed is as shown in Figure 2 B
The right side edge that electric charge collecting region 22 may also be exceeded to the right, even extends to the boundary of the pixel unit.
In the second aspect of the disclosure, a kind of method for manufacturing imaging sensor is provided.It is retouched below with reference to Fig. 3 A to 3G
The method for stating the manufacture imaging sensor according to one or more exemplary embodiments of the disclosure.
As shown in Figure 3A, it is operated from the upper surface of semiconductor substrate 31 with the second conduction type, such as can be with
By injecting the dopant of the first conduction type into semiconductor substrate 31, photodiode is formed in semiconductor substrate 31
Electric charge collecting region 32 with the first conduction type and the charge for shifting photodiode have the first conduction type
Floating diffusion region 63.
As shown in Figure 3B, it is operated from the upper surface of semiconductor substrate 31, such as deposition oxide can be passed sequentially through
With the processing of nitride, the first oxide skin(coating) L1 and nitride layer L2 is sequentially formed.Wherein, the thickness of the first oxide skin(coating) L1 can
To be equivalent to the thickness of the tunnel layer 361 in stacked structure 36 to be formed, the thickness of nitride layer L2 can be equivalent to by
The thickness of capture layer 362 in stacked structure 36 to be formed.
As shown in Figure 3 C, it is operated from the upper surface of semiconductor substrate 31, such as place is performed etching to nitride layer L2
Reason is removed by the part except the capture layer 362 in stacked structure 36 to be formed, thus by a part of shape of nitride layer L2
As the capture layer 362 in stacked structure 36.
As shown in Figure 3D, it is operated from the upper surface of semiconductor substrate 31, such as the place of deposition oxide can be passed through
Reason forms the second oxide skin(coating) L3.The thickness of second oxide skin(coating) L3 can be equivalent to will be in stacked structure 36 to be formed
The thickness on barrier layer 363.In this step, the part of the second oxide skin(coating) L3 being located on capture layer 362 is formed as stacking
Barrier layer 363 in structure 36.
As shown in FIGURE 3 E, it is operated, such as can be by deposition processes, such as is sunk from the upper surface of semiconductor substrate 31
Product polycrystalline semiconductor material, forms semiconductor material layer L4.The thickness of semiconductor material layer L4 can be equivalent to will be to be formed
The thickness of electrode layer 364 in stacked structure 36.In this step, semiconductor material layer L4 be located at barrier layer 363 on
Part is formed as electrode layer 364.
As illustrated in Figure 3 F, it is operated from the upper surface of semiconductor substrate 31, to semiconductor material layer L4, the second oxide
Layer L3 and the first oxide skin(coating) L1 performs etching processing, removes by stacked structure 36 to be formed and by TG transfer gate to be formed
The part except region where pole structure 34, so that a part of the first oxide skin(coating) L1 is formed tunnel layer 361, tunnel layer
361 are formed together stacked structure 36 with capture layer 362, barrier layer 363 and the electrode layer 364 formed in the above operation；And
And gate-dielectric 342 is collectively formed in a part of a part of the first oxide skin(coating) L1 and the second oxide skin(coating) L3, it will
A part of semiconductor material layer L4 forms gate electrode 341, and gate electrode 341 is collectively formed with gate-dielectric 342 and is used for
Control the transfer gate structure 34 of electric charge transfer.
As shown in Figure 3 G, voltage is applied to the electrode layer 364 of stacked structure 36, so that the in semiconductor substrate 31
The carrier of one conduction type gathers in capture layer 362, carries out so that the carrier of the second conduction type is in capture layer 362
Assemble under the action of potential, to form pinned surface layer 35.
In one case, the positive voltage relative to semiconductor substrate 31 is applied to the electrode layer 364 of stacked structure 36, partly
Electrons in conductor substrate 31 pass through tunnel layer 361 hence into capture layer 362, on barrier layer 363 due to tunneling effect
These electronics are captured in capture layer 362 under blocking.After the voltage for being applied to electrode layer 364 removes, in capture layer
Under the action of 362 these electronics captured, the void coalescence in semiconductor substrate 31 is stacked in being located at for semiconductor substrate 31
The surface of part under structure 36, to form pinned surface layer 35.The pinned surface layer 35 and stacked structure being thusly-formed
36 with there is overlapping region in the plan view of the major surfaces in parallel of imaging sensor, or even essentially coincide.The light being thusly-formed
Electric diode is the pinned photodiode of positive-negative-positive.
In another case, the negative voltage relative to semiconductor substrate 31 is applied to the electrode layer 364 of stacked structure 36,
Hole in semiconductor substrate 31 can pass through tunnel layer 361 hence into capture layer 362, on barrier layer 363 due to tunneling effect
Blocking under these holes be captured in capture layer 362.After the voltage for being applied to electrode layer 364 removes, capturing
Under the action of 362 these holes for being captured of layer, what the electronics in semiconductor substrate 31 was gathered in semiconductor substrate 31 is located at heap
The surface of part under stack structure 36, to form pinned surface layer 35.The pinned surface layer 35 and stacking being thusly-formed are tied
Structure 36 with there is overlapping region in the plan view of the major surfaces in parallel of imaging sensor, or even essentially coincide.It is thusly-formed
Photodiode is the pinned photodiode of NPN type.
In this way, since the pinned surface layer in the photodiode in the imaging sensor of the disclosure is infused by ion
Enter processing formation, the surface of semiconductor substrate is not damaged, therefore dark current can be reduced or eliminated.Further,
In the case where photodiode is the pinned photodiode of positive-negative-positive, the pinned surface layer of p-type, which is more advantageous to, to be reduced or eliminated
Dark current.It, can be by adjusting being applied to the electricity in stacked structure in addition, the stacked structure of the imaging sensor for the disclosure
The size of the voltage of pole layer, to adjust the amount of suppression to dark current.
It will be understood by those skilled in the art that in the disclosure, the semiconductor substrate 21,31 in imaging sensor is interpreted as
Material based on semiconductor, can be by being suitable for any semiconductor material (Si, SiC, SiGe etc.) of semiconductor device
It is made.In addition, semiconductor substrate 21,31 or silicon-on-insulator (SOI), silicon germanium on insulator, silicon on sapphire (SOS)
Etc. the semiconductor portions of various compound substrates.Semiconductor substrate 21,31 may be doping or undoped semiconductor material
Material, can also be the semiconductor material layer of the epitaxial growth on the material of semiconductor, in can also form based on half
The region of conductor material or non-semiconducting material.It will be appreciated by those skilled in the art that the material of semiconductor substrate 21,31 not by
To any restrictions, but can be selected according to practical application.
Word " A or B " in specification and claim includes " A and B " and " A or B ", rather than is exclusively only wrapped
Include " A " or only include " B ", unless otherwise specified.
In the word "front", "rear" in specification and claim, "top", "bottom", " on ", " under " etc., if deposited
If, it is not necessarily used to describe constant relative position for descriptive purposes.It should be appreciated that the word used in this way
Language be in appropriate circumstances it is interchangeable so that embodiment of the disclosure described herein, for example, can in this institute
It is operated in those of description show or other other different orientations of orientation.
As used in this, word " illustrative " means " be used as example, example or explanation ", not as will be by
" model " accurately replicated.It is not necessarily to be interpreted than other implementations in any implementation of this exemplary description
It is preferred or advantageous.Moreover, the disclosure is not by above-mentioned technical field, background technique, summary of the invention or specific embodiment
Given in go out theory that is any stated or being implied limited.
As used in this, word " substantially " means comprising the appearance by the defect, device or the element that design or manufacture
Any small variation caused by difference, environment influence and/or other factors.Word " substantially " also allows by ghost effect, makes an uproar
Caused by sound and the other practical Considerations being likely to be present in actual implementation with perfect or ideal situation
Between difference.
In addition, the description of front may be referred to and be " connected " or " coupling " element together or node or feature.Such as
It is used herein, unless explicitly stated otherwise, " connection " mean an element/node/feature and another element/node/
Feature is being directly connected (or direct communication) electrically, mechanically, in logic or in other ways.Similarly, unless separately
It clearly states outside, " coupling " means that an element/node/feature can be with another element/node/feature with direct or indirect
Mode link mechanically, electrically, in logic or in other ways to allow to interact, even if the two features may
It is not directly connected to be also such.That is, " coupling " is intended to encompass the direct connection and indirectly of element or other feature
Connection, including the use of the connection of one or more intermediary elements.
In addition, just to the purpose of reference, can with the similar terms such as " first " used herein, " second ", and
And it thus is not intended to limit.For example, unless clearly indicated by the context, be otherwise related to structure or element word " first ", "
Two " do not imply order or sequence with other such digital words.
It should also be understood that one word of "comprises/comprising" as used herein, illustrates that there are pointed feature, entirety, steps
Suddenly, operation, unit and/or component, but it is not excluded that in the presence of or increase one or more of the other feature, entirety, step, behaviour
Work, unit and/or component and/or their combination.
In the disclosure, therefore term " offer " " it is right to provide certain from broadly by covering all modes for obtaining object
As " including but not limited to " purchase ", " preparation/manufacture ", " arrangement/setting ", " installation/assembly ", and/or " order " object etc..
It should be appreciated by those skilled in the art that the boundary between aforesaid operations is merely illustrative.Multiple operations
It can be combined into single operation, single operation can be distributed in additional operation, and operating can at least portion in time
Divide and overlappingly executes.Moreover, alternative embodiment may include multiple examples of specific operation, and in other various embodiments
In can change operation order.But others are modified, variations and alternatives are equally possible.Therefore, the specification and drawings
It should be counted as illustrative and not restrictive.
Although being described in detail by some specific embodiments of the example to the disclosure, the skill of this field
Art personnel it should be understood that above example merely to be illustrated, rather than in order to limit the scope of the present disclosure.It is disclosed herein
Each embodiment can in any combination, without departing from spirit and scope of the present disclosure.It is to be appreciated by one skilled in the art that can be with
A variety of modifications are carried out without departing from the scope and spirit of the disclosure to embodiment.The scope of the present disclosure is limited by appended claims
It is fixed.
Claims (10)
1. a kind of imaging sensor characterized by comprising
Photodiode in the semiconductor substrate is formed, the photodiode includes:
Electric charge collecting region with the first conduction type；And
Pinned surface layer with second conduction type opposite with first conduction type, the pinned surface layer are located at institute
It states on electric charge collecting region,
Wherein, the pinned surface layer at least partly by the second conduction type in the semiconductor substrate carrier assemble
And it is formed.
2. imaging sensor according to claim 1, which is characterized in that described image sensor further include:
Stacked structure on the semiconductor substrate, the stacked structure and the pinned surface layer with described image
There is overlapping region in the plan view of the major surfaces in parallel of sensor,
Wherein, the semiconductor substrate and the stacked structure form Semiconductor Oxide-Nitride Oxide-semiconductor
Structure.
3. imaging sensor according to claim 2, which is characterized in that the stacked structure successively includes tunnel from bottom to up
Channel layer, capture layer, barrier layer and electrode layer,
Wherein, when applying the positive voltage relative to the semiconductor substrate to the electrode layer, in the semiconductor substrate
Electronics passes through the tunnel layer and is captured in the capture layer, so that the second conductive-type in the semiconductor substrate
The carrier of type is gathered in the surface for the part of the semiconductor substrate being located under the stacked structure, thus described in being formed
Pinned surface layer.
4. imaging sensor according to claim 2, which is characterized in that the stacked structure and the pinned surface layer exist
It is essentially coincided in the plan view.
5. imaging sensor according to claim 1, which is characterized in that the photodiode is PNP photodiode.
6. a kind of method for manufacturing imaging sensor, comprising:
Photodiode is formed in the semiconductor substrate, wherein forming the photodiode and including:
The electric charge collecting region with the first conduction type is formed in the semiconductor substrate；And
So that the carrier of the second conduction type in the semiconductor substrate, is located at the charge in the semiconductor substrate
Assemble in part on collecting region, to form the pinning with second conduction type opposite with first conduction type
Superficial layer is at least partly.
7. according to the method described in claim 6, it is characterized in that, the method also includes:
After forming the electric charge collecting region and before forming the pinned surface layer, on the semiconductor substrate
With the electric charge collecting region in the plan view of the major surfaces in parallel of described image sensor with overlapping region region
Stacked structure is formed,
Wherein formed the stacked structure include: sequentially form tunnel layer, capture layer, barrier layer and electrode layer so that
The semiconductor substrate and the stacked structure form Semiconductor Oxide-Nitride Oxide-semiconductor structure.
8. the method according to the description of claim 7 is characterized in that making the second conduction type in the semiconductor substrate
Carrier is assembled and forms the pinned surface layer and include:
After forming the stacked structure, the positive voltage relative to the semiconductor substrate is applied to the electrode layer, so that
Electronics in the semiconductor substrate passes through the tunnel layer and is captured in the capture layer, so that the semiconductor
The carrier of the second conduction type in substrate is gathered in the part of the semiconductor substrate being located under the stacked structure
Surface, to form the pinned surface layer.
9. the method according to the description of claim 7 is characterized in that the stacked structure is formed in and the electric charge collecting region
With the region that is essentially coincided in the plan view of the major surfaces in parallel of described image sensor.
10. the method according to the description of claim 7 is characterized in that the photodiode is PNP photodiode.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110444556A (en) * | 2019-08-30 | 2019-11-12 | 上海华力微电子有限公司 | The forming method of cmos sensor and cmos sensor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040262622A1 (en) * | 2003-03-28 | 2004-12-30 | Inna Patrick | Double pinned photodiode for CMOS APS and method of formation |
| US20080029792A1 (en) * | 2004-12-29 | 2008-02-07 | Shim Hee S | Cmos image sensor and method for fabricating the same |
| CN102593134A (en) * | 2011-01-07 | 2012-07-18 | 格科微电子（上海）有限公司 | Image sensor and manufacturing method thereof |
-
2018
- 2018-11-13 CN CN201811342765.8A patent/CN109461750A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040262622A1 (en) * | 2003-03-28 | 2004-12-30 | Inna Patrick | Double pinned photodiode for CMOS APS and method of formation |
| US20080029792A1 (en) * | 2004-12-29 | 2008-02-07 | Shim Hee S | Cmos image sensor and method for fabricating the same |
| CN102593134A (en) * | 2011-01-07 | 2012-07-18 | 格科微电子（上海）有限公司 | Image sensor and manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110444556A (en) * | 2019-08-30 | 2019-11-12 | 上海华力微电子有限公司 | The forming method of cmos sensor and cmos sensor |
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