CN113644023A - Method for improving BSI RTS level by adjusting thickness of DTI tungsten barrier layer - Google Patents
Method for improving BSI RTS level by adjusting thickness of DTI tungsten barrier layer Download PDFInfo
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- CN113644023A CN113644023A CN202110789832.6A CN202110789832A CN113644023A CN 113644023 A CN113644023 A CN 113644023A CN 202110789832 A CN202110789832 A CN 202110789832A CN 113644023 A CN113644023 A CN 113644023A
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Abstract
The invention provides a method for improving BSI RTS level by adjusting the thickness of a DTI tungsten barrier layer, which comprises the steps of providing a silicon substrate, and forming a deep groove on the silicon substrate; sequentially covering a first oxide layer, an HK dielectric layer, a second oxide layer and a tungsten adhesion layer in the deep trench; depositing tungsten on the silicon substrate to fill the deep trench; etching to remove tungsten on the surface of the silicon substrate; depositing the upper surface of the deep groove filled with tungsten to the thickness of
The oxidation barrier layer of (1). The overall level of RTS of the chip is remarkably reduced, and parameters P50 and P97 are improved by more than 20%; meanwhile, the white point pixel and the dark current level of the chip are also greatly reduced; the noise level of the chip is obviously improved, the yield of the chip is improved, and more profits are obtained at the same cost.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for improving BSI RTS level by adjusting the thickness of a DTI tungsten barrier layer.
Background
According to the back-illuminated BSI (back-illuminated CIS), after a silicon chip is thinned, CF and Micro Lens are built on the back of a photodiode, light rays are emitted from the back, the light-sensitive area of a photoelectric element is increased, loss of the light rays when the light rays are wired is reduced, and the light-sensitive capacity of the CIS in a weak light environment can be greatly improved. BSI Deep Trench Isolation (DTI) technology: after the silicon chip is thinned, in order to prevent crosstalk, a DTI technology needs to be adopted among the photodiodes, so that the crosstalk among pixels can be greatly reduced, and the imaging quality is improved.
RTS (random telegraph noise): the method is an important parameter for representing the performance of the CIS, and is a random process, in the CIS, RTS noise can generate wrong white points in places which are black, and imaging quality is seriously influenced; the primary source of RTS is dark current. A tungsten Block oxide (W Block oxide) is generally filled with W in DTI, and an oxidation barrier layer needs to be deposited on the surface after W CMP or etching to isolate and protect the DTI. The thickness and quality of the tungsten oxide barrier layer has a large impact on the quality of BSI imaging.
The existing W block oxide deposition process is plasma enhanced chemical vapor deposition (PEVCD). The nature of the oxide film, such as thickness, H content, stress, etc., affects the type and number of interface defects, which randomly trap and release carriers (e.g., dangling bonds) and behave as RTS. For example, oxide films of different thicknesses have different stress levels, and the stress weakens the Si-O/Si-Si bonds, causing them to break, creating traps, which in turn affect RTS.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention aims to provide a method for improving BSI RTS level by adjusting the thickness of a DTI tungsten barrier layer, so as to solve the problem of low imaging quality of CIS chips due to low CIS random telegraph noise level in the prior art.
To achieve the foregoing and other related objects, the present invention provides a method for improving BSI RTS levels by adjusting the thickness of a DTI tungsten barrier layer,
providing a silicon substrate, and forming a deep groove on the silicon substrate;
covering a first oxide layer, an HK dielectric layer, a second oxide layer and a tungsten adhesion layer in the deep groove in sequence;
depositing tungsten on the silicon substrate to fill the deep groove;
etching to remove tungsten on the surface of the silicon substrate;
depositing the upper surface of the deep groove filled with tungsten to the thickness of
The oxidation barrier layer of (1).
Preferably, in the first step, the deep trench is formed on the silicon substrate by combining plasma etching and wet etching.
Preferably, in the third step, the deep trench is filled with tungsten by a physical vapor deposition method.
Preferably, in the fourth step, the tungsten on the surface of the silicon substrate is removed by plasma etching.
Preferably, the thickness of the oxidation barrier layer deposited in the fifth step is
Or
Preferably, the thickness of the deposited oxidation barrier layer is adjusted by changing the deposition time of PECVD in step five.
Preferably, the method is used for a BIS process node of 55 nm.
As described above, the method for improving BSI RTS level by adjusting the thickness of the DTI tungsten barrier layer of the present invention has the following beneficial effects: the overall level of RTS of the chip is remarkably reduced, and parameters P50 and P97 are improved by more than 20%; meanwhile, the white point pixel and the dark current level of the chip are also greatly reduced; the noise level of the chip is obviously improved, the yield of the chip is improved, and more profits are obtained at the same cost.
Drawings
FIG. 1 is a schematic cross-sectional view of a deep trench filled with tungsten according to the present invention;
FIG. 2 is a schematic diagram showing a deep trench structure after removing tungsten on the upper surface of the silicon substrate by etching according to the present invention;
FIG. 3 is a schematic diagram illustrating a structure of the present invention after depositing an oxidation barrier layer on a deep trench filled with tungsten;
FIG. 4 shows RTS plots for oxidation barrier layers of different thicknesses;
FIG. 5 is a graph showing dark current curves for different thicknesses of oxidation barrier layers;
FIG. 6 shows RTS curves corresponding to oxidation-resistant barrier layers of different thicknesses under two P parameters in the present invention;
FIG. 7 shows dark current curves corresponding to different thickness of oxide barrier layers under two P parameters in the present invention;
fig. 8 is a flow chart illustrating a method of improving BSI RTS levels by adjusting the thickness of the DTI tungsten barrier layer according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 8. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The present invention provides a method for improving BSI RTS level by adjusting the thickness of a DTI tungsten barrier layer, as shown in fig. 8, fig. 8 is a flowchart of a method for improving BSI RTS level by adjusting the thickness of a DTI tungsten barrier layer in the present invention, which at least includes:
providing a silicon substrate, and forming a deep groove on the silicon substrate; as shown in fig. 1, fig. 1 is a schematic cross-sectional view of the deep trench filled with tungsten according to the present invention. In the first step, the silicon substrate Si is provided, and the deep groove is formed on the silicon substrate Si.
Further, in the first step of this embodiment, the deep trench is formed on the silicon substrate by a combination of plasma etching (plasma etch) and wet etching (wet etch).
Covering a first oxide layer, an HK dielectric layer, a second oxide layer and a tungsten adhesion layer in the deep groove in sequence; as shown in fig. 1, in the second step, the first oxide layer (chemical oxide), the HK dielectric layer (High-K), the second oxide layer (Liner oxide), and the tungsten glue layer (W glue layer) are sequentially formed in the deep trench. The first oxide layer (ceramic oxide), the HK dielectric layer (High-K), the second oxide layer (Liner oxide) and the tungsten adhesion layer (W glue layer) are sequentially covered in the deep trench, namely, the first oxide layer (ceramic oxide) directly covers the surface (bottom and side wall) of the deep trench, the HK dielectric layer (High-K) deposited later covers the surface of the first oxide layer (ceramic oxide), the second oxide layer (Liner oxide) deposited later covers the HK dielectric layer (High-K), and the tungsten adhesion layer (W glue layer) deposited later covers the second oxide layer (Liner oxide). As shown in fig. 1, in the embodiment, when the first oxide layer, the HK dielectric layer, the second oxide layer and the tungsten adhesion layer are deposited in the deep trench, the upper surfaces of the silicon substrates at two sides outside the deep trench are also covered by the first oxide layer, the HK dielectric layer, the second oxide layer and the tungsten adhesion layer.
Depositing tungsten on the silicon substrate to fill the deep groove; as shown in fig. 1, the third step is to deposit tungsten (W) on the silicon substrate to fill the deep trench, that is, to fill tungsten in the deep trench, and at the same time, the upper surface of the silicon substrate overflows a part of tungsten when depositing tungsten in the deep trench, so that the upper surface of the deep trench filled with tungsten as shown in fig. 1 is covered with tungsten.
Further, in the third step of the present embodiment, the deep trench is filled with tungsten by a Physical Vapor Deposition (PVD) method.
Etching to remove tungsten on the surface of the silicon substrate; as shown in fig. 2, fig. 2 is a schematic diagram showing a deep trench structure after removing tungsten on the upper surface of the silicon substrate by etching in the present invention. In this embodiment, since the first oxide layer, the HK dielectric layer, the second oxide layer, and the tungsten adhesion layer are also deposited on the upper surface of the silicon substrate on the two sides outside the deep trench, the tungsten on the upper surface of the silicon substrate is removed by etching in the fourth step until the tungsten adhesion layer is exposed.
Further, in the fourth step of the present embodiment, the tungsten on the surface of the silicon substrate is removed by plasma etching (plasma etch).
Depositing the upper surface of the deep groove filled with tungsten to the thickness of
The oxidation barrier layer of (1). As shown in fig. 3, fig. 3 is a schematic structural view of the present invention after depositing an oxidation barrier layer on a deep trench filled with tungsten. In the fifth step, the upper surface of the deep groove filled with tungsten is deposited to the thickness of
A W block oxide(s) is used.
Further, the thickness of the oxidation barrier layer deposited in the fifth step of this embodiment is as follows
Or
Still further, in the fifth step of the present embodiment, the thickness of the oxidation barrier layer deposited is
Further, in step five of this embodiment, the thickness of the deposited oxidation barrier layer is adjusted by changing the deposition time of PECVD.
Further, the method of the present embodiment is applied to a BIS process node of 55 nm.
As shown in fig. 4 and 5, fig. 4 shows RTS plots for oxidation barrier layers of different thicknesses. Wherein each thickness of
) The oxidation barrier layer (Block oxide) of (a) contains two curves corresponding to the P50 and P97 parameters, respectively. Fig. 5 shows dark current profiles for oxidation barrier layers of different thicknesses. Wherein each thickness of
) The oxidation barrier layer (Block oxide) of (a) contains two curves corresponding to the P50 and P97 parameters, respectively.
As shown in fig. 6 and 7, fig. 6 shows RTS curves corresponding to oxidation barrier layers of different thicknesses under two P parameters in the present invention. FIG. 7 shows dark current curves corresponding to different thickness of the oxidation-blocking layer under two P parameters in the present invention. Therefore, the optimal process conditions are found, the overall level of the RTS of the chip is obviously reduced, and the parameters P50 and P97 are improved by more than 20%; meanwhile, chip white point pixels and dark current levels (DC) are also greatly reduced; the noise level of the chip is obviously improved, the yield of the chip is improved, and more profits are obtained at the same cost.
In conclusion, the overall level of RTS of the chip is remarkably reduced, and the parameters P50 and P97 are improved by more than 20%; meanwhile, the white point pixel and the dark current level of the chip are also greatly reduced; the noise level of the chip is obviously improved, the yield of the chip is improved, and more profits are obtained at the same cost. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A method for improving BSI RTS levels by adjusting DTI tungsten barrier layer thickness, comprising at least:
providing a silicon substrate, and forming a deep groove on the silicon substrate;
covering a first oxide layer, an HK dielectric layer, a second oxide layer and a tungsten adhesion layer in the deep groove in sequence;
depositing tungsten on the silicon substrate to fill the deep groove;
etching to remove tungsten on the surface of the silicon substrate;
depositing the upper surface of the deep groove filled with tungsten to the thickness of
The oxidation barrier layer of (1).
2. The method of claim 1 for improving BSI RTS levels by adjusting DTI tungsten barrier layer thickness, wherein: in the first step, the deep groove is formed on the silicon substrate in a mode of combining plasma etching and wet etching.
3. The method of claim 1 for improving BSI RTS levels by adjusting DTI tungsten barrier layer thickness, wherein: and step three, filling tungsten in the deep groove by a physical vapor deposition method.
4. The method of claim 1 for improving BSI RTS levels by adjusting DTI tungsten barrier layer thickness, wherein: and in the fourth step, removing the tungsten on the surface of the silicon substrate by plasma etching.
5. The method of claim 1 for improving BSI RTS levels by adjusting DTI tungsten barrier layer thickness, wherein: depositing the oxidation barrier layer in the fifth step to a thickness of
Or
6. The method of claim 1 for improving BSI RTS levels by adjusting DTI tungsten barrier layer thickness, wherein: depositing the oxidation barrier layer in the fifth step to a thickness of
7. The method of claim 1 for improving BSI RTS levels by adjusting DTI tungsten barrier layer thickness, wherein: and fifthly, adjusting the thickness of the deposited oxidation barrier layer by changing the deposition time of PECVD.
8. The method of claim 1 for improving BSI RTS levels by adjusting DTI tungsten barrier layer thickness, wherein: the method is used for a BIS process node with the wavelength of 55 nm.
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Citations (5)
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| CN106486506A (en) * | 2015-08-27 | 2017-03-08 | 台湾积体电路制造股份有限公司 | Deep trench isolation structure and forming method thereof |
| CN110620125A (en) * | 2019-09-23 | 2019-12-27 | 上海华力微电子有限公司 | Structure for reducing random telegraph noise in CMOS image sensor and forming method |
| US20200251510A1 (en) * | 2017-10-13 | 2020-08-06 | Shanghai Ic R&D Center Co., Ltd. | Method for manufacturing backside-illuminated cmos image sensor structure |
| CN111834287A (en) * | 2020-08-18 | 2020-10-27 | 上海华力微电子有限公司 | Preparation method of deep trench isolation structure and semiconductor structure |
| CN111863850A (en) * | 2020-07-29 | 2020-10-30 | 上海华力微电子有限公司 | Manufacturing method of deep trench isolation grid structure |
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- 2021-07-13 CN CN202110789832.6A patent/CN113644023A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106486506A (en) * | 2015-08-27 | 2017-03-08 | 台湾积体电路制造股份有限公司 | Deep trench isolation structure and forming method thereof |
| US20200251510A1 (en) * | 2017-10-13 | 2020-08-06 | Shanghai Ic R&D Center Co., Ltd. | Method for manufacturing backside-illuminated cmos image sensor structure |
| CN110620125A (en) * | 2019-09-23 | 2019-12-27 | 上海华力微电子有限公司 | Structure for reducing random telegraph noise in CMOS image sensor and forming method |
| CN111863850A (en) * | 2020-07-29 | 2020-10-30 | 上海华力微电子有限公司 | Manufacturing method of deep trench isolation grid structure |
| CN111834287A (en) * | 2020-08-18 | 2020-10-27 | 上海华力微电子有限公司 | Preparation method of deep trench isolation structure and semiconductor structure |
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