CN101154681A

CN101154681A - High-voltage transistor adopting non-homogeneous gate oxide and its manufacturing method

Info

Publication number: CN101154681A
Application number: CNA2006101165581A
Authority: CN
Inventors: 钱文生
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2006-09-27
Filing date: 2006-09-27
Publication date: 2008-04-02
Anticipated expiration: 2026-09-27
Also published as: CN100502043C

Abstract

The invention discloses a high-voltage transistor which effectively reduces the GIDL effect, but does not change the electrical property and a method for manufacturing the same. The high-voltage transistor adopts a non-uniform high-voltage gate oxide layer, which reduces the GIDL and the leakage current caused by the GIDL and does not change the electrical property of an apparatus. The method for manufacturing the invention comprises the following steps of: performing high-pressure well and diffused ion source implantation on the surface of a silicon substrate; growing a100 A monox layer and depositing a 500 A silicon nitride layer; performing photoetching and etching in the area where a thickened oxide layer is needed to form a silicon nitride window; oxidizing 100 A monox to form monox-layer steps in a groove; getting rid of silicon nitride; oxidizing 500-1000 A monox; depositing polysilicon gate; performing photoetching and etching of the gate; performing low-doped source-drain ion implantation to form a common source; depositing and etching silicon nitride side walls; performing source-drain ion implantation to form another common source; making refractory metal silicide, depositing the a dielectric layer before metalation and etching contacting hole.

Description

Adopt the high voltage transistor and the manufacture method thereof of non-homogeneous gate oxide

Technical field

The present invention relates to a kind of high tension apparatus that is applied to memory circuit.The invention still further relates to the manufacture method of this high tension apparatus.

Background technology

The high tension apparatus that is applied to memory circuitry at present adopts asymmetrical diffuse source structure usually, can bear sufficiently high voltage in order to make high tension apparatus, and the source end must use low dosage, high-octane ion to inject and form the diffusion region.This diffusion region and polysilicon gate have bigger overlapping, and surface doping concentration is lower, introduce the leakage current of drain terminal (Gate induced drain leakage is called for short GIDL) thereby be very easy to produce grid, cause high voltage transistor that higher leakage current is arranged.The thickness of the gate oxide between GIDL and polysilicon gate and the diffuse source is inversely proportional to, and thick more grid oxygen just has more little GIDL leakage current.As adopt evenly thicker gate oxidation films, and can reduce the longitudinal electric field in the gate oxidation films, the GIDL effect can be eased, but can improve transistorized threshold voltage like this, changes its electric property.

Summary of the invention

The technical problem to be solved in the present invention provides and a kind ofly can effectively reduce the high voltage transistor that the GIDL effect does not change its electrical properties.For this reason, the invention provides a kind of manufacture method of making described high voltage transistor.

For solving the problems of the technologies described above, the invention provides a kind of high voltage transistor that adopts non-homogeneous gate oxide, leak in parallel by source electrode, high pressure trap, diffusion, and a silicon nitride side wall is respectively arranged at described region upper surface in parallel two ends, accompany two-layer grid up and down between the described both walls, the upper strata is a polysilicon, and lower floor is an oxide layer, and its oxide layer is a non-homogeneous gate oxide.

In order to make the high voltage transistor of described employing non-homogeneous gate oxide, manufacture method of the present invention comprises following steps: a. carries out high pressure trap and the injection of diffuse source ion in surface of silicon; B. for the first time growing silicon oxide layer and deposit silicon nitride layer; C. carry out photoetching in the zone that needs add thick grating oxide layer and etching forms the silicon nitride window; D. growing silicon oxide for the second time forms the oxide layer step at raceway groove; E. remove silicon nitride; F. growing silicon oxide for the third time; G. deposit polysilicon gate; H. the photoetching of grid and etching; I. low doping source is leaked ion and is injected the formation source electrode; J. the deposit of silicon nitride side wall and etching; K. the source is leaked ion and is injected the formation source electrode; L. make refractory metal silicide, the dielectric layer before the depositing metalization carves contact hole; M. deposited metal, etching is finished interconnection.

The present invention is owing to adopt the high voltage transistor of non-homogeneous high voltage grid oxidation layer, diffusion leak and the gate oxide of the crossover region of polysilicon than other channel region thick, do not having significantly to change under the situation of device electrology characteristic the leakage current that has reduced GIDL effectively and caused.

Description of drawings

Fig. 1 is the schematic diagram that the present invention adopts the high voltage transistor of non-homogeneous gate oxide;

Fig. 2 is the manufacturing process flow diagram that the present invention adopts the high voltage transistor of non-homogeneous gate oxide.

Embodiment

The present invention is further detailed explanation below in conjunction with accompanying drawing.

As shown in Figure 1, the present invention adopts the non-homogeneous gate oxide technology that high voltage transistor is improved, diffusion leaked and polysilicon between the oxide layer of overlapping region thicken, thereby obtain effectively reducing GIDL and the leakage current that causes thereof and significantly do not change the high voltage transistor of high tension apparatus electrology characteristic.

As shown in Figure 2, for the present invention adopts the manufacturing process flow diagram of the high voltage transistor of non-homogeneous gate oxide, at first, selectivity is carried out the ion that high pressure trap and diffusion leak and is injected on silicon substrate, thereby forms high-pressure trap area territory and diffusion drain region on silicon substrate; Again at its superficial growth one deck silicon oxide layer, thickness is 100A and one deck silicon nitride layer afterwards, and its thickness is 500A; Remove the silicon nitride that needs the oxide layer thicker region by photoetching and etching, continue the silicon oxide layer of oxidation 100A on the silicon oxide layer surface of exposing, other channel region can not form silicon oxide layer again because stopping of silicon nitride arranged; Remove silicon nitride layer, expose non-homogeneous silicon oxide layer, can carry out standardization growing silicon oxide layer this moment up to satisfying the purposes needs, the thickness of this growing silicon oxide layer reaches 500～1000A among the present invention; At silicon oxide layer surface deposition polysilicon gate; Polysilicon gate and silica grid are carried out photoetching and etching, expose silicon substrate two end regions; Carrying out the injection of low doping source leakage ion, form low doping source with the corresponding position of diffusion drain terminal; Adopt silicon nitride to carry out the silicon nitride side wall of deposit and etching formation silicon face closed at both ends grid again; Leak ion in the employing source, low-doped source region that the silicon nitride side wall does not hide fully and inject the formation source electrode.Finished the manufacturing of adopting the high voltage transistor of non-homogeneous gate oxide.

Claims

1. high voltage transistor that adopts non-homogeneous gate oxide, leak in parallel by source electrode, high pressure trap, diffusion, and a silicon nitride side wall is respectively arranged at described region upper surface in parallel two ends, accompany two-layer grid layer up and down between the described both walls, the upper strata is a polysilicon, lower floor is an oxide layer, it is characterized in that: described oxide layer is non-homogeneous oxide layer.

2. the high voltage transistor of employing non-homogeneous gate oxide according to claim 1 is characterized in that: described non-homogeneous oxide layer is leaked oxidation bed thickness 100 dusts of the thickness of overlapping region than other channel regions at described polysilicon and described diffusion.

3. a manufacture method of making the high voltage transistor of the described employing non-homogeneous gate oxide of claim 1 is characterized in that, comprises following steps:

A. carry out high pressure trap and the injection of diffuse source ion in surface of silicon;

B. for the first time growing silicon oxide layer and deposit silicon nitride layer;

C. carry out photoetching in the zone that needs add thick grating oxide layer and etching forms the silicon nitride window;

D. growing silicon oxide for the second time forms the oxide layer step at raceway groove;

E. remove silicon nitride;

F. growing silicon oxide for the third time;

G. deposit polysilicon gate;

H. the photoetching of grid and etching;

I. low doping source is leaked ion and is injected the formation source electrode;

J. the deposit of silicon nitride side wall and etching;

K. the source is leaked ion and is injected the formation source electrode;

L. make refractory metal silicide, the dielectric layer before the depositing metalization carves contact hole;

M. deposited metal, etching is finished interconnection.

4. manufacture method according to claim 3 is characterized in that: the silicon oxide layer thickness of the described growth first time is 100 dusts.

5. manufacture method according to claim 3 is characterized in that: the silicon nitride layer thickness of the described deposit first time is 500 dusts.

6. manufacture method according to claim 3 is characterized in that: the silicon oxide layer thickness of the described growth second time is 100 dusts.

7. manufacture method according to claim 3 is characterized in that: the described silicon oxide layer thickness of growth for the third time is 500～1000 dusts.