CN103094281B

CN103094281B - A kind of 5V cmos device structure and manufacture method thereof

Info

Publication number: CN103094281B
Application number: CN201110348591.8A
Authority: CN
Inventors: 刘冬华; 钱文生; 胡君; 段文婷; 石晶
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2011-11-07
Filing date: 2011-11-07
Publication date: 2015-10-14
Anticipated expiration: 2031-11-07
Also published as: CN103094281A

Abstract

The invention discloses a kind of 5V cmos device structure, comprise: silicon substrate is formed P trap (N trap) and shallow trench isolation from, described P trap (N trap) is formed with gate oxide, described gate oxide is formed with gate polysilicon, isolation side walls is formed in gate oxide and gate polysilicon both sides, and described gate polysilicon and P trap (N trap) draw connection metal line by contact hole; Wherein, described gate oxide thickness non-uniform Distribution.The invention also discloses a kind of manufacture method of 5V cmos device structure.5VCMOS device architecture of the present invention and manufacture method thereof utilize marginal position thickness to be greater than centre position thickness, and the gate oxide of non-uniform thickness can improve the puncture voltage of circuit, can increase the withstand voltage stability of circuit.

Description

A kind of 5V cmos device structure and manufacture method thereof

Technical field

The present invention relates to field of semiconductor manufacture, particularly relate to a kind of 5V cmos device structure.The invention still further relates to a kind of manufacture method of 5V cmos device structure.

Background technology

5V device has been widely used in circuit design.5v voltage is a kind of input and output voltage adopted at present extensively, has demand widely to 5v device in current circuit reality, is all adopt them to design imput output circuit usually.For 5v cmos device, the key parameters such as its threshold voltage, drive current and cut-off current, everybody compares concern.But in the circuit application of reality, the puncture voltage of mosfet is also very important important parameter.The method of the monitoring mosfet puncture voltage that industry is general is as follows: substrate, source and grounded-grid, and drain terminal adds bias voltage, when the electric current of drain terminal reaches a certain standard (usual 100nA/um), just thinks that this voltage is puncture voltage.When the length long enough of raceway groove, puncture or occur in gate oxide, otherwise occur in source and drain-substrate pn knot between.When the puncture voltage of reality test 5v device, we can see that drain terminal electric current when puncturing is equal with the electric current that substrate monitors, therefore we can decision device puncture be due to source and drain-substrate between pn bind up one's hair to give birth to puncture and cause.But the puncture voltage of the puncture voltage of comparator device and source and drain pn knot, the breakdown potential that usual device electric breakdown strength is tied than source and drain pn is forced down.

As shown in Figure 1 and Figure 2, a kind of traditional 5V MOSFET element structure breakdown potential occurs in the position 10 be in immediately below gate edge of drain terminal.Industry is in order to improve the withstand voltage of device, and there is diverse ways in different companies, but mostly concentrates on knot engineering (Junction Engineering).Such as adopt codope drain terminal (Double Doped Drain); And for example increase withstand voltage by the extension prolongation of drain terminal, such as LDMOS structure.Through carefully studying punch-through and the mechanism of 5v device, by semiconductor technology and device simulation tool, we find, when device punctures, its breakdown potential occurs in the position be in immediately below gate edge of drain terminal, instead of our the metallurgical junction position of source and drain pn circle that it has been generally acknowledged that.This phenomenon gives us enlightenment: can not tie technologic change by pn and realize the raising of device electric breakdown strength.

Summary of the invention

The technical problem to be solved in the present invention is to provide the puncture voltage that a kind of 5V cmos device structure can improve circuit, can increase the withstand voltage stability of circuit.For this reason, present invention also offers kind of a manufacture method for 5V cmos device structure.

For solving the problems of the technologies described above, 5V cmos device structure of the present invention, comprising:

Silicon substrate is formed P trap (or N trap) and shallow trench isolation from, described P trap (or N trap) is formed with gate oxide, described gate oxide is formed with gate polysilicon, isolation side walls is formed in gate oxide and gate polysilicon both sides, and described gate polysilicon and P trap (or N trap) draw connection metal line by contact hole; Wherein, described gate oxide thickness non-uniform Distribution.

The thickness of described gate oxide edge is greater than the thickness of middle part.

The thickness of described gate oxide middle part is 10 nanometer to 20 nanometers.

The width of described gate oxide edge is 1 nanometer to 10 nanometer.

5V cmos device structure making process of the present invention, comprising:

(1) make in P type substrate shallow trench isolation from, make P trap;

(2) gate oxide is grown, growth gate polysilicon;

(3) gate polysilicon etching is carried out;

(4) hydrofluoric acid wet etching is carried out;

(5) carry out gate polysilicon to reoxidize;

(6) etch, make isolation side walls;

(7) P trap and gate polysilicon are drawn connection metal line by contact hole.

Further improvement, time implementation step (1), P type substrate makes N trap.

Further improvement, time implementation step (2), growth gate oxide thickness is 10 nanometer to 20 nanometers.

Further improvement, time implementation step (4), hydrofluoric acid wet etching is etched to middle part by position, gate oxide both sides of the edge, and etching width is 1 nanometer to 10 nanometer.

The gate oxide that 5V cmos device structure of the present invention utilizes non-uniform thickness to distribute can improve the puncture voltage of circuit, can increase the withstand voltage stability of circuit.

Accompanying drawing explanation

Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:

Fig. 1 is a kind of schematic diagram of traditional 5V cmos device structure.

Fig. 2 is the carrier impact power emulation schematic diagram of traditional 5V cmos device structure devices when puncturing.

The schematic diagram of Fig. 3 5V cmos device of the present invention structure.

Fig. 4 is the partial enlarged drawing of gate oxide in Fig. 2 (4).

Fig. 5 is that 5V cmos device structure of the present invention contrasts schematic diagram with the electric-field intensity distribution of drain terminal under identical bias voltage of traditional 5V CMOS

Fig. 6 is the flow chart of 5V cmos device structure manufacturer of the present invention.

Fig. 7 is the schematic diagram one of manufacturer of the present invention, the device architecture that its display implementation step (1), (2) are formed afterwards.

Fig. 8 is the schematic diagram two of manufacturer of the present invention, the device architecture that its display implementation step (3), (4) are formed afterwards.

Fig. 9 is the schematic diagram three of manufacturer of the present invention, the device architecture that its display implementation step (5) is formed afterwards.

Description of reference numerals

1 is P type substrate 2 are shallow trench isolations from

3 are P trap/N traps 4 is gate oxides

4.1 are gate oxide middle parts 4.2 is gate oxide edges

5 is gate polysilicons

6 is isolation side walls 7 is source/drain of MOSFET

8 are contact holes 9 is metal wires

10 is electric field concentrated areas

A is the Electric Field Distribution curve of 5V cmos device of the present invention

B is the Electric Field Distribution curve of traditional 5V cmos device

C is gate oxide marginal position.

Embodiment

As shown in Figure 3, Figure 4,5V cmos device structure of the present invention, comprising:

Silicon substrate is formed with P trap (or N trap) 1 and shallow trench isolation from 2, described P trap (or N trap) 1 is formed with gate oxide 4, described gate oxide 4 is formed with gate polysilicon 5, isolation side walls 6 is formed in gate oxide 4 and gate polysilicon 5 both sides, and described gate polysilicon 5 and P trap (or N trap) 1 draw connection metal line 9 by contact hole 8; Wherein, described gate oxidation 4 layer thickness non-uniform Distribution has gate oxide middle part 4.1 and gate oxide edge 4.2, and the thickness of gate oxide edge 4.2 is greater than the thickness of gate oxide middle part 4.1.5V cmos device structure of the present invention, it punctures the position still occurring in 10, but under identical drain terminal bias voltage, electric field strength weakens.

As shown in Figure 6, the manufacture method of 5V cmos device structure of the present invention, comprising:

(1) as shown in Figure 7, P type substrate 1 makes shallow trench isolation from 2, make P trap 3;

(2) gate oxide 4 is grown, growth gate polysilicon 5;

(3) as shown in Figure 8, gate polysilicon etching is carried out;

(4) carry out hydrofluoric acid wet etching, the edge 4.2 of gate oxide 4 is etched removal, retain gate oxide middle part 4.1;

(5) as shown in Figure 9, carry out gate polysilicon in gate oxide edge 4.2 and reoxidize, oxide layer edge 4.2 is filled up grid oxygen again, make the thickness of oxide layer edge 4.2 be greater than the thickness of gate oxide middle part 4.1;

(6) etch, make isolation side walls 6;

(7) P trap 2 and gate polysilicon 5 being drawn connection metal line 9 by contact hole 8, being formed as schemed device as shown in Figure 3.

Below through the specific embodiment and the embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims

1. a manufacture method for 5V cmos device structure, comprising:

(1) make in P type substrate shallow trench isolation from, make P trap;

(2) gate oxide is grown, growth gate polysilicon;

(3) gate polysilicon etching is carried out;

(4) carry out hydrofluoric acid wet etching by position, gate oxide both sides of the edge to middle part, the gate oxide marginal portion etching below gate polysilicon is removed;

(5) carry out gate polysilicon to reoxidize, the gate oxide marginal portion be etched is filled up grid oxygen again, make the thickness of gate oxide marginal portion be greater than the thickness in gate oxide centre position;

(6) etch, make isolation side walls;

2. 5V cmos device construction manufacturing method as claimed in claim 1, is characterized in that: time implementation step (1), P type substrate makes N trap.

3. 5V cmos device construction manufacturing method as claimed in claim 1, is characterized in that: time implementation step (2), and growth gate oxide thickness is 10 nanometer to 20 nanometers.

4. 5V cmos device construction manufacturing method as claimed in claim 3, it is characterized in that: time implementation step (4), hydrofluoric acid wet etching is etched to middle part by position, gate oxide both sides of the edge, and etching width is 1 nanometer to 10 nanometer.