CN110061053A - A kind of enhanced semiconductor transistor and preparation method thereof - Google Patents
A kind of enhanced semiconductor transistor and preparation method thereof Download PDFInfo
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- CN110061053A CN110061053A CN201910036676.9A CN201910036676A CN110061053A CN 110061053 A CN110061053 A CN 110061053A CN 201910036676 A CN201910036676 A CN 201910036676A CN 110061053 A CN110061053 A CN 110061053A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 150000004767 nitrides Chemical class 0.000 claims abstract description 159
- 230000004888 barrier function Effects 0.000 claims abstract description 93
- 238000000407 epitaxy Methods 0.000 claims abstract description 38
- 238000005530 etching Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 17
- 229910002704 AlGaN Inorganic materials 0.000 claims description 18
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 238000002161 passivation Methods 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000000926 separation method Methods 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 5
- 229910005535 GaOx Inorganic materials 0.000 claims description 4
- 239000004411 aluminium Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 4
- 229910052681 coesite Inorganic materials 0.000 claims description 4
- 229910052906 cristobalite Inorganic materials 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- 230000008569 process Effects 0.000 claims description 4
- 229910052682 stishovite Inorganic materials 0.000 claims description 4
- 229910052905 tridymite Inorganic materials 0.000 claims description 4
- 230000004913 activation Effects 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 3
- 230000000717 retained effect Effects 0.000 claims description 3
- 229910017105 AlOxNy Inorganic materials 0.000 claims description 2
- 229910004205 SiNX Inorganic materials 0.000 claims description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 2
- 229910052593 corundum Inorganic materials 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims description 2
- 229910017464 nitrogen compound Inorganic materials 0.000 claims description 2
- 150000002830 nitrogen compounds Chemical class 0.000 claims description 2
- 229910052594 sapphire Inorganic materials 0.000 claims description 2
- 239000010980 sapphire Substances 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 2
- 150000001875 compounds Chemical class 0.000 claims 4
- 235000012239 silicon dioxide Nutrition 0.000 claims 1
- 230000006378 damage Effects 0.000 abstract description 6
- 208000027418 Wounds and injury Diseases 0.000 abstract description 3
- 208000014674 injury Diseases 0.000 abstract description 3
- 230000008439 repair process Effects 0.000 abstract description 2
- 230000001276 controlling effect Effects 0.000 abstract 1
- 230000001105 regulatory effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 29
- 238000005036 potential barrier Methods 0.000 description 6
- 238000013459 approach Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000003471 anti-radiation Effects 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
Abstract
The present invention relates to a kind of enhanced semiconductor transistors and preparation method thereof.The device includes substrate, semiconductor epitaxial layers, the grid, source electrode and drain electrode of growth on substrate.Epitaxial layer includes nitride nucleating layer, nitride stress buffer layer, nitride channel, an epitaxial nitride barrier layer and p-type nitride layer and secondary epitaxy nitride barrier layer.It is etched by constituency, retains area of grid p-type nitride, make gate turn-off；By the constituency secondary epitaxy after exposure mask, secondary epitaxy nitride barrier layer is grown on an epitaxial nitride barrier layer, promotes access area conduction.By regulating and controlling the thickness and component of an epitaxial nitride barrier layer and secondary epitaxy nitride barrier layer, and then realize that more preferably gate turn-off and access area height lead ability.The method requires to reduce to etching technics, can effectively repair etching injury.The enhanced semiconductor device of high threshold voltage, high ducting capacity, high stability can be achieved in the final present invention.
Description
Technical field
The present invention relates to technical field of semiconductor device, more particularly, to a kind of enhanced semiconductor transistor and its
Preparation method.
Background technique
It is the third generation semiconductor material of representative since forbidden bandwidth is loose, thermal conductivity is high, breakdown electric field is high etc. using GaN material
Advantage has very big development space in high temperature, high frequency, anti-radiation, high-power applications field.
GaN base electronic device usually utilizes the Two-dimensional electron of high concentration at AlGaN/GaN heterostructure interface, high mobility
Gas work makes device have the advantages that conducting resistance is small, output electric current is big, switching speed is fast.However, also just because of this
AlGaN/GaN heterojunction structure (high two-dimensional electron gas, 2DEG), so that device is outside plus in the case that gate bias are zero, also day
So in the open state, as depletion type operates.
The realization of the normal enhancement device of high-performance is the significant challenge that GaN base electronic device faces, and is current science
The scientific and technological difficult point that boundary and industrial circle are generally acknowledged.High-performance normally closed device requires have positive threshold voltage and high threshold value electricity
Pressure value, to simplify device peripheral circuit, guarantee thrashing safety, so that it is guaranteed that device can reliably work.Device is realized normal
The general thinking of pass type characteristic is the 2DEG for retaining the conducting of access area height, i.e., does not influence the conducting resistance of device, while exhausting grid
Pole lower channels 2DEG, to realize that device grids are also at off state in the case where not applying voltage condition.Currently, industry is generally adopted
Normally-off GaN power electronic device is realized with 3 kinds of methods: (1) being insulated slot grid structure (MOSFET), and (2) cascode stage is coupled
Structure (Cascode) (3) p-type grid structure (p-GaN gate, as shown in Figure 1).
In above structure, since the advantages that p-type gate device structure is simple, threshold voltage uniformity, is by academia and industry
Boundary's concern.Currently, p-type gate device has been realized in industrialized development, there is Japan in the dominant company for carrying out the structure devices
Panasonic company, the EPC company in the U.S. and Canadian GaN Systems company.Currently, about p-type grid normally-off
The realization of AlGaN/GaN HEMT device, industry mainly use lithographic technique scheme, which becomes industry due to easy to accomplish
The method generallyd use, however there are many deficiencies for this method, such as when etching removes access area p-GaN material, due to etching
Uniformity is poor and there are problems that over etching, and etching can bring lattice damage to AlGaN potential barrier surface and introduce additional
Defect level can make the electrology characteristic of access area 2DEG degenerate, to influence the performance uniformity and stability of device.Separately
A kind of selection of technical scheme region growing p-GaN technology is also used, i.e., p-GaN layer is carried out on AlGaN/GaN heterojunction structure
Selective area growth, thus realize area of grid retain p-GaN layer, and access area without p-GaN layer structure (as shown in Fig. 2,
01 layer is SiO2Mask layer).However, the dynamic (dynamical) influence of epitaxial growth is limited by, when the grid length of device is smaller, that is to say, that
When growth window is very narrow, it is difficult to control using the growth that this method can have p-GaN material and adulterates the disadvantages of uneven, at present
In this respect without breakthrough.In addition, p-GaN layer hole concentration is not generally high, mainstream reported values are substantially no higher than 1 at present
×1018 cm-3, therefore the Al component of the AlGaN potential barrier below p-GaN layer in AlGaN/GaN heterojunction structure and thickness are general
It is smaller, it is commonly lower than 20% component and lower than 18nm thickness, this is advantageously implemented enhanced kind of operation, but will lead to connect simultaneously
The resistance for entering area increases, and relatively thin AlGaN potential barrier can also make the doped chemical (such as magnesium) in p-GaN layer be easier to expand
It is dissipated to channel, and then influences the reliability of device.
Summary of the invention
The present invention in order to overcome at least one of the drawbacks of the prior art described above, provides a kind of enhanced semiconductor transistor
And preparation method thereof, the device of preparation is able to achieve higher threshold voltage, lower conducting resistance and more stable work shape
State.
In order to solve the above technical problems, the technical solution adopted by the present invention is that: a kind of enhanced semiconductor transistor, including
Substrate, semiconductor epitaxial layers, grid, source electrode and the drain electrode of growth on substrate；Wherein, the epitaxial layer, is wrapped from bottom to top
Include nitride nucleating layer, nitride stress buffer layer, nitride channel, an epitaxial nitride barrier layer and p-type nitridation
Nitride layer and secondary epitaxy nitride barrier layer；The p-type nitride layer is only remained in epitaxial nitride gesture of area of grid
On barrier layer, the pinch off of Two-dimensional electron gas channel below grid is realized；After masking process, the secondary epitaxy nitride gesture
Barrier layer selective area growth is on an epitaxial nitride barrier layer other than area of grid.
In the present invention, by the p-type nitride other than the etching grid region of constituency, the p-type nitridation of area of grid is left
Object realizes the pinch off of grid groove.On secondary epitaxy nitride barrier layer selective area growth Yu Yici epitaxial nitride barrier layer,
Realize high conducting access area.Pass through the thickness of an epitaxial nitride barrier layer and secondary epitaxy nitride barrier layer of regulation simultaneously
And component, realize the grid source access area and grid leak access area of more preferably gate turn-off capability and high conducting.And the method can
With the bring access area damage of effective reparation etching, the requirement to etching technics is also reduced.It is final to realize high threshold voltage, height
The enhanced semiconductor device of ducting capacity, high stability.
Further, the substrate be Si substrate, Sapphire Substrate, silicon carbide substrates, GaN self-supported substrate or
Any one of AlN.
Further, the nitride stress buffer layer is any or combination containing AlN, AlGaN, GaN, SiN.
Further, the nitride nucleating layer is nitride layer containing Al.
Further, the nitride channel is GaN or AlGaN layer.
Further, an epitaxial nitride barrier layer is in AlGaN, AlInN, InGaN, AlInGaN, AlN
One or any of several combination, Al component can be 1%-30%, with a thickness of 1nm-30nm.
Further, the p-type nitride layer is GaN, AlGaN, AlInN or AlInGaN, and thickness is not less than 5nm.
Further, the secondary epitaxy nitride barrier layer is in AlGaN, AlInN, InGaN, AlInGaN, AlN
One or any of several combination, Al component can be 1%-40%, with a thickness of 1nm-40nm.
Further, also inserted with one layer of AlN between an epitaxial nitride barrier layer and nitride channel
Space separation layer, the space AlN separation layer thickness are 0.3nm-3nm.
Further, it is also hindered inserted with one layer of AlN between the p-type nitride layer and an epitaxial nitride barrier layer
Barrier, AlN barrier layer thickness are 0.3nm-5nm.
Further, the secondary epitaxy nitride barrier layer aluminium component is generally greater than an epitaxial nitride potential barrier
Layer.
Further, the p-type nitride layer of the area of grid is retained, and under the p-type nitride layer of area of grid
Epitaxial nitride barrier layer of the exterior domain of side is partially removed, and a remaining epitaxial nitride barrier layer thickness is 1-
30nm。
Further, also in place on the secondary epitaxy nitride barrier layer to grow cap or passivation layer；It is described
Cap be GaN, with a thickness of 0.5-8 nm；The passivation layer is SiN, with a thickness of 1-100 nm.
Further, the source electrode and drain electrode is Ohmic contact, and grid is Ohmic contact or Schottky contacts.
The present invention also provides a kind of enhanced semiconductor crystal tube preparation methods, comprising the following steps:
S1. growing nitride nucleating layer on substrate；
S2. the growing nitride stress-buffer layer on nitride nucleating layer；
S3. in nitride stress buffer growth nitride channel；
S4. an epitaxial nitride barrier layer is grown on nitride channel；
S5. p-type nitride layer is grown on an epitaxial nitride barrier layer；
S6. one layer of mask layer is deposited in p-type nitride layer；
S7. by photolithography patterning and the method for etching, retain the mask layer and p-type nitride layer for forming area of grid；
S8. selective area growth secondary epitaxy nitride barrier layer；
S9. the mask layer on area of grid is removed；
S10. the acceptor doping element in high-temperature annealing activation p-type nitride layer；
S11. dry etching completes device isolation, while etching source electrode and drain electrode ohmic contact regions；
S12. source electrode and drain electrode metal ohmic contact is formed on the source and drain regions；
S13. gate metal is formed in area of grid p-type nitride layer.
Traditional etch approach stated in the background prepares p-type grid enhancement device, requires equipment and technique non-
It is often harsh, there are problems that over etching and etching injury are brought, this can serious deterioration device property.The invention patent proposition is adopted
With etch approach combination constituency diauxic growth technology: removing the p-type nitride layer other than area of grid by dry etching first
And the epitaxial nitride barrier layer of part one time, retain the p-type nitride layer and an epitaxial nitride potential barrier of area of grid
Layer, to realize the pinch off of grid groove.Then, constituency secondary epitaxy is carried out, the online high temperature of MOCVD repairs an extension potential barrier
The etching injury (can be under nitrogen, ammonia or its mixed-gas environment) of layer, regrowth secondary epitaxy nitride barrier layer, from
And realize the high ducting capacity access area channel except grid region.Again and, can be by extension barrier layer of device and secondary
Extension barrier layer is redesigned, the thickness design of component and barrier layer including aluminium element in barrier layer, to reach out
Close being obviously improved for characteristic.
Compared with prior art, beneficial effect is: the present invention provides a kind of enhanced semiconductor transistor arrangement and systems
Preparation Method, using etch approach combination constituency secondary epitaxy technology, this is also that region is accessed other than area of grid and grid
Nitride barrier layer design provides feasibility, passes through epitaxial nitride barrier layer of design and secondary epitaxy nitride barrier layer
It is different to realize access area except the turn-off characteristic and area of grid of grid lower section hetero-junctions channel for layer structure while thus reasonable
The conductive capability of matter knot channel, this advantage are that do not had using current existing etch approach or selective area epitaxial p-GaN scheme
Standby.The technology of the present invention finally can effectively realize high threshold voltage, high conduction property, high stability enhancement device.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of enhancement device in existing etch approach.
Fig. 2 is the structural schematic diagram of enhancement device in existing selective area epitaxial p-GaN scheme.
Fig. 3-14 is the element manufacturing flow diagram of the embodiment of the present invention 1.
Figure 15 is the device architecture schematic diagram of the embodiment of the present invention 2.
Figure 16 is the device architecture schematic diagram of the embodiment of the present invention 3.
Figure 17 is the device architecture schematic diagram of the embodiment of the present invention 4.
Figure 18 is the device architecture schematic diagram of the embodiment of the present invention 5.
Figure 19 is the device architecture schematic diagram of the embodiment of the present invention 6.
Figure 20 is the device architecture schematic diagram of the embodiment of the present invention 7.
Figure 21 is the device architecture schematic diagram of the embodiment of the present invention 8.
Figure 22 is the device architecture schematic diagram of the embodiment of the present invention 9.
Figure 23 is the device architecture schematic diagram of the embodiment of the present invention 10.
Figure 24 is the device architecture schematic diagram of the embodiment of the present invention 11.
Figure 25 is the device architecture schematic diagram of the embodiment of the present invention 12.
Figure 26 is the device architecture schematic diagram of the embodiment of the present invention 13.
In figure, 1- substrate；2- nitride nucleating layer；3- nitride stress buffer layer；4- nitride channel；5- is primary
Epitaxial nitride barrier layer；6-p type nitride layer；7- secondary epitaxy nitride barrier layer；8- source electrode；9- drain electrode；10- grid；
The space 11-AlN separation layer；The nitride channel of 12- secondary epitaxy；13- cap or passivation layer；14- passivation layer；The source 15-
Pole field plate；16- bridges dielectric layer；17- drain electrode thick electrode；18-SiO2Mask layer；19- mask layer.
Specific embodiment
Attached drawing only for illustration, is not considered as limiting the invention；In order to better illustrate this embodiment, attached
Scheme certain components to have omission, zoom in or out, does not represent the size of actual product；To those skilled in the art,
The omitting of some known structures and their instructions in the attached drawings are understandable.Being given for example only property of positional relationship is described in attached drawing
Illustrate, is not considered as limiting the invention.
Embodiment 1:
It is as shown in figure 14 the device architecture schematic diagram of the present embodiment, a kind of semiconductor enhancement mode transistor, including substrate 1, life
Grow semiconductor epitaxial layers, grid 10, source electrode 8 and drain electrode 9 on substrate 1.Wherein, the epitaxial layer includes from bottom to top
Nitride nucleating layer 2, nitride stress buffer layer 3,4, epitaxial nitride barrier layers 5 of nitride channel and p-type nitrogen
Compound layer 6 and secondary epitaxy nitride barrier layer 7；P-type nitride layer 6 is only remained in grid 10 region one time epitaxial nitride gesture
On barrier layer 5, the pinch off of 10 lower section Two-dimensional electron gas channel of grid is realized.After masking process, secondary epitaxy nitride gesture
7 selective area growth of barrier layer is on an epitaxial nitride barrier layer 5 other than 10 region of grid.
The production method of above-mentioned semiconductor enhancement mode transistor is as shown in Fig. 3-Figure 14, comprising the following steps:
S1. the growing nitride nucleating layer 2 on substrate 1, as shown in Figure 3；
S2. the growing nitride stress-buffer layer 3 on nitride nucleating layer 2, as shown in Figure 4；
S3. in 3 growing nitride channel layer 4 of nitride stress buffer layer, as shown in Figure 5；
S4. an epitaxial nitride barrier layer 5 is grown on nitride channel 4, as shown in Figure 6；
S5. p-type nitride layer 6 is grown on an epitaxial nitride barrier layer 5, as shown in Figure 7；
S6. one layer of mask layer 19 is deposited in p-type nitride layer 6, as shown in Figure 8；
S7. by photolithography patterning and the method for etching, retain the mask layer 19 and p-type nitride layer 6 in 10 region of grid,
P-type layer except 10 region of grid all removes, and removes the epitaxial nitride barrier layer of part one time except 10 region of grid
5, as shown in Figure 9；
S8. lattice damage caused by high temperature online annealing reparation etching, and then selective area growth secondary epitaxy nitride barrier layer
Layer 7, as shown in Figure 10；
S9. the mask layer 19 on 10 region of grid is removed, as shown in figure 11；
S10. the acceptor doping element in high-temperature annealing activation p-type nitride layer 6；
S11. dry etching completes device isolation, while etching 9 ohmic contact regions of source electrode 8 and drain electrode, it is preferable that ohm
Contact area secondary epitaxy nitride barrier layer 7 is partially etched, and etching depth is no more than secondary epitaxy nitride barrier layer 7
Thickness, as shown in figure 12；
S12. 9 metal ohmic contacts of source electrode 8 and drain electrode are formed on 9 regions of source electrode 8 and drain electrode, as shown in figure 13；
S13. 10 metal of grid is formed in 10 region p-type nitride layer 6 of grid, as shown in figure 14.
So far, that is, the preparation process of entire device is completed.Figure 14 is the device architecture schematic diagram of embodiment 1.
Embodiment 2
As shown in figure 15 it is the device architecture schematic diagram of the present embodiment, is only that with the difference of 1 structure of embodiment: in embodiment 2
The one layer of space AlN separation layer 11 has also been sandwiched between nitride channel 4 and an epitaxial nitride barrier layer 5, with a thickness of
0.3-3 nm.For improving channel two-dimensional electron gas characteristic.
Embodiment 3
It is as shown in figure 16 the device architecture schematic diagram of the present embodiment, be only that with the difference of 1 structure of embodiment: embodiment 1 is
In, the epitaxial nitride barrier layer 5 of part one time except 10 region of grid is eliminated, and in embodiment 3 except 10 region of grid
The epitaxial nitride barrier layer 5 of part one time completely retain.Compared to embodiment 1, embodiment 3 requires harsher etching side
Case, such as oxygen-containing or fluorine-containing self termination etching condition of more advanced equipment.
Embodiment 4
It is as shown in figure 17 the device architecture schematic diagram of the present embodiment, be only that with the difference of 1 structure of embodiment: embodiment 1 is
In, the epitaxial nitride barrier layer 5 of part one time except 10 region of grid is eliminated, and in embodiment 4 except 10 region of grid
The all removals of an epitaxial nitride barrier layer 5.In embodiment 4, before growing secondary epitaxy nitride barrier layer 7,
The space thin layer AlN separation layer 11 can be grown, first with a thickness of 0.3-3 nm.
Embodiment 5
It is as shown in figure 18 the device architecture schematic diagram of the present embodiment, be only that with the difference of 1 structure of embodiment: embodiment 1 is
In, the epitaxial nitride barrier layer 5 of part one time except 10 region of grid is eliminated, and in embodiment 5 except 10 region of grid
The all removals of an epitaxial nitride barrier layer 5, and further eliminate partial nitridation object channel layer 4.In embodiment 5,
Before growing secondary epitaxy nitride barrier layer 7, the space thin layer AlN separation layer 11 can also be grown, first with a thickness of 0.3-3 nm.
Embodiment 6
It is as shown in figure 19 the device architecture schematic diagram of the present embodiment, be only that with the difference of 1 structure of embodiment: embodiment 1 is
In, the epitaxial nitride barrier layer 5 of part one time except 10 region of grid is eliminated, and in embodiment 6 except 10 region of grid
The all removals of an epitaxial nitride barrier layer 5, and further eliminate partial nitridation object channel layer 4, and then secondary two
The nitride channel 124 of one layer of secondary epitaxy has been sandwiched in length.The nitride channel 124 of secondary epitaxy with a thickness of 1-10
nm.In embodiment 6, before growing secondary epitaxy nitride barrier layer 7, the isolation of the space thin layer AlN preferably can also be first grown
Layer 11, with a thickness of 0.3-3 nm.
Embodiment 7
As shown in figure 20 it is the device architecture schematic diagram of the present embodiment, is only that with the difference of 1 structure of embodiment: in embodiment 7,
Ohmic contact regions secondary epitaxy nitride barrier layer 7 is all etched, and then etches into an epitaxial nitride barrier layer 5,
The extension barrier layer thickness finally retained is 1-10 nm.
Embodiment 8
As shown in figure 21 it is the device architecture schematic diagram of the present embodiment, is only that with the difference of 1 structure of embodiment: in embodiment 8,
There are also the cap grown in place or passivation layers 13 on secondary epitaxy nitride barrier layer 7.Preferably cap is GaN, thick
Degree is 0-8 nm.Passivation layer in place is SiNx, SiO2, Al2O3, AlOxNy, GaOx, GaOxNy, with a thickness of 0-100 nm.
Embodiment 9
As shown in figure 22 it is the device architecture schematic diagram of the present embodiment, is only that with the difference of 1 structure of embodiment: in embodiment 9,
It also offs normal on secondary epitaxy nitride barrier layer 7 passivation layer 14 of growth.Passivation layer 14 is silicon nitride, silica or oxidation
The high K mediums such as aluminium, or its laminated construction, growth technique LPCVD, PECVD, RTCVD, ALD, PEALD.
Embodiment 10
As shown in figure 23 it is the device architecture schematic diagram of the present embodiment, is only that with embodiment 1 and the difference of 9 structure of embodiment:
In embodiment 10, device grids 10 contain field plate structure.
Embodiment 11
As shown in figure 24 it is the device architecture schematic diagram of the present embodiment, is only that with embodiment 1 and the difference of 10 structure of embodiment:
In embodiment 10, device source electrode 8 contains field plate structure.
Embodiment 12
As shown in figure 25 it is the device architecture schematic diagram of the present embodiment, is only that with the difference of 1 structure of embodiment: in embodiment 1,
The shape of p-type nitride barrier layer is rectangle；In embodiment 12, the shape of p-type nitride barrier layer is trapezoidal.Furthermore, it is to be understood that p
Type nitride shape may be the structures such as arc, step type.
Embodiment 13
As shown in figure 26 it is the device architecture schematic diagram of the present embodiment, is only that with the difference of 1 structure of embodiment: embodiment 13
In, secondary epitaxy nitride barrier layer 7 is contained in the side of p-type nitride barrier layer.
Obviously, the above embodiment of the present invention be only to clearly illustrate example of the present invention, and not be pair
The restriction of embodiments of the present invention.Core of the invention content is secondary epitaxy barrier layer again after p-type nitride layer etching, one
Aspect can reduce the requirement to etching technics, on the other hand can be by epitaxial nitride barrier layer of design and secondary outer
Prolong the thickness and component of nitride barrier layer, and then obtains the enhanced device of high threshold voltage, high ducting capacity, high stability
Part.The present invention carries out illustrating for the relevant technologies only by several device architectures, and deforms or tie in other similar passing through
It is still feasible in the device solution of conjunction, herein without illustrating one by one.For those of ordinary skill in the art, upper
State it is bright on the basis of can also make other variations or changes in different ways, the technical solution in each embodiment include step
Rapid order, the selection of material category and parameter, process and selection of parameter etc., can suitably change combination, each to implement
Can also be appropriately combined between scheme, formed it will be appreciated by those skilled in the art that other embodiments.There is no need and unable to right
All embodiments are exhaustive.Any modification done within the spirit and principles of the present invention and changes equivalent replacement
Into etc., it should all be included in the scope of protection of the claims of the present invention.
Claims (10)
1. a kind of enhanced semiconductor transistor, including substrate (1), the semiconductor epitaxial layers being grown on substrate (1), grid
(10), source electrode (8) and drain electrode (9)；It is characterized in that, the epitaxial layer, includes nitride nucleating layer (2), nitrogen from bottom to top
Compound stress-buffer layer (3), nitride channel (4), an epitaxial nitride barrier layer (5) and p-type nitride layer (6)
With secondary epitaxy nitride barrier layer (7)；The p-type nitride layer (6) is only remained in grid (10) region one time extension nitrogen
On compound barrier layer (5), the pinch off of Two-dimensional electron gas channel below grid (10) is realized；By secondary outer after masking process
Prolong growth, an epitaxial nitride of secondary epitaxy nitride barrier layer (7) selective area growth other than grid (10) region
On barrier layer (5).
2. a kind of enhanced semiconductor transistor according to claim 1, which is characterized in that the substrate (1) is Si
Any one of substrate (1), Sapphire Substrate (1), silicon carbide substrates (1), GaN self-supported substrate (1) or AlN；The nitrogen
Compound stress-buffer layer (3) is any or combination containing AlN, AlGaN, GaN, SiN；The nitride nucleating layer (2) is
Nitride layer containing Al；The nitride channel (4) is GaN or AlGaN layer.
3. a kind of enhanced semiconductor transistor according to claim 1, which is characterized in that an epitaxial nitride
Object barrier layer (5) is one of AlGaN, AlInN, InGaN, AlInGaN, AlN or any several combination, and Al component can be with
For 1%-30%, with a thickness of 1nm-30nm；The p-type nitride layer (6) is GaN, AlGaN, AlInN or AlInGaN, and thickness is not
Lower than 5nm；The secondary epitaxy nitride barrier layer (7) is one of AlGaN, AlInN, InGaN, AlInGaN, AlN
Or any several combination, Al component can be 1%-40%, with a thickness of 1nm-40nm.
4. a kind of enhanced semiconductor transistor according to claim 3, which is characterized in that an epitaxial nitride
Also inserted with the one layer of space AlN separation layer (11), the space AlN separation layer between object barrier layer (5) and nitride channel (4)
(11) with a thickness of 0.3nm-3nm.
5. a kind of enhanced semiconductor transistor according to claim 3, which is characterized in that the p-type nitride layer
(6) also inserted with one layer of barrier layer AlN between an epitaxial nitride barrier layer (5), AlN barrier layer thickness is 0.3nm-
5nm。
6. a kind of enhanced semiconductor transistor according to claim 3, which is characterized in that the secondary epitaxy nitridation
Object barrier layer (7) aluminium component is generally greater than an epitaxial nitride barrier layer (5).
7. a kind of enhanced semiconductor transistor according to claim 3, which is characterized in that described grid (10) region
P-type nitride layer (6) be retained, an and extension nitrogen of the exterior domain of p-type nitride layer (6) lower section in grid (10) region
Compound barrier layer (5) is partially removed, and a remaining epitaxial nitride barrier layer (5) is with a thickness of 1-30nm.
8. a kind of enhanced semiconductor transistor according to any one of claims 1 to 7, which is characterized in that described two
It is also in place on secondary epitaxial nitride barrier layer (7) to grow cap or passivation layer 13；The cap is GaN, with a thickness of
0.5-8 nm；The passivation layer is SiNx, SiO2, Al2O3, AlOxNy, GaOx, GaOxNy, with a thickness of 1-100 nm.
9. a kind of enhanced semiconductor transistor according to claim 8, which is characterized in that the source electrode (8) and leakage
Pole (9) is Ohmic contact, and grid (10) is Ohmic contact or Schottky contacts.
10. a kind of enhanced semiconductor crystal tube preparation method, which comprises the following steps:
S1. the growing nitride nucleating layer (2) on substrate (1)；
S2. the growing nitride stress-buffer layer (3) on nitride nucleating layer (2)；
S3. in nitride stress buffer layer (3) growing nitride channel layer (4)；
S4. an epitaxial nitride barrier layer (5) is grown on nitride channel (4)；
S5. p-type nitride layer (6) are grown on an epitaxial nitride barrier layer (5)；
S6. one layer of mask layer (19) is deposited on p-type nitride layer (6)；
S7. by photolithography patterning and the method for etching, retain the mask layer (19) and p-type nitrogen for forming grid (10) region
Compound layer (6)；
S8. selective area growth secondary epitaxy nitride barrier layer (7)；
S9. the mask layer (19) on grid (10) region is removed；
S10. the acceptor doping element in high-temperature annealing activation p-type nitride layer (6)；
S11. dry etching completes device isolation, while etching source electrode (8) and drain electrode (9) ohmic contact regions；
S12. source electrode (8) and drain electrode (9) metal ohmic contact are formed on source electrode (8) and drain electrode (9) region；
S13. grid (10) metal is formed in grid (10) region p-type nitride layer (6).
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110690284A (en) * | 2019-11-19 | 2020-01-14 | 南方科技大学 | Gallium nitride-based field effect transistor and preparation method thereof |
| CN111244165A (en) * | 2020-01-15 | 2020-06-05 | 南方科技大学 | Preparation method of grid structure and grid structure |
| CN112614778A (en) * | 2020-12-18 | 2021-04-06 | 江苏能华微电子科技发展有限公司 | Method and device for forming multifunctional p-GaN electrode in GaN HEMT device |
| CN112786687A (en) * | 2021-02-08 | 2021-05-11 | 厦门市三安集成电路有限公司 | Semiconductor epitaxial structure, preparation method thereof and semiconductor device |
| CN112993012A (en) * | 2021-02-08 | 2021-06-18 | 厦门市三安集成电路有限公司 | Epitaxial structure of gallium nitride-based power device and preparation method thereof |
| CN113628962A (en) * | 2021-08-05 | 2021-11-09 | 苏州英嘉通半导体有限公司 | III-nitride enhanced HEMT device and manufacturing method thereof |
| CN113838931A (en) * | 2021-08-23 | 2021-12-24 | 华灿光电（浙江）有限公司 | High electron mobility transistor chip and preparation method thereof |
| WO2024001693A1 (en) * | 2022-06-29 | 2024-01-04 | 华为技术有限公司 | Device, module, and apparatus |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110210377A1 (en) * | 2010-02-26 | 2011-09-01 | Infineon Technologies Austria Ag | Nitride semiconductor device |
| CN102318047A (en) * | 2009-03-23 | 2012-01-11 | 松下电器产业株式会社 | Semiconductor device and method of manufacturing the device |
| CN103715248A (en) * | 2012-09-28 | 2014-04-09 | 富士通株式会社 | Semiconductor device and method for manufacturing a semiconductor device |
| CN104037081A (en) * | 2013-03-08 | 2014-09-10 | 首尔半导体株式会社 | Heterojunction transistor and method of fabricating the same |
| US20140252368A1 (en) * | 2013-03-08 | 2014-09-11 | Samsung Electronics Co., Ltd. | High-electron-mobility transistor |
| CN106486363A (en) * | 2015-09-01 | 2017-03-08 | 中国科学院苏州纳米技术与纳米仿生研究所 | Group III-nitride enhancement mode HEMT based on p-type layer and preparation method thereof |
| CN107768252A (en) * | 2017-11-03 | 2018-03-06 | 中山大学 | A kind of normally-off GaN base MOSFET structure of the high conduction property of high threshold voltage and preparation method thereof |
| US20180248027A1 (en) * | 2015-10-27 | 2018-08-30 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor device |
| CN209592046U (en) * | 2019-01-15 | 2019-11-05 | 中山大学 | A kind of enhanced semiconductor transistor |
-
2019
- 2019-01-15 CN CN201910036676.9A patent/CN110061053A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102318047A (en) * | 2009-03-23 | 2012-01-11 | 松下电器产业株式会社 | Semiconductor device and method of manufacturing the device |
| US20110210377A1 (en) * | 2010-02-26 | 2011-09-01 | Infineon Technologies Austria Ag | Nitride semiconductor device |
| CN103715248A (en) * | 2012-09-28 | 2014-04-09 | 富士通株式会社 | Semiconductor device and method for manufacturing a semiconductor device |
| CN104037081A (en) * | 2013-03-08 | 2014-09-10 | 首尔半导体株式会社 | Heterojunction transistor and method of fabricating the same |
| US20140252368A1 (en) * | 2013-03-08 | 2014-09-11 | Samsung Electronics Co., Ltd. | High-electron-mobility transistor |
| CN106486363A (en) * | 2015-09-01 | 2017-03-08 | 中国科学院苏州纳米技术与纳米仿生研究所 | Group III-nitride enhancement mode HEMT based on p-type layer and preparation method thereof |
| US20180248027A1 (en) * | 2015-10-27 | 2018-08-30 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor device |
| CN107768252A (en) * | 2017-11-03 | 2018-03-06 | 中山大学 | A kind of normally-off GaN base MOSFET structure of the high conduction property of high threshold voltage and preparation method thereof |
| CN209592046U (en) * | 2019-01-15 | 2019-11-05 | 中山大学 | A kind of enhanced semiconductor transistor |
Non-Patent Citations (1)
| Title |
|---|
| 杨帆;何亮;郑越;沈震;刘扬;: "选择区域外延槽栅结构GaN常关型MOSFET的研究", 电源学报, no. 04, pages 14 - 20 * |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110690284A (en) * | 2019-11-19 | 2020-01-14 | 南方科技大学 | Gallium nitride-based field effect transistor and preparation method thereof |
| CN111244165A (en) * | 2020-01-15 | 2020-06-05 | 南方科技大学 | Preparation method of grid structure and grid structure |
| CN112614778A (en) * | 2020-12-18 | 2021-04-06 | 江苏能华微电子科技发展有限公司 | Method and device for forming multifunctional p-GaN electrode in GaN HEMT device |
| CN112786687A (en) * | 2021-02-08 | 2021-05-11 | 厦门市三安集成电路有限公司 | Semiconductor epitaxial structure, preparation method thereof and semiconductor device |
| CN112993012A (en) * | 2021-02-08 | 2021-06-18 | 厦门市三安集成电路有限公司 | Epitaxial structure of gallium nitride-based power device and preparation method thereof |
| CN113628962A (en) * | 2021-08-05 | 2021-11-09 | 苏州英嘉通半导体有限公司 | III-nitride enhanced HEMT device and manufacturing method thereof |
| CN113628962B (en) * | 2021-08-05 | 2024-03-08 | 苏州英嘉通半导体有限公司 | III-nitride enhanced HEMT device and manufacturing method thereof |
| CN113838931A (en) * | 2021-08-23 | 2021-12-24 | 华灿光电（浙江）有限公司 | High electron mobility transistor chip and preparation method thereof |
| WO2024001693A1 (en) * | 2022-06-29 | 2024-01-04 | 华为技术有限公司 | Device, module, and apparatus |
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