WO2024001693A1 - Device, module, and apparatus - Google Patents

Abstract

Provided are a device, a module, and an apparatus, which have good reliability and long service life. The device can comprise a first semiconductor layer provided on a substrate, a second semiconductor layer epitaxially formed on the first semiconductor layer, and a gate structure provided on the second semiconductor layer. The oxidation of a region, projected by the gate structure in the vertical direction, in the second semiconductor layer facilitates eliminating the polarization effect of the second semiconductor layer on the first semiconductor layer and reducing the carrier concentration of the first semiconductor layer in a region under a gate, such that a threshold voltage of the gate is greater than 0, thereby realizing an enhanced FET.

Description

A device, module and device

This application claims priority to the Chinese patent application submitted to the State Intellectual Property Office of China on June 29, 2022, with application number 202210778240.9 and the invention name "a device, module and equipment", the entire content of which is incorporated by reference. in this application.

Technical field

This application relates to the field of semiconductor technology, and in particular to a device, module and equipment.

Background technique

With the development of semiconductor technology, Field Effect Transistor (FET) based on semiconductor materials is widely used in the preparation of electronic modules. The performance of FET determines the performance of electronic modules. Compared with depletion-mode FETs, enhancement-mode FETs have the advantages of improving the safety of electronic modules, reducing losses, and simplifying circuit design.

The current method of realizing enhancement mode FET includes a recessed gate structure, which involves etching the barrier layer in the FET, which easily produces a large number of defects in the barrier layer, reduces the gate leakage of the FET, and increases the gate breakdown voltage, which is not conducive to Improve the reliability and life of electronic modules.

Contents of the invention

Provide a device, module and equipment with good reliability and lifespan.

In a first aspect, a device is provided. The device may include a first semiconductor layer disposed on a substrate, a second semiconductor layer epitaxially formed on the first semiconductor layer, and a gate disposed on the second semiconductor layer. The second semiconductor layer in the first region is oxidized. Wherein, the first region includes a region where the gate structure is projected in the second semiconductor layer in a vertical direction.

Oxidizing the second semiconductor layer in the first region is beneficial to eliminating the polarization effect of the second semiconductor layer on the first semiconductor layer in the region below the gate, reducing the carrier concentration of the first semiconductor layer in the region below the gate, so that the gate electrode The threshold voltage (Vth) is greater than 0, realizing enhancement mode FET. In addition, the oxidized second semiconductor layer in the first region has good insulation, which is equivalent to adding a dielectric layer under the gate structure, which is beneficial to reducing gate leakage, increasing gate breakdown voltage, and improving device reliability. and service life.

Compared with etching the second semiconductor layer in the first region to deplete carriers in the first semiconductor layer under the gate, the device provided by the first aspect can deplete the carriers under the gate without etching the second semiconductor layer. Therefore, it is beneficial to reduce defects caused by etching damage in the second semiconductor layer, increase gate breakdown voltage, and reduce gate leakage.

"The area where the gate structure projects in the vertical direction in the second semiconductor layer" may be in the shape of a column, with one bottom surface of the column being the contact surface between the gate structure and the second semiconductor layer, and the height of the column being less than Or equal to the thickness of the second semiconductor layer along the vertical direction, that is, the thickness of the second semiconductor layer where oxidation occurs is not limited. "Vertical direction" may refer to the vertical direction when the plane of the substrate is used as the horizontal plane, or it may refer to the direction perpendicular to the plane of the substrate.

Optionally, due to the accuracy of the oxidation process, the first region may include, in addition to the first under-gate region, other regions adjacent to the first under-gate region.

Optionally, the device may also include a source electrode and a drain electrode. The source electrode and the drain electrode are respectively connected to the second semiconductor Body layers are connected. The positions of the source electrode and the drain electrode are not limited. For example, the source electrode and the drain electrode may be disposed on the second semiconductor layer, or the source electrode and the drain electrode may pass through the second semiconductor layer into the first semiconductor layer. layer, it is helpful to reduce the series impedance of the device and improve the efficiency of the device.

Optionally, the second semiconductor layer in the second region is not oxidized. The second region is another region of the second semiconductor layer adjacent to the first region. The size of the second region is not limited. For example, the second region may include a region between the source electrode and the gate structure and a region between the gate structure and the drain electrode. That is to say, the second semiconductor layer between the source gate and the second semiconductor layer between the gate drain is not oxidized, and the first semiconductor layer between the source gate and the first semiconductor layer between the gate drain still produces relatively A high concentration of carriers is beneficial to reducing the series resistance of the device.

Optionally, the thickness of the second semiconductor layer in the first region may be greater than or equal to the thickness of the second semiconductor layer in the second region, and the second region is the second region between the second semiconductor layer and the second region. Other regions adjacent to the first region are thus prevented from reducing the output impedance and gate breakdown voltage of the device due to etching of the second semiconductor layer in the first region.

Optionally, the second semiconductor layer may include oxygen in the first region. The oxygen element has high stability in the second semiconductor layer and is not easy to migrate to other areas other than the first area, which is beneficial to improving the reliability of the device.

Optionally, the gate structure may include a gate electrode and a dielectric layer, and the dielectric layer is disposed between the gate electrode and the second semiconductor layer. By adding a dielectric layer between the gate electrode and the second semiconductor layer, it is helpful to further reduce the leakage of the gate electrode, increase the gate breakdown voltage, improve the reliability of the device, and extend the service life of the device.

Optionally, the dielectric layer may be aluminum oxide (Al2O3), silicon nitride (SiNx), hafnium oxide (HfO2), silicon dioxide (SiO2), or silicon oxynitride (SiON).

Optionally, the device further includes a passivation protection layer disposed on the second semiconductor layer, and the gate structure passes through the passivation protection layer to connect to the second semiconductor layer. The passivation protective layer is conducive to strengthening the polarization effect of the barrier layer and increasing the concentration of two-dimensional electron gas (2DEG). In addition, the passivation protective layer is conducive to enhancing the device's resistance to moisture and heat, improving the reliability of the device, and reducing the surface state of the barrier layer, reducing surface leakage current and surface charge traps of the device.

Optionally, the source electrode and the drain electrode pass through the passivation protection layer respectively to connect to the second semiconductor layer.

Optionally, the thickness of the passivation protective layer is greater than the thickness of the dielectric layer.

Optionally, the first semiconductor layer and the second semiconductor layer each include a Group III nitride semiconductor. Group III nitride semiconductor materials have strong piezoelectric polarization and spontaneous polarization effects, which can significantly increase the concentration and mobility of 2DEG produced on heterostructures (such as AlGaN/GaN), giving the manufactured electronic devices powerful current handling capabilities.

Optionally, the first semiconductor layer includes gallium element and nitrogen element, and the second semiconductor layer includes aluminum element and nitrogen element.

Optionally, the second semiconductor layer includes a first barrier layer epitaxially on the first semiconductor layer and a second barrier layer epitaxially on the first barrier layer. Optionally, the lattice matching degree between the first barrier layer and the first semiconductor layer is better than the lattice matching degree between the second barrier layer and the first semiconductor layer. In this way, it is beneficial to reduce the Stress defects in the second semiconductor layer due to lattice mismatch. Optionally, the device further includes the substrate.

In a second aspect, a module is also provided, including the device described in the first aspect or any possible implementation manner of the first aspect.

Optionally, the module is a power module or a radio frequency module. Optionally, the power module may include one or more transistor elements, at least one of which may include the first aspect or any possible implementation of the first aspect. the device described. Optionally, the radio frequency module can include an amplifier. Any of the previously provided devices can be used in this amplifier.

Optionally, the amplifier may include a power amplifier and/or a low noise amplifier. Optionally, the radio frequency module may also include radio frequency switches and/or filters. Any of the devices provided above can be applied to power amplifiers and/or low noise amplifiers and/or RF switches.

In a third aspect, a device is also provided, including the module as described in the second aspect, which advantageously achieves high reliability and long life.

Taking the device including the radio frequency module provided above as an example, the device can be, for example, a wireless terminal device (such as a mobile phone or a smart watch) or a customer premise equipment (customer premise equipment, CPE) or a wireless router.

Taking the device including the power module provided above as an example, the device can be any device that needs power supply. For example, the device may be a communication device, a home electronic device, an automotive electronic device, an aerospace device, or the like.

Description of drawings

Figure 1 schematically shows a possible cross-sectional view of the device, and the gate voltage is 0V;

Figure 2 exemplarily shows a first semiconductor layer and a second semiconductor layer in contact with each other, as well as energy band diagrams of the two;

Figure 3 schematically shows another possible cross-sectional view of the device, and the gate voltage is greater than Vth;

Figure 4 schematically shows another possible cross-sectional view of the device, and the gate voltage is 0V;

Figure 5 schematically shows another possible cross-sectional view of the device, and the gate voltage is 0V;

Figure 6 exemplarily shows the simulation test results of the device shown in Figure 5;

7 to 12 exemplarily illustrate the process of preparing the device shown in FIG. 4 .

Detailed ways

A device is provided, a cross-sectional view of the device is shown in Figure 1. Referring to FIG. 1 , the device may include a substrate, a first semiconductor layer disposed on the substrate, a second semiconductor layer epitaxially formed on the first semiconductor layer, a gate structure, a source electrode and a drain electrode.

The first semiconductor layer can be formed on the substrate using thin film growth technologies such as metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (Molecular Beam Epitaxy, MBE). The material of the first semiconductor layer is not limited. For example, the first semiconductor layer may include Group III nitride. Optionally, the first semiconductor layer may include at least gallium (Ga) and nitrogen (N). For example, the first semiconductor layer may include gallium nitrogen (GaN). The thickness of the first semiconductor layer is not limited, for example, the thickness of the first semiconductor layer is 50 nm to 6000 nm.

The second semiconductor layer can be formed on the first semiconductor layer using a thin film growth technology such as MOCVD or MBE. The material of the second semiconductor layer is not limited. For example, the second semiconductor layer may include Group III nitride. Optionally, the second semiconductor layer may include at least aluminum element (Al) and nitrogen element (N). For example, the second semiconductor layer may include AlN, indium aluminum nitride (InAlN) or aluminum gallium nitride (AlGaN) or scandium aluminum nitride. (ScAlN) or at least one of indium gallium aluminum nitride (InGaAlN). The thickness of the second semiconductor layer is not limited, for example, the thickness of the second semiconductor layer does not exceed 10 nm.

The second semiconductor layer may be a single-layer structure or a multi-layer structure, and the multi-layer structure may include at least two layers. Referring to FIG. 1 , the second semiconductor layer includes a first barrier layer epitaxially on the first semiconductor layer and a second barrier layer epitaxially on the first barrier layer. Optionally, the lattice matching between the first barrier layer and the first semiconductor layer is better than that between the second barrier layer and the first semiconductor layer. The lattice matching degree of the first semiconductor layer, in other words, the difference between the lattice parameter of the first barrier layer and the lattice parameter of the first semiconductor layer is smaller than the lattice matching of the second barrier layer. The difference between the lattice parameter and the lattice parameter of the first semiconductor layer. In this way, it is beneficial to increase the thickness of the second semiconductor layer to increase the interface polarization between the second semiconductor layer and the first semiconductor layer on the premise of reducing stress defects caused by lattice mismatch in the second semiconductor layer. Effect, generate more carriers, increase the current density and power density of the device output, and are conducive to the miniaturization of high-power devices.

For example, the first barrier layer may include AlN or AlGaN, with a thickness not exceeding 5 nm, and the second barrier layer may include AlN (such as first barrier AlGaN, second barrier AlN), InAlN or AlGaN or ScAlN or InGaAlN, with a thickness of No more than 5nm. The ratio between the elements in the first barrier layer is not limited. Taking the first barrier layer including AlGaN as an example, the proportion of Al component is 50% to 100%. The ratio between the elements in the second barrier layer is not limited. Taking the second barrier layer including InAlN as an example, the proportion of In component is 0% to 20%. Taking the second barrier layer including ScAlN as an example, the proportion of Sc component is 0% to 30%.

FIG. 1 only illustrates the structure of the second semiconductor layer, but does not limit the structure of the second semiconductor layer. For example, compared with the double-layer structure shown in FIG. 1 , the second semiconductor layer may include more layers, or only Includes one layer.

Contact between the first semiconductor layer and the second semiconductor layer may form a junction, and a region of the junction located in the first semiconductor layer and/or a region located in the second semiconductor layer may generate carriers. The type of carriers is not limited. For example, the carriers may be electrons or holes.

FIG. 2 takes the first semiconductor layer and the second semiconductor layer as GaN and AlN respectively as an example to illustrate the contacting first semiconductor layer and the second semiconductor layer and their energy band diagrams. Relying on the strong spontaneous polarization effect and piezoelectric polarization effect between the AlN layer and GaN layer, a large number of 2DEG will be induced in the AlN/GaN heterojunction channel. Figure 2 represents 2DEG as a circle filled with black. AlN has a wider band gap than GaN, forming a triangular potential well at the heterojunction interface. The conduction band Ec on the GaN side is lower than the Fermi level Ef, and a large number of electrons are accumulated in the potential well and are restricted from moving laterally in the thin layer at the interface. Field Effect Transistor (FET) prepared based on this heterojunction is generally depletion type. For depletion-mode FETs, to turn off the device, a negative gate voltage must be applied, which will increase the complexity of the gate drive design, and is prone to misleading turn-on, potential threats of shoot-through, and reducing circuit stability and safety. For enhancement-mode FET, it will only turn on when positive bias is applied, which reduces circuit complexity, and the stability and safety of enhancement-mode FET are also better.

In order to obtain an enhancement mode FET, the second semiconductor layer in the first region may be oxidized, wherein the first region includes a region where the gate structure projects in the vertical direction in the second semiconductor layer (referred to as the first under-gate region). "Vertical direction" may refer to the vertical direction when the plane of the substrate is used as the horizontal plane, or it may refer to the direction perpendicular to the plane of the substrate. In Figure 1, a rectangular area filled with diagonal lines represents the cross-section of the area under the first gate. Affected by the accuracy of the oxidation process, the first region may include, in addition to the first under-gate region, other regions adjacent to the first under-gate region. The following description takes the first region as the under-gate region in the second semiconductor layer as an example.

Other regions of the second semiconductor layer adjacent to the first region are referred to as second regions. In FIG. 1 , a rectangular area filled with white in the second semiconductor layer represents a cross-section of the second area. Optionally, the second semiconductor layer in the second region is not oxidized. The size of the second region is not limited. For example, referring to FIG. 1 , the second region may include a region between the source electrode and the gate structure and a region between the gate structure and the drain electrode.

The method of oxidizing the second semiconductor layer in the first region is not limited. For example, the second semiconductor layer in the first region may be oxidized by surface oxidation such as ion implantation or plasma oxidation. The type of oxidant used to oxidize the second semiconductor layer is not limited. Optionally, the oxidizing agent may be an oxidizing agent containing oxygen elements. Correspondingly, through the oxidation of oxygen-containing elements After the second semiconductor layer in the first region is oxidized with an agent, compared with the unoxidized second semiconductor layer, the second semiconductor layer in the first region further contains at least additional oxygen element (O). If the second semiconductor layer is a single layer of AlN grown epitaxially on the first semiconductor layer, then after the second semiconductor layer in the first region is oxidized, the second semiconductor layer may include Al, N and O in the first region. If the second semiconductor layer includes a first barrier layer and a second barrier layer as shown in Figure 1, and the first barrier layer is AlN epitaxially formed on the first semiconductor layer, the second barrier layer is AlN epitaxially formed on the first semiconductor layer. Then, after the second semiconductor layer in the first region is oxidized, the first barrier layer may include Al, N and O in the first region, and the second barrier layer may include In, Al, N and O. Optionally, the oxygen content of the second semiconductor layer in the first region is greater than or equal to 2%. The oxygen element has high stability in the second semiconductor layer and is not easy to migrate to other areas other than the first area, which is beneficial to improving the reliability of the device.

Generally, the thickness of the second semiconductor layer after oxidation will increase, so that the thickness of the second semiconductor layer in the first region may be greater than the thickness of the second semiconductor layer in the second region. It can be understood that in the device shown in FIG. 1 , the gate structure is disposed on the protrusion on the upper surface of the second semiconductor layer, so the gate structure can be called a raised gate structure.

The area where the gate structure is projected in the first semiconductor layer in the vertical direction is simply referred to as the second under-gate area. In FIG. 1 , a rectangular area within a dotted frame in the first semiconductor layer represents the cross-section of the area under the second gate. After the second semiconductor layer in the first gate lower region is oxidized, its energy band structure changes, resulting in the junction formed between it and the first semiconductor layer in the second gate lower region being unable to continue to induce a large number of carriers (for example, 2DEG), the first semiconductor layer is depleted of carriers in the region under the second gate. Since the second semiconductor layer in the second region is not oxidized, a large number of carriers are still generated in the junction formed between it and the first semiconductor layer, which is beneficial to reducing the series resistance of the device. In FIG. 1 , a circle filled with black represents the carriers induced by the second semiconductor layer in the first semiconductor layer.

The source electrode and the drain electrode of the FET need to be electrically connected through a conductive channel in the first semiconductor layer. However, referring to FIG. 1 , after the second semiconductor layer in the first region is oxidized, the carriers of the first semiconductor layer in the region under the second gate are depleted, and the conductive communication in the first semiconductor layer is interrupted. In this way, when the bias voltage of the gate structure is zero, there is no electrical connection between the source electrode and the drain electrode, and the FET is in a disconnected state. Referring to Figure 3, when a forward bias is applied to the gate structure, the first semiconductor layer in the third region generates carriers under the action of the electric field, and a continuous conductive channel, source electrode and drain are generated in the first semiconductor layer An electrical connection is made between the electrodes and the FET is turned on. It can be seen that the FET with the above convex gate structure can behave as an enhancement mode FET.

By etching the second semiconductor layer to prepare a recessed gate structure, the carriers of the first semiconductor layer in the third region can also be depleted to obtain an enhancement mode FET. Compared with enhancement-mode FETs with concave gate structures, enhancement-mode FETs with convex gate structures have higher output impedance and gate breakdown voltage. This is because when preparing the convex gate structure shown in Figure 1, the carriers of the first semiconductor layer in the third region can be depleted through surface oxidation without etching the second semiconductor layer, and the second semiconductor layer can be reduced. Defects caused by etching in the semiconductor layer reduce gate leakage and increase gate breakdown voltage.

Continuing to refer to FIG. 1 , the gate structure is disposed on the second semiconductor layer. The gate structure may include a gate electrode. The gate electrode is a conductive material, and the specific type of the conductive material is not limited. For example, the conductive material can be a metal element or alloy including at least one element among titanium, aluminum, nickel, and gold. The size of the gate electrode is not limited, for example, the gate length of the gate electrode is 30 nm to 250 nm.

By oxidizing the second semiconductor layer in the first region, it not only helps to deplete the carriers of the first semiconductor layer in the third region, but also reduces the carrier concentration of the second semiconductor layer in the first region, reducing the gate potential. The barrier layer becomes a dielectric layer, forming a metal-intermediate The metal-insulator-semiconductor (MIS) junction is beneficial to reducing gate leakage and increasing gate breakdown voltage.

Optionally, referring to FIG. 1 , the gate structure may further include a dielectric layer (or gate dielectric layer) disposed between the gate electrode and the second semiconductor layer. The material of the dielectric layer is not limited. For example, the dielectric layer may be aluminum trioxide (Al2O3), silicon nitride (SiNx), hafnium oxide (HfO2), silicon dioxide (SiO2), or silicon oxynitride (SiON). The thickness of the dielectric layer is not limited, for example, the thickness of the dielectric layer does not exceed 10 nm. By adding a dielectric layer between the gate electrode and the second semiconductor layer, it is helpful to further reduce the leakage of the gate electrode, increase the gate breakdown voltage, improve the reliability of the device, and extend the service life of the device.

The source electrode and the drain electrode of the device are respectively connected to the second semiconductor layer. Referring to FIG. 1 , the source electrode and the drain electrode may be respectively disposed on the second semiconductor layer on both sides of the gate structure.

The distance between the source electrode and the gate structure is not limited. For example, the distance between the source electrode and the gate structure (or gate-source distance) is 0.1 μm to 1.5 μm. The distance between the drain electrode and the gate structure is not limited. For example, the distance between the drain electrode and the gate structure (or gate-drain distance) is 0.1 μm to 1.5 μm. The distance between the source electrode and the drain electrode is not limited. For example, the distance between the source electrode and the drain electrode (or source-drain distance) is 0.2 μm to 3 μm. In this way, it is helpful to reduce the series resistance of the device, so that when the device operates at low voltage (such as less than 12V or even less than 5V), it still has higher efficiency, gain, bandwidth and switching frequency, covering the operating frequency of the device from 2GHz to 150GHz.

In FIG. 1 , the source electrode and the drain electrode are arranged on the second semiconductor as an example and not a limitation. The source electrode and the drain electrode can also be connected to the second semiconductor layer through other arrangement methods. For example, the source electrode and the drain electrode may penetrate the second semiconductor layer into the first semiconductor layer in the vertical direction, in other words, penetrate the entire second semiconductor layer and part of the first semiconductor layer in the vertical direction.

The source and drain are conductive materials, and the specific type of the conductive material is not limited. For example, the conductive material can be a metal element or alloy including at least one element among titanium, aluminum, nickel and gold, or it can be n-type GaN, n-type InGaN or other highly conductive n-type semiconductor materials, n-type carrier concentration >1E19/cm3.

The substrate shown in FIG. 1 may be composed of a single layer of material, and the type of the material is not limited. For example, the substrate may be any one of GaN substrate, SiC substrate, sapphire substrate, and Si substrate. The single-layer material may be a high-resistance material, for example, its sheet resistance is greater than 5000Ω/□.

Alternatively, the substrate shown in FIG. 1 may be composed of multiple layers of materials, and the type of material of any layer in the substrate is not limited. For example, the substrate may include three layers of materials. The first layer of the three layers of materials may be, for example, any one of GaN substrate, SiC substrate, sapphire substrate, and Si substrate. The second layer may be any one of GaN substrate, SiC substrate, sapphire substrate, and Si substrate. The nucleation and stress control layer (for example, AlN) is epitaxially formed on the first layer, and the third layer may be a buffer layer epitaxially formed on the second layer. This third layer may be, for example, a doped GaN layer. The doping ratio is not limited. For example, the doping element may be iron or carbon. The doping concentration is not limited. Taking carbon doping as an example, the doping concentration can be greater than 1E18/cm3, which will help increase the resistivity of the third layer and reduce leakage.

Alternatively, the first semiconductor layer may be formed on a substrate other than the substrate shown in FIG. 1 , and then the first semiconductor layer may be transferred to the substrate shown in FIG. 1 . Alternatively, the first semiconductor layer may be formed on a substrate other than the substrate shown in FIG. 1 and other structures may be provided on the first semiconductor layer, and then the first semiconductor layer and the other structures may be transferred to on the substrate shown in Figure 1. The material of the substrate is not limited as long as the substrate can carry a structure disposed on the substrate. For example, the substrate can be a substrate of semiconductor material (such as a Si substrate), or the substrate can A substrate (such as a circuit board) made of materials other than semiconductor materials.

FIG. 1 only illustrates the structure of the device, but does not limit the device.

Optionally, the device may include fewer structures than in Figure 1. For example, after the first semiconductor layer is formed on the substrate shown in Figure 1, the substrate is removed by grinding or other processes.

Optionally, compared with the structure shown in Figure 1, the device can include more other structures. For example, referring to Figure 4, the device can also include a passivation protection layer and a gate field plate.

The passivation protection layer may be disposed on the second semiconductor layer. The passivation protective layer is conducive to enhancing the device's resistance to moisture and heat, improving the reliability of the device, and reducing the surface state of the barrier layer, reducing surface leakage current and surface charge traps of the device. Optionally, the passivation protective layer may include silicon nitrogen (SiNx), which is beneficial to strengthening the polarization effect of the barrier layer and inducing more carriers (for example, 2DEG) in the first semiconductor layer. The thickness of the passivation protection layer is not limited, for example, the thickness of the passivation protection layer is 13 nm to 500 nm.

The passivation protection layer may be a single-layer structure or a multi-layer structure, and the multi-layer structure may include at least two layers. Referring to FIG. 4 , the passivation protection layer includes a first passivation protection layer on the second semiconductor layer and a second passivation protection layer on the first passivation protection layer. The thickness of the first passivation protection layer and the second passivation protection layer is not limited. For example, the thickness of the first passivation protection layer may be from 3 nm to 20 nm, and the thickness of the second passivation protection layer may be from 10 nm to 480 nm. FIG. 4 only illustrates the structure of the passivation protection layer, but does not limit the passivation protection layer. For example, compared with the double-layer structure shown in FIG. 4 , the passivation protection layer may include more layers, or only Includes one layer.

The gate structure passes through the passivation protection layer. For example, referring to FIG. 4 , the gate structure is disposed vertically through the passivation protection layer and connected to the second semiconductor layer.

Optionally, referring to FIG. 4 , the device further includes a gate field plate disposed on the gate electrode, and the gate field plate is electrically connected to the gate electrode. The gate field plate helps to make the electric field distribution between the gate and the drain more uniform, and prevents the electric field intensity near the gate from being too high, resulting in a reduction in the withstand breakdown voltage. From a functional perspective only, the electrode passing through the passivation protective layer in Figure 4 is called the gate electrode, and the electrode above the passivation protective layer is called the gate field plate. Optionally, it can be obtained in a primary electrode preparation process. Gate electrode and gate field plate.

FIG. 4 takes the gate structure including a dielectric layer connected to the second semiconductor layer and a gate electrode connected to the dielectric layer as an example but not a limitation. Optionally, referring to Figure 4, the thickness of the passivation protective layer may be greater than the thickness of the dielectric layer. That is to say, a part of the gate electrode is disposed in the passivation protective layer, which is beneficial to shortening the distance between the gate electrode and the first The distance between the semiconductor layers is beneficial to increasing the carrier concentration of the first semiconductor layer in the region under the second gate when a forward bias is applied to the gate electrode.

FIG. 4 only illustrates the structure of the passivation protection layer, but does not limit the passivation protection layer. For example, compared with the double-layer structure shown in FIG. 4 , the passivation protection layer may include more layers, or only Includes one layer.

FIG. 4 only illustrates the structure of the device without limitation, and the device may include more or less structures.

Referring to FIG. 5 , a device is also provided. Compared with the device shown in FIG. 4 , the device may further include an insulating layer disposed on the gate electrode and/or the passivation protection layer. The material of the insulating layer is not limited. For example, the insulating layer may be SiN. The thickness of the insulating layer is not limited, for example, the thickness of the insulating layer may be 10 nm to 500 nm.

Referring to FIG. 5 , the device may further include a source field plate disposed on the source electrode, and the source field plate is electrically connected to the source electrode. The source field plate is conducive to transferring the feedback capacitance between the gate and the drain to the gate and source, overcoming the problem of device gain reduction caused by the introduction of the gate field plate.

FIG. 5 only illustrates the structure of the device without limitation, and the device may include more or less structures.

Electrical measurements of the device are provided below. Assume that in the device shown in Figure 5, the first semiconductor layer is 200nm GaN, the first barrier layer is 1nm AlGaN (the proportion of Al component is 80%), the second barrier layer is 3nm AlN, and the dielectric The SiN layer is 2nm, and the device is electrically simulated and tested. The results are shown in Figure 6. In this structure, the lattice matching degree between the first barrier layer and the first semiconductor layer is better than the lattice matching degree between the second barrier layer and the first semiconductor layer. In other words, the first barrier layer has a lattice matching degree with the first semiconductor layer. The difference between the lattice parameter of the barrier layer and the lattice parameter of the first semiconductor layer is smaller than the difference between the lattice parameter of the second barrier layer and the lattice parameter of the first semiconductor layer. In this way, it is beneficial to increase the thickness of the second semiconductor layer to increase the interface polarization between the second semiconductor layer and the first semiconductor layer on the premise of reducing stress defects caused by lattice mismatch in the second semiconductor layer. Effect, generate more carriers, increase the current density and power density of the device output, and are conducive to the miniaturization of high-power devices.

Referring to Figure 6, curve 1 represents the change of the device's drain current (denoted as ID) with the gate voltage (denoted as VG), and curve 2 represents the change of the device's transconductance (denoted as Gm) with VG. It can be seen from curve 1 that Vth is greater than 0V, the saturation current Idmax is close to 1.2A/mm, and it can be seen from curve 2 that the transconductance Gm is close to 400mS/mm. It can be seen that the device is an enhancement-mode FET with a small series resistance, which is conducive to the preparation of low-loss and high-efficiency FETs.

Below, with reference to Figures 7 to 12, a possible method for preparing the device shown in Figure 4 is provided.

First, as shown in FIG. 7 , a first semiconductor layer, a second semiconductor layer and a passivation protection layer are sequentially formed on a substrate. The first semiconductor layer and the second semiconductor layer may be formed, for example, by using an epitaxial growth technique such as MOCVD. The passivation protective layer may be formed, for example, by using growth techniques such as chemical vapor deposition or atomic layer deposition or sputtering.

The thickness of the first semiconductor layer is not limited, for example, the thickness of the first semiconductor layer is 50 nm to 200 nm. The material of the first semiconductor layer is not limited. For example, the first semiconductor layer may include Group III nitride. For example, the second semiconductor layer may include at least one of aluminum nitride (AlN), indium aluminum nitride (InAlN), aluminum gallium nitride (AlGaN), scandium aluminum nitride (ScAlN), or indium gallium aluminum nitride (InGaAlN).

The thickness of the second semiconductor layer is not limited, for example, the thickness of the second semiconductor layer does not exceed 10 nm. The second semiconductor layer may have a single-layer structure or a multi-layer structure. Referring to FIG. 7 , the second semiconductor layer includes a first barrier layer epitaxially on the first semiconductor layer and a second barrier layer epitaxially on the first barrier layer. The first barrier layer may include AlN or AlGaN with a thickness not exceeding 5 nm, and the second barrier layer may include AlN, InAlN or AlGaN or ScAlN or InGaAlN, and the thickness may not exceed 5 nm.

Optionally, the passivation protection layer may include silicon nitrogen (SiNx). The thickness of the passivation protection layer is not limited, for example, the thickness of the passivation protection layer is 13 nm to 500 nm. The passivation protection layer can be a single-layer structure or a multi-layer structure. Referring to FIG. 7 , the passivation protection layer includes a first passivation protection layer on the second semiconductor layer and a second passivation protection layer on the first passivation protection layer. The thickness of the first passivation protection layer and the second passivation protection layer is not limited. For example, the thickness of the first passivation protection layer may be from 3 nm to 20 nm, and the thickness of the second passivation protection layer may be from 10 nm to 480 nm.

Next, as shown in FIG. 8 , a resist pattern is formed on the surface of the passivation protective layer. The resist pattern can be formed by applying photoresist to the surface of the passivation protective layer and developing it by exposure.

Next, as shown in FIG. 9 , the passivation protective layer not covered by the anti-reagent is etched to remove the anti-reagent pattern. The passivation protection layer can be etched by dry etching (eg, ion etching). The etching source may be one capable of etching the passivation protective layer without etching the second semiconductor layer. A window appears in the etched passivation protection layer, which can expose the second semiconductor layer.

Next, as shown in Figure 10, the device is surface oxidized using an oxidizing agent. The oxidizing agent may, for example, include the element oxygen. Oxygen can be injected into the second semiconductor layer through the window in the passivation protection layer. The oxidized second semiconductor layer is filled with a rectangular area with diagonal lines (ie, the first area mentioned above) as shown in FIG. 10 . The method of oxidizing the second semiconductor layer in the first region is not limited. For example, surface oxidation such as ion implantation or plasma oxidation may be used.

Next, as shown in Figure 11, a gate structure and a gate field plate are formed in the window of the passivation protection layer. Specifically, a dielectric layer is formed on the window of the passivation protection layer and on the surface of the passivation protection layer. The dielectric layer (not specifically shown in FIG. 11 ) formed on the surface of the passivation protection layer can be considered as a part of the passivation protection layer. The material of the dielectric layer is not limited. For example, the dielectric layer may be aluminum oxide (Al2O3), silicon nitride (SiNx), hafnium oxide (HfO2), silicon dioxide (SiO2), or silicon oxynitride (SiON). The thickness of the dielectric layer is not limited, for example, the thickness of the dielectric layer does not exceed 10 nm. After that, the gate electrode and source field plate as shown in Figure 11 can be formed by applying photoresist, exposing, developing, forming a metal film, and removing the photoresist in sequence. The gate electrode and the source field plate may be formed sequentially in one metal film deposition process (eg, vapor deposition). The material of the metal film is not limited. For example, the metal film may be a metal element or an alloy including at least one element among titanium, aluminum, nickel and gold.

Next, as shown in Fig. 12, a source electrode and a drain electrode are formed. Specifically, the source electrode and the drain electrode as shown in Figure 12 can be formed sequentially through processes such as applying photoresist, exposing, developing, etching the passivation protective layer, forming a metal film, and removing the photoresist. The material of the metal film is not limited. For example, the metal film may be a metal element or an alloy including at least one element among titanium, aluminum, nickel and gold. It can also be n-type GaN, n-type InGaN or other highly conductive n-type semiconductor materials, with n-type carrier concentration >1E19/cm3.

The above provides the device and the preparation method of the device, and the following provides a module and equipment.

A module is also provided, which may include any of the devices provided above. The type of module is not limited.

Optionally, the module can be a radio frequency module. The radio frequency module may include at least one of a power amplifier (power amplifier for short), a low noise amplifier, a radio frequency switch, a filter, a circulator, an isolator and an antenna. Any of the devices provided above can be applied to at least one component thereof, such as a power amplifier and/or a low-noise amplifier and/or a radio frequency switch. The radio frequency power module advantageously achieves high reliability and long life. .

Optionally, the module can be a power module. The power module may include one or more transistor components. As an example, the power module may include a high-voltage circuit, a low-voltage circuit, and a transformer disposed between the high-voltage circuit and the low-voltage circuit. The high-voltage circuit and the low-voltage circuit may each include one or more transistor elements. Any of the devices provided above can be applied to at least one transistor element of the power module, which advantageously achieves high reliability and long life.

A device is also provided, which can include any of the modules provided above, which can advantageously achieve high reliability and long life.

Taking the device including the radio frequency module provided above as an example, the device can be, for example, a wireless terminal device (such as a mobile phone or a smart watch) or a customer premise equipment (customer premise equipment, CPE) or a wireless router.

Taking the device including the power module provided above as an example, the device can be any device that needs power supply. For example, The device may be a communication device or a home electronic device or an automotive electronic device or an aerospace device, etc.

In the above, the words "exemplary" or "for example" are used to mean examples, illustrations or explanations. Any example or design described as "exemplary" or "such as" is not intended to be construed as preferred or advantageous over other examples or designs. Rather, use of the words "exemplary" or "such as" is intended to present the concept in a concrete manner.

The term "and/or" appearing in this application can be an association relationship describing associated objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A alone exists, and A and B exist simultaneously. , the case where B exists alone, where A and B can be singular or plural. In addition, the character "/" in this application generally indicates that the related objects are an "or" relationship. In this application, "plurality" means two or more.

The terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the terms so used are interchangeable under appropriate circumstances, and are merely a way of distinguishing objects with the same attributes in describing the embodiments of the present application. Furthermore, the terms "include" and "having" and any variations thereof, are intended to cover non-exclusive inclusions, such that a process, method, system, product or apparatus comprising a series of elements need not be limited to those elements, but may include not explicitly other elements specifically listed or inherent to such processes, methods, products or equipment.

The description of the above examples is only used to help understand the method and the core idea of the present application; at the same time, for those of ordinary skill in the field, there will be changes in the specific examples and application scope based on the ideas of the present application. In summary, As mentioned above, the content of this specification should not be construed as a limitation on this application.

Claims (12)

1. A device, characterized in that it includes:

   a first semiconductor layer provided on the substrate;

   a second semiconductor layer epitaxially on the first semiconductor layer;

   A gate structure disposed on the second semiconductor layer, the second semiconductor layer in a first region is oxidized, and the first region is where the gate structure extends along the vertical direction of the second semiconductor layer. The projected area in the layer.
2. The device according to claim 1, wherein the thickness of the second semiconductor layer in the first region is greater than or equal to the thickness of the second semiconductor layer in the second region, and the second region is the other regions in the second semiconductor layer adjacent to the first region.
3. The device of claim 1 or 2, wherein the second semiconductor layer includes oxygen in the first region.
4. The device according to any one of claims 1 to 3, wherein the gate structure includes a gate electrode and a dielectric layer, and the dielectric layer is disposed between the gate electrode and the second semiconductor layer. between.
5. The device of claim 4, further comprising a passivation protection layer disposed on the second semiconductor layer, and the gate structure passes through the passivation protection layer.
6. The device according to claim 5, wherein the thickness of the passivation protection layer is greater than the thickness of the dielectric layer.
7. The device according to any one of claims 1 to 6, wherein the first semiconductor layer and the second semiconductor layer each comprise a Group III nitride semiconductor.
8. The device of claim 7, wherein the first semiconductor layer includes gallium and nitrogen, and the second semiconductor layer includes aluminum and nitrogen.
9. The device according to claim 8, wherein the second semiconductor layer includes a first barrier layer epitaxially extending on the first semiconductor layer and a second barrier layer epitaxially extending on the first barrier layer. barrier layer.
10. A module, characterized by comprising the device according to any one of claims 1 to 9.
11. The module according to claim 10, characterized in that the module is a power module or a radio frequency module;

    The power module includes one or more transistor elements, at least one of the one or more transistor elements including a device as claimed in any one of claims 1 to 9;

    The radio frequency module includes a power amplifier, a low noise amplifier, a radio frequency switch and a filter, and the power amplifier and/or low noise amplifier and/or radio frequency switch includes the device according to any one of claims 1 to 9.
12. A device, characterized by comprising the module according to claim 10 or 11.