CN108258043A - A kind of enhanced MOS HEMT devices of GaN base and preparation method thereof - Google Patents

A kind of enhanced MOS HEMT devices of GaN base and preparation method thereof Download PDF

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CN108258043A
CN108258043A CN201810025899.0A CN201810025899A CN108258043A CN 108258043 A CN108258043 A CN 108258043A CN 201810025899 A CN201810025899 A CN 201810025899A CN 108258043 A CN108258043 A CN 108258043A
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layer
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grid
gate dielectric
barrier
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梁世博
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Beijing China Carbon Science And Technology Co Ltd
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Beijing China Carbon Science And Technology Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

Present invention relates particularly to enhanced MOS HEMT devices of a kind of GaN base and preparation method thereof.The device includes substrate and epitaxial layer, epitaxial layer includes buffer layer, GaN channel layers, AlGaN potential barrier, AlN barrier layers successively from bottom to up, Ohm contact electrode is deposited in source drain region, gate medium is AlON dielectric layers and high-k dielectric layer lamination from bottom to up, wherein AlON dielectric layers are aoxidized for the AlN barrier layers of grid lower zone, gate metal is deposited in area of grid, is passivated between source-drain electrode and grid by the lamination of passivation layer and high-k gate dielectric layer.The present invention can it is self aligned oxidation area of grid have highly polar AlN single crystalline layers, realize the controllable growth of AlON media, the problems such as exhausting the two-dimensional electron gas below area of grid, obtain the enhanced MOS HEMT devices of GaN base, effectively preventing ion dam age caused by etching barrier layer.

Description

A kind of enhanced MOS HEMT devices of GaN base and preparation method thereof
Technical field
The present invention relates to field of semiconductor integration technology more particularly to a kind of enhanced MOS high electron mobilities of GaN base are brilliant Body tube device and preparation method thereof.
Background technology
The research of GaN material and device and forward position and hot spot that application is current global semiconductor research.GaN material with SiC and diamond are known as third generation semi-conducting material together.GaN material has that energy gap is wide, critical breakdown electric field The advantages that height, electron saturation velocities are high, thermal conductivity is high, heterojunction boundary two-dimensional electron gas is high, is next-generation power device Ideal substitute.
The operating mode of traditional GaN device is mostly depletion device, and in switching mode circuit, there are power consumption height and designs The problem of complicated.In order to meet the commercial demand of GaN power electronic devices, the safety of circuit work is improved, GaN base is enhanced MOS HEMT devices have become a current important research direction.
In order to realize enhanced work, enhanced MOS HEMT (high electron mobility transistor) device of GaN base leads at present Frequently with concave grid groove technology, barrier layer thickness is thinned by lithographic technique, concave grid groove technology is higher to etching apparatus requirement, and And lattice damage can be caused, process repeatability is poor, influences the stability and reliability of device.Ultra-thin potential barrier increases without etching GaN base Strong type MOS HEMT devices have important researching value and wide application prospect.
Invention content
Present invention aims at high-k gate dielectric layer is used as diffusion barrier layer and protective layer, by GaN base MOS HEMT devices The AlN barrier layers of part area of grid are oxidized into AlON, reduce the polarity of barrier layer below device grids so that the GaN ditches The two-dimensional electron gas of channel layer area of grid exhausts, and realizes the enhanced MOS HEMT devices of GaN base of no etching, and the present invention will be open A kind of enhanced MOS HEMT devices of GaN base and preparation method thereof.
In order to achieve the above objectives, the present invention provides a kind of enhanced MOS HEMT devices of GaN base, and the GaN base is enhanced MOS HEMT devices by substrate, buffer layer, GaN channel layers, AlGaN potential barrier, AlN barrier layers, AlON dielectric layers, passivation layer, High-k gate dielectric layer, barrier metal layer and Source and drain metal level composition.
The buffer layer is stacked in the substrate;The GaN channel layers are stacked on the buffer layer:It is described AlGaN potential barrier is stacked on the GaN channel layers;The AlN barrier layers are stacked in two on the AlGaN potential barrier Side;The AlON dielectric layers are stacked on the AlGaN potential barrier close to the position of side, and its both sides and the AlN gesture Barrier layer connects;The Source and drain metal level is stacked on the AlN barrier layers and in the enhanced MOS HEMT device of the GaN base The both sides of part;The passivation layer is on the close grid side of the AlN barrier layers and the Source and drain metal level, and is covered The Source and drain metal level is close to the side wall of grid side;The high-k gate dielectric layer is stacked in the passivation layer and the AlON is situated between On matter layer;The barrier metal layer is stacked on the area of grid part of the high-k gate dielectric layer.
The substrate is silicon, one kind in sapphire, single-crystal silicon carbide substrate.
The buffer layer can be formed for one kind in AlN, AlGaN, GaN or its stack combinations, the thickness of the buffer layer Degree is between 1 micron -3 microns.
The thickness of the GaN channel layers is between 1 nanometer -1 micron.
The thickness of the AlGaN potential barrier is between 3 angstroms -6 nanometers.
The thickness of the AlN barrier layers is between 3 angstroms -4 nanometers.
The width and the distance between the passivation layer of the AlON dielectric layers are essentially identical.
The passivation layer can be silicon nitride, silica or aluminium base, zirconium base, hafnium base, gadolinium base, gallium base, lanthanum base, the oxidation of tantalum base Object, the thickness of the passivation layer is between 1 nanometer -100 nanometers;
The high-k gate dielectric layer can be high-k oxide, including aluminium base, zirconium base, hafnium base, gadolinium base, gallium base, Lanthanum base, tantalum base, yttrium-based oxide, the doped chemical in the oxide of the high-k gate dielectric layer can be aluminium, zirconium, hafnium, gadolinium, gallium, One or more in lanthanum, tantalum, nitrogen, phosphorus, yttrium, the thickness of the high-k gate dielectric layer is between 3 angstroms -6 nanometers.
The barrier metal layer can be one or more layers metal group of tantalum nitride, titanium nitride, titanium, nickel, platinum, gold, tungsten or aluminium It closes, the thickness of the barrier metal layer is between 1 nanometer -1 micron.
The Source and drain metal level can be nickel, germanium, gold, palladium, titanium, copper, platinum, tungsten, aluminium one or more layers metallic combination and Into the thickness of the Source and drain metal level is between 1 nanometer -1 micron.
In addition, the present invention also provides a kind of preparation method of the aforementioned enhanced MOS HEMT devices of GaN base, the method packet Include following steps:
Step 1:Over the substrate successively buffer layer described in extension, the GaN channel layers, the AlGaN potential barrier, AlN single crystalline layers;
Step 2:Both sides on the AlN single crystalline layers form the source and drain gold by way of photoetching, evaporation, stripping Belong to layer;
Step 3:The material layer of the passivation layer is deposited, is gone by the way of photoetching, stripping, dry etching or wet etching Except the material layer of the passivation layer of area of grid;
Step 4:The material layer of the high-k gate dielectric is deposited, the high k is penetrated using containing ozone gas or oxygen plasma The material layer of gate dielectric layer aoxidizes the AlN single crystalline layers of area of grid, generates the AlON dielectric layers;
Step 5:The barrier metal layer is formed in the material layer of the high-k gate dielectric;
Step 6:Remove material layer and the part high-k gate dielectric of the part passivation layer in the Source and drain metal level The material layer of layer, forms the passivation layer and the high-k gate dielectric layer.
It is using MBE (molecular beam epitaxy) or MOCVD (Metal Organic Chemical Vapor Deposition) in the step 1 Mode extension described in buffer layer, the GaN channel layers, the AlGaN potential barrier, AlN single crystalline layers.
In the step 2, the epitaxial substrate first obtained with organic chemical reagent cleaning step 1 is needed, in source and drain metal With diluted hydrochloric acid or the natural oxide of phosphoric acid removal sample surfaces before evaporation.
In the step 3, the deposition method of the material layer of the passivation layer includes atomic layer deposition, plasma-reinforced chemical One or more deposition methods in vapor deposition, magnetron sputtering, molecular beam epitaxy or metal organic chemical vapor deposition.
In the step 4, the deposition method of the material layer of the high-k gate dielectric layer includes atomic layer deposition, plasma increases One or more deposition sides in extensive chemical vapor deposition, magnetron sputtering, molecular beam epitaxy or metal organic chemical vapor deposition Method;The ozone gas that contains is one or more mixed gases in ozone or ozone and nitrogen, helium, argon gas, described Containing ozone gas the AlN single crystalline layers of area of grid, the time of the oxidation are aoxidized through the material layer of the high-k gate dielectric layer It can be 1 millisecond between -5 hours;The oxygen plasma is by one or more mixed in oxygen, ozone, helium, argon gas Gas after conjunction, by the plasma that plasma generator ionization is formed, the op plasma generator power exists Between 0-200 watts every square centimeter, the oxygen plasma aoxidizes area of grid through the material layer of the high-k gate dielectric layer AlN single crystalline layers, the oxidization time of the oxygen plasma can be 1 millisecond between -5 hours;The AlN of the area of grid is mono- Crystal layer is oxidized into after the AlON dielectric layers, can be reduced the polarity at interface above the GaN channel layers area of grid, be made The two-dimensional electron gas for obtaining the GaN channel layers area of grid exhausts, and can be used for preparing enhanced MOS HEMT devices.
In the step 5, the barrier metal layer is formed by the way of photoetching, evaporation, etching or stripping.
In the step 6, the part removed by the way of photoetching, etching or corrosion in the Source and drain metal level is described blunt Change the material layer of material layer and the part high-k gate dielectric layer of layer, form the passivation layer and the high-k gate dielectric layer
Advantages of the present invention and technique effect are as follows:
The enhanced MOS HEMT devices of GaN base are compared to traditional enhanced MOS HEMT devices tool of concave grid groove GaN base There is following advantage:1. in preparation method, do not need to grid slot barrier layer carry out dry etching, avoid etching lattice damage and The problems such as process repeatability is poor;2. using barrier layer of the high-k gate dielectric as oxidation source, it is possible to prevente effectively from oxygen plasma and AlN layers are in direct contact, and reduce the ion dam age in oxidation process;It 3., can using barrier layer of the high-k gate dielectric as oxidation source Technological parameter during with by the thickness and the oxidation that control high-k gate dielectric, the accurate growth for controlling AlON;4. it is generated AlON dielectric layers can be as the gate medium of the enhanced MOS HEMT of GaN base, without removal.
Description of the drawings
Fig. 1 is the structure diagram of the enhanced MOS HEMT devices of GaN base provided by the present invention;
Fig. 2 is on substrate after buffer layer, the GaN channel layers, the AlGaN potential barrier, AlN single crystalline layers described in extension Structure diagram;
Fig. 3 is the structure diagram to be formed after the Source and drain metal level;
Fig. 4 is the material layer and the structure diagram after area of grid trepanning for depositing the passivation layer;
Fig. 5 is the structure diagram after the material layer for depositing the high-k gate dielectric layer;
Fig. 6 is the structure diagram to be formed after the AlON dielectric layers;
Fig. 7 is the structure diagram to be formed after the barrier metal layer;
Wherein:
1 be substrate, 2 be buffer layer, 3 be GaN channel layers, 4 be AlGaN potential barrier, 5 be AlN barrier layers, 6 be source and drain gold Belong to layer, 7 be passivation layer, 8 be high-k gate dielectric layer, 9 be AlON dielectric layers, 10 be barrier metal layer, 11 be two-dimensional electron gas one, 5a For the material layer that AlN single crystalline layers, 11a are two-dimensional electron gas two, 7a is the material layer of passivation layer, 8a is high-k gate dielectric layer.
Specific embodiment
To make the purpose of the present invention, content and advantage clearer, with reference to the accompanying drawings and examples, to the present invention's Specific embodiment is described in further detail.The following examples are only intended to illustrate the technical solution of the present invention more clearly, And it is not intended to limit the protection scope of the present invention and limits the scope of the invention.
The present embodiment specifically describes a kind of enhanced MOS HEMT devices of GaN base provided by the present invention and its preparation side Method.
As shown in Figure 1, the enhanced MOS HEMT devices of GaN base that the present embodiment is provided, by substrate 1, buffer layer 2, GaN Channel layer 3, AlGaN potential barrier 4, AlN barrier layers 5, AlON dielectric layers 9, passivation layer 7, high-k gate dielectric layer 8, barrier metal layer 10, It is formed with Source and drain metal level 6.
The buffer layer 2 is stacked on the substrate 1;The GaN channel layers 3 are stacked on the buffer layer 2:Institute AlGaN potential barrier 4 is stated to be stacked on the GaN channel layers 3;The AlN barrier layers 5 be stacked in the AlGaN potential barrier 4 it On both sides;The AlON dielectric layers 9 are stacked on the AlGaN potential barrier 4 that (unsymmetric structure can close to the position of side To increase drain breakdown voltage), and its both sides connects with the AlN barrier layers 5;The Source and drain metal level 6 is stacked in the AlN On the barrier layer 5 and both sides in the enhanced MOS HEMT devices of the GaN base;The passivation layer 7 is in the AlN potential barriers On the close grid side of layer 5 and the Source and drain metal level 6, and the Source and drain metal level 6 is covered close to the side of grid side Wall;The high-k gate dielectric layer 8 is stacked on the passivation layer 7 and the AlON dielectric layers 9;The barrier metal layer 10 is stacked On the area of grid part of the high-k gate dielectric layer 8;4 He of the AlGaN potential barrier below the AlN barrier layers 5 3 interface of GaN channel layers forms two-dimensional electron gas 1.
The substrate 1 is silicon.
The buffer layer 2 is AlN/AlGaN/GaN laminated construction, and the thickness of the buffer layer 2 is 1.5 microns.
The thickness of the GaN channel layers 3 is 50 nanometers.
The thickness of the AlGaN potential barrier 4 is 5 nanometers.
The thickness of the AlN barrier layers 5 is 2 nanometers.
The distance between the width of the AlON dielectric layers 9 and the passivation layer 7 are essentially identical.
The passivation layer 7 is silicon nitride, and the thickness of the passivation layer 7 is 30 nanometers, and the distance between described passivation layer 7 is 200 nanometers.
The high-k gate dielectric layer 8 is alundum (Al2O3), and the thickness of the high-k gate dielectric layer 8 is 2 nanometers.
The barrier metal layer 10 is Ni/Au laminations, and the thickness of the barrier metal layer 10 is 200 nanometers.
The Source and drain metal level 6 is Ti/Al/Ni/Au, and the thickness of the Source and drain metal level 6 is 200 nanometers.
In addition, the present embodiment also provides a kind of preparation method of the enhanced MOS HEMT devices of aforementioned GaN base, the method Include the following steps:
Step 1:As shown in Fig. 2, the buffer layer 2 described in extension, the GaN channel layers 3, described successively on the substrate 1 AlGaN potential barrier 4, AlN single crystalline layers 5a;
Step 2:As shown in figure 3, the shape by way of photoetching, evaporation, stripping of the both sides on the AlN single crystalline layers 5a Into the Source and drain metal level 6;
Step 3:As shown in figure 4, deposit the dielectric layer material of the passivation layer, using photoetching, stripping, dry etching side The dielectric layer material of the passivation layer of formula removal area of grid forms the material layer 7a of the passivation layer;
Step 4:As shown in Figure 5 and Figure 6, the material layer 8a of the high-k gate dielectric is deposited, institute is penetrated using oxygen plasma The material layer 8a of high-k gate dielectric layer is stated to aoxidize the AlN single crystalline layer 5a of area of grid, generates the AlON dielectric layers 9;
Step 5:As shown in fig. 7, the barrier metal layer 10 is formed on the material layer 8a of the high-k gate dielectric;
Step 6:As shown in Fig. 7 and Fig. 1, the material layer 7a of the part passivation layer in the Source and drain metal level 6 is removed With the material layer 8a of the part high-k gate dielectric layer, the passivation layer 7 and the high-k gate dielectric layer 8 are formed.
It is buffer layer 2, the GaN channel layers 3, the AlGaN described in extension by the way of MOCVD in the step 1 Barrier layer 4, AlN single crystalline layer 5a form two-dimensional electron gas two at the interface of the GaN channel layers 3 and the AlGaN potential barrier 4 11a。
In the step 2, need first to serve as a contrast come the extension that cleaning step 1 is obtained using acetone, ethyl alcohol, deionized water successively Bottom, and dried up with high pure nitrogen, with the natural oxide of diluted hydrochloric acid removal sample surfaces before source and drain evaporation of metal.
In the step 3, the deposition method of the material layer 7a of the passivation layer is plasma reinforced chemical vapour deposition, institute The material layer 7a for stating passivation layer is silicon nitride, and thickness is 30 nanometers.
In the step 4, the deposition method of the material layer 8a of the high-k gate dielectric layer is atomic layer deposition;Described oxygen etc. Gas ions are to pass through the plasma that is formed of plasma generator ionization, the op plasma generator power by oxygen Every square centimeter for 100 watts, the oxygen plasma aoxidizes area of grid through the material layer 8a of the high-k gate dielectric layer AlN single crystalline layers 5a, the oxidization time of the oxygen plasma is 20 minutes;The AlN single crystalline layers 5a of the area of grid is oxidized to After the AlON dielectric layers 9, the polarity at interface above 3 area of grid of GaN channel layers can be reduced so that described The two-dimensional electron gas of 3 area of grid of GaN channel layers exhausts, and can be used for preparing enhanced MOS HEMT devices.
In the step 5, the barrier metal layer 10 is formed by the way of photoetching, evaporation, etching or stripping.
In the step 6, the part passivation layer in the Source and drain metal level 6 is removed by the way of photoetching, etching Material layer 7a and the part high-k gate dielectric layer material layer 8a, form the passivation layer 7 and the high-k gate dielectric layer 8
The above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art For member, without departing from the technical principles of the invention, several improvement and deformation can also be made, these are improved and deformation Also it should be regarded as protection scope of the present invention.

Claims (10)

1. a kind of enhanced MOS HEMT devices of GaN base, which is characterized in that including substrate, buffer layer, GaN channel layers, AlGaN Barrier layer, AlN barrier layers, AlON dielectric layers, passivation layer, high-k gate dielectric layer, barrier metal layer and Source and drain metal level;The buffering Layer is stacked in the substrate;The GaN channel layers are stacked on the buffer layer:The AlGaN potential barrier is stacked in On the GaN channel layers;The AlN barrier layers are stacked in the both sides on the AlGaN potential barrier;The AlON dielectric layers It is stacked in close to the position of side on the AlGaN potential barrier, and its both sides connects with the AlN barrier layers;The source and drain Metal layer is stacked on the AlN barrier layers and the both sides in the enhanced MOS HEMT devices of the GaN base;The passivation Layer covers the Source and drain metal level and leans on the close grid side of the AlN barrier layers and the Source and drain metal level The side wall of nearly grid side;The high-k gate dielectric layer is stacked on the passivation layer and the AlON dielectric layers;The grid gold Belong to layer to be stacked on the area of grid part of the high-k gate dielectric layer.
A kind of 2. enhanced MOS HEMT devices of GaN base as described in claim 1, which is characterized in that the AlGaN potential barrier Thickness between 3 angstroms -6 nanometers.
3. a kind of enhanced MOS HEMT devices of GaN base as described in claim 1, which is characterized in that the AlN barrier layers Thickness is between 3 angstroms -4 nanometers.
A kind of 4. enhanced MOS HEMT devices of GaN base as described in claim 1, which is characterized in that the AlON dielectric layers Width and the distance between the passivation layer it is essentially identical.
5. the preparation method of the enhanced MOS HEMT devices of GaN base described in a kind of claim 1, which is characterized in that including as follows Step:
Step 1:Buffer layer, the GaN channel layers, the AlGaN potential barrier, AlN are mono- described in extension successively over the substrate Crystal layer;
Step 2:Both sides on the AlN single crystalline layers form the source and drain metal by way of photoetching, evaporation, stripping Layer;
Step 3:The material layer of the passivation layer is deposited, grid are removed by the way of photoetching, stripping, dry etching or wet etching The material layer of the passivation layer in polar region domain;
Step 4:The material layer of the high-k gate dielectric is deposited, is situated between using containing ozone gas or oxygen plasma through the high k grid The material layer of matter layer aoxidizes the AlN single crystalline layers of area of grid, generates the AlON dielectric layers;
Step 5:The barrier metal layer is formed in the material layer of the high-k gate dielectric;
Step 6:Remove material layer and the part high-k gate dielectric layer of the part passivation layer in the Source and drain metal level Material layer forms the passivation layer and the high-k gate dielectric layer.
6. the preparation method of the enhanced MOS HEMT devices of GaN base as claimed in claim 5, which is characterized in that the step 4 In, the deposition method of the material layer of the high-k gate dielectric layer includes atomic layer deposition, plasma reinforced chemical vapour deposition, magnetic One or more deposition methods in control sputtering, molecular beam epitaxy or metal organic chemical vapor deposition, the high-k gate dielectric layer For the oxide of high-k, including aluminium base, zirconium base, hafnium base, gadolinium base, gallium base, lanthanum base, tantalum base, yttrium-based oxide, the height Doped chemical in the oxide of k gate dielectric layers is aluminium, one or more, the institute in zirconium, hafnium, gadolinium, gallium, lanthanum, tantalum, nitrogen, phosphorus, yttrium The thickness of high-k gate dielectric layer is stated between 3 angstroms -6 nanometers.
7. the preparation method of the enhanced MOS HEMT devices of GaN base as claimed in claim 5, which is characterized in that the step 4 In, the ozone gas that contains is one or more mixed gases in ozone or ozone and nitrogen, helium, argon gas, described Containing ozone gas the AlN single crystalline layers of area of grid, the time of the oxidation are aoxidized through the material layer of the high-k gate dielectric layer For 1 millisecond between -5 hours.
8. the preparation method of the enhanced MOS HEMT devices of GaN base as claimed in claim 5, which is characterized in that the step 4 In, the oxygen plasma be by one or more mixed gases in oxygen, ozone, helium, argon gas, by etc. from The plasma that the ionization of daughter generator is formed, the oxygen plasma are aoxidized through the material layer of the high-k gate dielectric layer The AlN single crystalline layers of area of grid.
9. the preparation method of the enhanced MOS HEMT devices of GaN base as claimed in claim 8, which is characterized in that the grade from For the operating power of daughter generator between 0-200 watts every square centimeter, the oxidization time of the oxygen plasma is 1 millisecond -5 Between hour.
10. the preparation method of the enhanced MOS HEMT devices of GaN base as claimed in claim 5, which is characterized in that the step In 4, the AlN single crystalline layers of the area of grid are oxidized into after the AlON dielectric layers, reduce the GaN channel layers gate regions The polarity at interface above domain so that the two-dimensional electron gas of the GaN channel layers area of grid exhausts, and is used to prepare enhanced MOS HEMT device.
CN201810025899.0A 2018-01-11 2018-01-11 A kind of enhanced MOS HEMT devices of GaN base and preparation method thereof Pending CN108258043A (en)

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