CN110867441A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN110867441A
CN110867441A CN201810986580.4A CN201810986580A CN110867441A CN 110867441 A CN110867441 A CN 110867441A CN 201810986580 A CN201810986580 A CN 201810986580A CN 110867441 A CN110867441 A CN 110867441A
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China
Prior art keywords
layer
semiconductor
semiconductor layer
hemt
mosfet
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CN201810986580.4A
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Chinese (zh)
Inventor
刘埃森
蔡滨祥
林进富
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN201810986580.4A priority Critical patent/CN110867441A/en
Publication of CN110867441A publication Critical patent/CN110867441A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type

Abstract

The invention discloses a semiconductor element and a manufacturing method thereof. The semiconductor element comprises a semiconductor substrate on an insulator, a high electron mobility transistor element and a metal oxide semiconductor field effect transistor element. A semiconductor substrate on an insulator, comprising: the semiconductor device includes a first semiconductor layer, a second semiconductor layer, and an insulating layer. The second semiconductor layer is located on the first semiconductor layer. The insulating layer is located between the first semiconductor layer and the second semiconductor layer. The high electron mobility transistor element is located on the first semiconductor layer. The metal oxide semiconductor field effect transistor element is positioned on the second semiconductor layer and electrically connected with the high electron mobility transistor element. The top surface of the high electron mobility transistor element is coplanar with the top surface of the second semiconductor layer.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present invention relates to integrated circuits and methods of fabricating the same, and more particularly, to semiconductor devices and methods of fabricating the same.
Background
With the advance of technology, various electronic products are developed towards the trend of high speed, high efficiency, light weight, small size and so on. Therefore, how to increase the number and functions of semiconductor devices in a limited chip area is a goal of the development of the semiconductor industry.
Disclosure of Invention
The invention provides a semiconductor element, which integrates a normally-on (normal on) High Electron Mobility Transistor (HEMT) element and a normally-off (normal off) metal-oxide-semiconductor field effect transistor (MOSFET) element on the same chip to achieve low threshold voltage (threshold voltage), fast switching speed and maintain high voltage capability (voltage capability).
The present invention provides a semiconductor device, which integrates a HEMT device and a MOSFET device through an interconnect structure to achieve the requirement of miniaturization.
The invention provides a semiconductor element, which comprises a semiconductor-on-insulator (SOI) substrate, a HEMT element and a MOSFET element. An SOI substrate comprising: the semiconductor device includes a first semiconductor layer, a second semiconductor layer, and an insulating layer. The second semiconductor layer is located on the first semiconductor layer. The insulating layer is located between the first semiconductor layer and the second semiconductor layer. The HEMT element is located on the first semiconductor layer. The MOSFET element is located on the second semiconductor layer and electrically connected with the HEMT element. The top surface of the HEMT element is coplanar with the top surface of the second semiconductor layer.
In an embodiment of the invention, the semiconductor device further includes an interconnect structure on the HEMT device and the MOSFET device, wherein the HEMT device and the MOSFET device are electrically connected through the interconnect structure.
In an embodiment of the invention, the gate of the HEMT device is electrically connected to the source of the MOSFET device, and the source of the HEMT device is electrically connected to the drain of the MOSFET device.
In an embodiment of the invention, the sidewall of the HEMT device is a tapered sidewall.
In an embodiment of the invention, the semiconductor device further includes a dielectric layer located on the HEMT device and the MOSFET device and filling a gap between the HEMT device and the second semiconductor layer to electrically isolate the HEMT device and the MOSFET device.
In an embodiment of the invention, the top surface of the first semiconductor layer is a (111) crystal plane, and the top surface of the second semiconductor layer is a (100) crystal plane.
In an embodiment of the invention, a thickness of the second semiconductor layer is smaller than a thickness of the first semiconductor layer.
In an embodiment of the invention, the HEMT device includes: buffer layer, channel layer, barrier layer and two-dimensional electron gas layer. The buffer layer is located on the first semiconductor layer. The channel layer is located on the buffer layer. The barrier layer is located on the channel layer. The two-dimensional electron gas layer is located in the channel layer adjacent to the barrier layer.
In an embodiment of the invention, the HEMT device is a normally-on device, and the MOSFET device is a normally-off device.
The invention provides a method for manufacturing a semiconductor element, which comprises the following steps. Providing an SOI substrate, wherein the SOI substrate sequentially comprises a first semiconductor layer, an insulating layer and a second semiconductor layer. An opening is formed exposing the first semiconductor layer. A HEMT element is formed on the first semiconductor layer in the opening. And forming a MOSFET element on the second semiconductor layer, wherein the top surface of the HEMT element is coplanar with the top surface of the second semiconductor layer.
In an embodiment of the invention, the method further includes forming an interconnect structure on the HEMT device and the MOS device, wherein the HEMT device and the MOSFET device are electrically connected through the interconnect structure.
In an embodiment of the invention, the forming the interconnect structure includes the following steps. A dielectric layer is formed on the HEMT element and the MOSFET element to fill the gap between the HEMT element and the second semiconductor layer. A plurality of conductive plugs are formed in the dielectric layer to electrically connect the HEMT device and the MOSFET device, respectively. And forming a plurality of conductive layers to be respectively electrically connected with the conductive plugs.
In an embodiment of the invention, the gate of the HEMT device is electrically connected to the source of the MOSFET device, and the source of the HEMT device is electrically connected to the drain of the MOSFET device.
In an embodiment of the present invention, after forming the interconnect structure, the method further includes the following steps. And forming conductive terminals on the interconnection structure. And carrying out a monomer manufacturing process.
In an embodiment of the invention, the sidewall of the HEMT device is a tapered sidewall, and the HEMT device is electrically isolated from the MOSFET device.
In an embodiment of the invention, the providing the SOI substrate includes the following steps. An insulating layer is formed over the second semiconductor material. The second semiconductor material is flip-bonded (flip-bonding) onto the first semiconductor layer such that the insulating layer is between the first semiconductor layer and the second semiconductor material.
In an embodiment of the invention, after the second semiconductor material is bonded to the first semiconductor layer in an inverted manner, the method further includes thinning the second semiconductor material to form the second semiconductor layer, wherein a thickness of the second semiconductor layer is smaller than a thickness of the first semiconductor layer.
In an embodiment of the invention, a sum of the thicknesses of the second semiconductor layer and the insulating layer is substantially equal to a thickness of the HEMT device.
In an embodiment of the invention, the top surface of the first semiconductor layer is a (111) crystal plane, and the top surface of the second semiconductor layer is a (100) crystal plane.
In an embodiment of the invention, the forming of the HEMT device includes the following steps. A buffer layer is epitaxially grown on the first semiconductor layer. And epitaxially growing a channel layer on the buffer layer. A barrier layer is epitaxially grown on the channel layer, wherein a two-dimensional electron gas layer is formed in the channel layer adjacent to the barrier layer.
Based on the above, the present invention integrates the HEMT device and the MOSFET device on the same chip through the interconnect structure to achieve low threshold voltage, fast switching speed and maintain high voltage capability. Compared with the method of externally connecting the component in the packaging stage, the manufacturing method of the semiconductor element has lower manufacturing cost, can meet the requirement of miniaturization, and further improves the reliability of the product.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A to fig. 1O are schematic cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the invention;
fig. 2 is a schematic top view of fig. 1O.
Detailed Description
The present invention will be described more fully with reference to the accompanying drawings of the present embodiments. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The thickness of layers and regions in the drawings may be exaggerated for clarity. The same or similar reference numerals denote the same or similar elements, and the following paragraphs will not be repeated.
Fig. 1A to fig. 1O are schematic cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the invention.
Referring to fig. 1A to fig. 1O, an embodiment of the invention provides a method for manufacturing a semiconductor device 10 (shown in fig. 1O), which includes the following steps. First, an SOI substrate 100 is provided (as shown in fig. 1D). Specifically, as shown in fig. 1A, a first semiconductor layer 101 is provided. In one embodiment, the first semiconductor layer 101 may be a silicon substrate having a top surface 101t of a < 111 > crystal plane. In an alternative embodiment, the first semiconductor layer 101 may be a < 111 > single crystal silicon layer. Next, as shown in fig. 1B, an insulating layer 103 is formed on the second semiconductor material 102'. In an embodiment, the second semiconductor material 102' may be bulk silicon. The insulating layer 103 may be an insulating material including silicon oxide, silicon nitride, silicon oxynitride, a suitable insulating material, or a combination thereof. For example, the insulating layer 103 may be silicon oxide (which may be referred to as a Buried Oxide (BOX) layer) and may be formed by a thermal oxidation method, a Chemical Vapor Deposition (CVD) method, or a suitable formation method.
Then, as shown in fig. 1C, the combined structure of the second semiconductor material 102 'and the insulating layer 10 is bonded upside down onto the first semiconductor layer 101 so that the insulating layer 103 is located between the first semiconductor layer 101 and the second semiconductor material 102'. In an embodiment, the bonding may be, for example, a thermal compression bonding method to bond the first semiconductor layer 101 and the insulating layer 103 together.
Thereafter, as shown in fig. 1C and fig. 1D, a thinning process is performed to remove a portion of the second semiconductor material 102', so as to form a thinned second semiconductor material 102 (hereinafter referred to as a second semiconductor layer 102). In some embodiments, the thinning process includes a Chemical Mechanical Polishing (CMP) process, a polishing process, or other suitable thinning process. After the thinning process, an SOI substrate 100 including a first semiconductor layer 101, a second semiconductor layer 102, and an insulating layer 103 disposed between the first semiconductor layer 101 and the second semiconductor layer 102 is formed, as shown in fig. 1D. In an embodiment, the thickness T2 of the second semiconductor layer 102 is less than the thickness T1 of the first semiconductor layer 101. The top surface 102t of the second semiconductor layer 102 exposed after thinning is a < 100 > crystal plane. In an alternative embodiment, the second semiconductor layer 102 may be a < 100 > single crystal silicon layer. It is noted that the thickness T2 of the second semiconductor layer 102 can be controlled to correspond to the thickness T3 (shown in fig. 1I) of the HEMT device 200 to be formed subsequently. In alternative embodiments, the crystal plane of the top surface 101t of the first semiconductor layer 101 and the crystal plane of the top surface 102t of the second semiconductor layer 102 may be the same or different.
Referring to fig. 1E, a hard mask layer 104 and a photoresist pattern 106 are sequentially formed on the SOI substrate 100. In one embodiment, the hard mask layer 104 may be, for example, silicon nitride, silicon oxynitride, a suitable material, or a combination thereof, which may be formed by CVD.
Referring to fig. 1E and 1F, a portion of the hard mask layer 104 is removed by using the photoresist pattern 106 as a mask. Then, using the patterned hard mask layer 104a as a mask, a portion of the second semiconductor layer 102 and a portion of the insulating layer 103 are removed to form an opening 105. As shown in fig. 1F, the opening 105 exposes the top surface 101t of the first semiconductor layer 101.
Referring to fig. 1G and fig. 1H, after the photoresist pattern 106 is removed, the HEMT device 200 is formed on the top surface 101t of the first semiconductor layer 101 in the opening 105. Specifically, the HEMT device 200 includes a substrate 201, a buffer layer 202, a channel layer 204, a barrier layer 206, and a dielectric layer 208. The substrate 201 has a front surface S1 and a back surface S2 opposite to each other. The back surface S2 of the substrate 201 is in direct contact with the top surface 101t of the first semiconductor layer 101 (or the bottom surface 105b of the opening 105). In one embodiment, the substrate 201 may be considered a growth substrate epitaxially grown from the top surface 101t of the first semiconductor layer 101. In this case, the crystal plane < 111 > of the top surface 101t of the first semiconductor layer 101 is a crystal plane suitable for epitaxial growth of the substrate 201. In alternative embodiments, the material of the substrate 201 may be, for example, Sapphire (Sapphire), silicon carbide (SiC), aluminum nitride (AlN), silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), or a combination thereof.
As shown in fig. 1H, the buffer layer 202, the channel layer 204, the barrier layer 206 and the dielectric layer 208 are sequentially formed on the front surface S1 of the substrate 201. The buffer layer 202, the channel layer 204, the barrier layer 206, and the dielectric layer 208 may be formed by Metal-organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), Hydride Vapor Phase Epitaxy (HVPE), or a combination thereof.
In detail, the buffer layer 202 may be disposed between the substrate 201 and the channel layer 204 to reduce a lattice constant difference and a thermal expansion coefficient difference between the substrate 201 and the channel layer 204. In one embodiment, the material of the buffer layer 202 includes a group III nitride, such as a group III-V compound semiconductor material, and may have a single layer or a multi-layer structure. In alternative embodiments, the material of the buffer layer 202 includes AlN, GaN, AlGaN, InGaN, AlInN, AlGaInN, or combinations thereof.
The channel layer 204 may be disposed between the buffer layer 202 and the barrier layer 206. Due to the heterojunction formed between the channel layer 204 and the barrier layer 206, a two-dimensional electron gas (2DEG) layer 205 with high electron mobility is formed in the region of the channel layer 204 near the barrier layer 206. In one embodiment, the material of the channel layer 204 includes a group III nitride, such as a group III-V compound semiconductor material, which may be, for example, undoped (undoped) or unintentionally doped (undoped) GaN. However, the invention is not limited thereto, and in other embodiments, the material of the channel layer 204 is within the scope of the invention as long as the energy gap of the material of the channel layer 204 is different from the energy gap of the material of the barrier layer 206. In an alternative embodiment, a thicker GaN layer may be formed by HVPE first, and then a thinner GaN layer of better quality may be formed by MOCVD or MBE.
The barrier layer 206 may be disposed between the channel layer 204 (or two-dimensional electron gas layer 205) and the dielectric layer 208. In one embodiment, the material of the barrier layer 206 includes a group III nitride, such as a group III-V compound semiconductor material, and may have a single layer or a multi-layer structure. In one embodiment, the barrier layer 206 includes AlGaN, AlInN, AlN, AlGaInN, or a combination thereof. In one embodiment, the barrier layer 206 may be a doped or undoped layer. In addition, a doped GaN layer may also be formed between the barrier layer 206 and the dielectric layer 208 to form ohmic contacts (ohmic contacts) with the source electrode 214 and the drain electrode 216 (as shown in fig. 1K) to be formed subsequently.
A dielectric layer 208 may be disposed on the barrier layer 206. In one embodiment, the material of the dielectric layer 208 includes a dielectric material, and may have a single-layer or multi-layer structure. In one embodiment, the material of the dielectric layer 208 includes aluminum oxide (Al)2O3) Silicon nitride, silicon oxide, aluminum nitride (AlN), or a combination thereof.
Note that, since the formation crystal plane of the HEMT device 200 is < 111 >, the sidewall S3 of the HEMT device 200 formed by epitaxial growth is a tapered sidewall (tapered sidewalls). That is, as shown in fig. 1H, the sidewall S3 of the HEMT device 200 does not contact the second semiconductor layer 102a (or the side 105S of the opening 105) for electrical isolation. In the cross-sectional view of fig. 1H, the HEMT device 200 can be a trapezoid structure with a bottom width (or area) larger than a top width (or area).
Referring to fig. 1H and fig. 1I, the hard mask layer 104a is removed to expose the top surface 102t of the second semiconductor layer 102. In this case, as shown in fig. 1I, the top surface 200t of the HEMT device 200 is coplanar with the top surface 102t of the second semiconductor layer 102 a. From another perspective, the thickness T3 of the HEMT device 200 can be substantially equal to the sum of the thicknesses T4 of the second semiconductor layer 102a and the insulating layer 103 a. Therefore, after the deposition process of the subsequent layer stack, there is no significant height difference between the height of the layer stack in the area with the opening 105 and the height of the layer stack in the other area without the opening. Thus, the present embodiment can effectively improve the performance of the planarization process (e.g., the CMP process) of the subsequent layer stack.
Referring to fig. 1J, MOSFET devices 300 and 400 are formed on the second semiconductor layer 102a on both sides of the opening 105. In this case, the crystal plane < 100 > of the top surface 102t of the second semiconductor layer 102a is a crystal plane suitable for formation of the MOSFET devices 300, 400. Specifically, MOSFET device 300 includes a gate structure 302, doped regions 304, 306, and spacers 308. The gate structure 302 includes a gate dielectric layer 302a and a gate electrode 302b on the gate dielectric layer 302 a. In one embodiment, the material of the gate dielectric layer 302a includes silicon oxide, and the forming method thereof includes thermal oxidation or CVD. The material of the gate electrode 302b includes polysilicon, and a formation method thereof includes CVD. The doped regions 304 and 306 are respectively disposed in the second semiconductor layer 102a at two sides of the gate structure 302. The doped regions 304, 306 are formed, for example, by using the gate structure 302 as a mask and performing an ion implantation process to implant dopants into the second semiconductor layer 102 a. In one embodiment, the doped region 304 may be a source; and doped region 306 may be a drain. However, the invention is not limited thereto, and in other embodiments, the doped region 304 may also be a drain; and doped region 306 may be a source. The spacers 308 are disposed on the second semiconductor layer 102a on both sides of the gate structure 302. The material of the spacer 308 includes silicon oxide, silicon nitride or a combination thereof, and the method for forming the spacer 308 is well known to those skilled in the art and will not be described in detail herein.
Similarly, the MOSFET device 400 includes a gate structure 402, doped regions 404, 406, and spacers 408. The gate structure 402 includes a gate dielectric layer 402a and a gate electrode 402b on the gate dielectric layer 402 a. The doped regions 404 and 406 are respectively disposed in the second semiconductor layer 102a at two sides of the gate structure 402. The spacers 408 are disposed on the second semiconductor layer 102a on both sides of the gate structure 402. In an embodiment, the MOSFET devices 300, 400 may be MOSFET devices of the same type (N-type or P-type). In alternative embodiments, MOSFET elements 300, 400 may be different types of MOSFET elements.
Referring to fig. 1K, a source 214, a drain 216 and a region between the source 214 and the drain 216 are formed on the HEMT device 200And a gate electrode 212. Specifically, the gate 212 is formed on the dielectric layer 208 and is in contact with the dielectric layer 208. The source 214 extends through the dielectric layer 208 to contact the underlying barrier layer 206. The drain 216 extends through the dielectric layer 208 to contact the underlying barrier layer 206. In one embodiment, the materials of the gate 212, the source 214, and the drain 216 each comprise a conductive material, which may be a metal (e.g., Ta, Ti, W, Pd, Ni, Au, Al, or combinations thereof), a metal nitride (e.g., TaN, TiN, WN, or combinations thereof), a metal silicide (e.g., WSi)x) Or a combination thereof. In an embodiment, the gate 212, the source 214, and the drain 216 may be made of the same material, but the invention is not limited thereto. In other embodiments, the materials of the gate 212, the source 214, and the drain 216 may be different from each other.
Referring to fig. 1L and 1N, an interconnect structure 500 is formed on the HEMT device 200 and the MOSFET devices 300 and 400. Specifically, as shown in fig. 1L, a dielectric layer 108 is formed on a substrate 100 a. The dielectric layer 108 covers the surface of the HEMT device 200 and the MOSFET devices 300 and 400. In detail, as shown in fig. 1L, a portion 108P of the dielectric layer 108 also fills the gaps between the HEMT device 200 and the second semiconductor layer 102a and between the HEMT device 200 and the insulating layer 103a to electrically isolate the HEMT device 200 from the MOSFET devices 300 and 400. In one embodiment, the dielectric layer 108 may be referred to as an interlayer dielectric (ILD) layer, which may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. The method of forming the dielectric layer 108 includes CVD.
As shown in fig. 1L and 1M, the dielectric layer 108 is patterned to form a plurality of contact openings O1, O2, O3, O4, O5, O6, O7, O8, and O9 (hereinafter, referred to as contact openings O1-O9) in the dielectric layer 108 a. Specifically, the contact opening O1 exposes the doped region 304. The contact opening O2 exposes the gate electrode 302 b. The contact opening O3 exposes the doped region 306. The contact opening O4 exposes the source 214. The contact opening O5 exposes the gate 212. The contact opening O6 exposes the drain 216. The contact opening O7 exposes the doped region 404. The contact opening O8 exposes the gate electrode 402 b. The contact opening O9 exposes the doped region 406. In one embodiment, the contact openings O1-O9 are separate from each other and not connected to each other, as shown in FIG. 1M.
Next, as shown in fig. 1M and 1N, conductive plugs 314, 312, 316, 224, 222, 226, 414, 412, 416 are formed in the contact openings O1-O9, respectively. In one embodiment, the material of the conductive plugs 314, 312, 316, 224, 222, 226, 414, 412, 416 includes a conductive material, which may be a metal material, such as tungsten (W), aluminum (Al), copper (Cu), or a combination thereof. The formation of the conductive plugs 314, 312, 316, 224, 222, 226, 414, 412, 416 includes filling the contact openings O1-O9 with a conductive material, followed by a planarization process to remove excess conductive material on the dielectric layer 108 a. In one embodiment, the planarization process may be, for example, a CMP process or an etch-back process.
Then, referring to fig. 1N, a conductive layer 324 is formed on the conductive plug 314, such that the conductive plug 314 is electrically connected to the conductive layer 324 and the doped region 304. A conductive layer 322 is formed over the conductive plug 312 such that the conductive plug 312 electrically connects the conductive layer 322 with the gate electrode 302 b. A conductive layer 326 is formed over the conductive plugs 316, 224 such that the conductive layer 326 electrically connects the conductive plugs 316, 224 and electrically connects the doped region 306 and the source 214. A conductive layer 232 is formed on the conductive plug 222 such that the conductive plug 222 electrically connects the conductive layer 232 and the gate electrode 212. A conductive layer 236 is formed over the conductive plug 226 such that the conductive plug 226 electrically connects the conductive layer 236 with the drain 216. A conductive layer 424 is formed over the conductive plug 414 such that the conductive plug 414 electrically connects the conductive layer 424 and the doped region 404. A conductive layer 422 is formed over conductive plug 412 such that conductive plug 412 electrically connects conductive layer 422 and gate electrode 402 b. A conductive layer 426 is formed over conductive plug 416 such that conductive plug 416 electrically connects conductive layer 426 with doped region 406. It is noted that although not shown in the cross section of fig. 1N, the conductive layer 232 may be electrically connected to the conductive layer 324 by routing. In addition, another dielectric layer 118 may also be formed to laterally cover and electrically isolate the conductive layers 324, 322, 326, 232, 236, 424, 422, 426.
Referring to fig. 1O, conductive terminals 110a, 100b, 100c, 100d, and 100e (hereinafter referred to as conductive terminals 110a-100e) are formed on the conductive layers 324, 322, 236, 424, and 422, respectively. In one embodiment, the conductive terminals 110a-100e may be solder (solder paste), solder balls (solder balls), bumps, the like, or combinations thereof. In alternative embodiments, the material of the conductive terminals 110a-100e includes copper, aluminum, a lead-free alloy (e.g., gold, tin, silver, aluminum, or a copper alloy), or a lead alloy (e.g., a lead-tin alloy). As shown in fig. 1O, after the conductive terminals 110a-100e are formed, a singulation process is performed along the cut line C-C', thereby forming the semiconductor device 10.
Fig. 2 is a schematic top view of fig. 1O.
Referring to fig. 1O and fig. 2, the gate 212 of the HEMT device 200 is electrically connected to the doped region 304 (which can be regarded as a source) of the MOSFET device 300 through the conductive plug 222, the conductive layers 232 and 324 and the conductive plug 314. In addition, the source 214 of the HEMT device 200 is electrically connected to the doped region 306 (which may be regarded as the drain) of the MOSFET device 300 through the conductive plug 224, the conductive layer 326 and the conductive plug 316. In addition, the semiconductor device 10 can be externally connected to a source voltage S through the conductive terminal 110 a; the conductive terminal 110b is externally connected with a grid voltage G; and is externally connected to the drain voltage D through the conductive terminal 110 c. That is, the semiconductor device 10 can electrically connect the HEMT device 200 and the MOSFET device 300 together or be integrated on the same chip through the interconnect structure 500. Compared with the external bonding wire bonding method, the manufacturing method of the semiconductor device 10 of the embodiment has lower manufacturing cost, can reduce the chip area to achieve the miniaturization requirement, and further improves the reliability of the product.
In one embodiment, the HEMT device 200 is a normally on device that can be used for signal amplification and high voltage operation. And MOSFET device 300 is a normally off (normal off) device that can be used as a switching device. Therefore, this structure of cascading the HEMT device 200 with the MOSFET device 300 (cascode) can achieve a low threshold voltage, a fast switching speed, and maintain a high voltage capability.
In summary, the HEMT device and the MOSFET device are integrated on the same chip through the interconnect structure in the present invention, so as to achieve low threshold voltage, fast switching speed and maintain high voltage capability. Compared with the method of externally connecting the component in the packaging stage, the manufacturing method of the semiconductor element has lower manufacturing cost, can reduce the using area of a chip to meet the requirement of miniaturization, and further improves the reliability of the product.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, and that various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.

Claims (20)

1. A semiconductor component, comprising:
a semiconductor substrate on an insulator, comprising:
a first semiconductor layer;
a second semiconductor layer on the first semiconductor layer; and
an insulating layer between the first semiconductor layer and the second semiconductor layer;
a high electron mobility transistor element on the first semiconductor layer; and
a metal oxide semiconductor field effect transistor element on the second semiconductor layer and electrically connected to the high electron mobility transistor element, wherein a top surface of the high electron mobility transistor element is coplanar with a top surface of the second semiconductor layer.
2. The semiconductor device as claimed in claim 1, further comprising an interconnect structure on the HEMT device and the MOSFET device, wherein the HEMT device and the MOSFET device are electrically connected through the interconnect structure.
3. The semiconductor device of claim 1, wherein a gate of the hemt device is electrically connected to a source of the mosfet device and a source of the hemt device is electrically connected to a drain of the mosfet device.
4. The semiconductor device as claimed in claim 1, wherein the sidewalls of the high electron mobility transistor device are tapered sidewalls.
5. The semiconductor device as claimed in claim 4, further comprising a dielectric layer on the HEMT device and the MOSFET device and filling a gap between the HEMT device and the second semiconductor layer to electrically isolate the HEMT device and the MOSFET device.
6. The semiconductor device of claim 1, wherein the top surface of said first semiconductor layer is a < 111 > crystal plane and the top surface of said second semiconductor layer is a < 100 > crystal plane.
7. The semiconductor element according to claim 1, wherein a thickness of the second semiconductor layer is smaller than a thickness of the first semiconductor layer.
8. The semiconductor element according to claim 1, wherein the high electron mobility transistor element comprises:
a buffer layer on the first semiconductor layer;
the channel layer is positioned on the buffer layer;
a barrier layer on the channel layer;
a two-dimensional electron gas layer in the channel layer adjacent to the barrier layer.
9. The semiconductor device of claim 1, wherein said hemt device is a normally-on device and said mosfet device is a normally-off device.
10. A method for manufacturing a semiconductor device includes:
providing a semiconductor substrate on an insulator, wherein the semiconductor substrate on the insulator sequentially comprises a first semiconductor layer, an insulating layer and a second semiconductor layer;
forming an opening exposing the first semiconductor layer;
forming a high electron mobility transistor element on the first semiconductor layer in the opening; and
forming a metal oxide semiconductor field effect transistor element on the second semiconductor layer, wherein a top surface of the high electron mobility transistor element is coplanar with a top surface of the second semiconductor layer.
11. The method of claim 10, further comprising forming an interconnect structure over said hemt and mosfet devices, wherein said hemt and mosfet devices are electrically connected through said interconnect structure.
12. The method of claim 11, wherein said forming said interconnect structure comprises:
forming a dielectric layer on the HEMT device and the MOSFET device to fill a gap between the HEMT device and the second semiconductor layer;
forming a plurality of conductive plugs in the dielectric layer to be electrically connected with the high electron mobility transistor element and the metal oxide semiconductor field effect transistor element respectively; and
and forming a plurality of conductive layers to be respectively electrically connected with the plurality of conductive plugs.
13. The method according to claim 11, wherein a gate of the hemt device is electrically connected to a source of the mosfet device, and a source of the hemt device is electrically connected to a drain of the mosfet device.
14. The method of claim 11, further comprising, after said forming said interconnect structure:
forming a conductive terminal on the interconnection structure; and
and carrying out a monomer manufacturing process.
15. The method according to claim 10, wherein the sidewalls of the hemt device are tapered sidewalls, and the hemt device is electrically isolated from the mosfet device.
16. The method of manufacturing a semiconductor device according to claim 10, wherein the providing the semiconductor-on-insulator substrate comprises:
forming the insulating layer on a second semiconductor material; and
bonding the second semiconductor material upside down onto the first semiconductor layer such that the insulating layer is located between the first semiconductor layer and the second semiconductor material.
17. The method of manufacturing a semiconductor device according to claim 16, further comprising thinning the second semiconductor material to form the second semiconductor layer after inversely bonding the second semiconductor material to the first semiconductor layer, wherein a thickness of the second semiconductor layer is smaller than a thickness of the first semiconductor layer.
18. The method of claim 17, wherein a sum of thicknesses of the second semiconductor layer and the insulating layer is substantially equal to a thickness of the hemt device.
19. The method according to claim 10, wherein the top surface of the first semiconductor layer is a < 111 > crystal plane and the top surface of the second semiconductor layer is a < 100 > crystal plane.
20. The method for manufacturing a semiconductor element according to claim 10, wherein the forming the high electron mobility transistor element comprises:
epitaxially growing a buffer layer on the first semiconductor layer;
epitaxially growing a channel layer on the buffer layer; and
epitaxially growing a barrier layer on the channel layer, wherein a two-dimensional electron gas layer is formed in the channel layer proximate to the barrier layer.
CN201810986580.4A 2018-08-28 2018-08-28 Semiconductor device and method for manufacturing the same Pending CN110867441A (en)

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