WO2020192303A1

WO2020192303A1 - Semiconductor device and manufacturing method

Info

Publication number: WO2020192303A1
Application number: PCT/CN2020/075500
Authority: WO
Inventors: 林科闯; 邹鹏辉; 刘胜厚; 刘成; 李敏; 赵杰; 卢益峰; 蔡仙清; 杨健
Original assignee: 厦门市三安集成电路有限公司
Priority date: 2019-03-27
Filing date: 2020-02-17
Publication date: 2020-10-01
Also published as: CN109950317A

Abstract

Provided in the embodiments of the present application are a semiconductor device and a manufacturing method. The method comprises: successively forming a channel layer and a barrier layer, which are made of gallium nitride materials, on a substrate, and then preparing, based on an ohmic contact region formed on the barrier layer, through holes which penetrate the barrier layer, so as to expose part of the channel layer; and then depositing a plurality of ohmic metal layers on the barrier layer, and the plurality of deposited ohmic metal layers contacting the channel layer through the through holes, wherein an ohmic metal layer, which is in direct contact with the channel layer, of the plurality of ohmic metal layers is a tantalum metal layer. By means of preparing the through holes which penetrate the barrier layer, and depositing the plurality of ohmic metal layers at positions of the through holes in the barrier layer, distances between the ohmic metal layers and two-dimensional electron gas can be reduced, such that the temperature required for subsequent annealing is relatively low, and in conjunction with the characteristics of the tantalum metal layer, ohmic contact resistance which is subsequently formed can be reduced.

Description

Semiconductor device and manufacturing method

Technical field

This application relates to the field of microelectronics technology, specifically, to a semiconductor device and a manufacturing method.

Background technique

The third-generation semiconductor material GaN has a large band gap (3.4eV), high electron saturation rate (2×107cm/s), high breakdown electric field (1×1010～3×1010V/cm), high thermal conductivity, Corrosion resistance and radiation resistance, etc., and has broad application prospects. In particular, HEMT (High Electron Mobility Transistors) with AlGaN/GaN heterojunction structure has the advantages of high frequency, high power density, and high operating temperature, and is the future development direction of solid-state microwave power devices and power electronic devices . Among them, the ohmic contact process is one of the key technologies for making high-performance GaN-based devices, which directly affects the power, frequency and reliability of the device. Excellent ohmic contacts include low ohmic contact resistivity and good ohmic contact morphology.

Because GaN materials have high thermal stability and are not prone to chemical reactions, it is not easy to form ohmic contacts. For this reason, how to improve the quality of ohmic contacts has become an urgent problem to be solved in the production of high-quality GaN-based devices.

Summary of the invention

technical problem

The solution to the problem

Technical solutions

In view of this, the purpose of this application is to provide a semiconductor device and a manufacturing method thereof to improve the above-mentioned problems.

An embodiment of the present application provides a method for manufacturing a semiconductor device, the method including:

Provide a substrate;

Forming a channel layer based on the substrate, and the channel layer is made of gallium nitride material;

Forming a barrier layer on the side of the channel layer away from the substrate, and forming an ohmic contact area on the barrier layer;

Preparing a through hole penetrating the barrier layer based on the ohmic contact region of the barrier layer, exposing part of the channel layer;

Depositing a multi-layer ohmic metal layer based on the barrier layer, the multi-layer ohmic metal layer is in contact with the channel layer through the through hole, wherein the multi-layer ohmic metal layer is directly connected to the channel layer The contacted ohmic metal layer is a tantalum metal layer.

In the semiconductor device manufacturing method of the foregoing embodiment, the step of forming an ohmic contact region on the barrier layer includes:

Coating photoresist on the side of the barrier layer away from the channel layer;

The photoresist is exposed and developed to expose a part of the barrier layer to form the ohmic contact area, wherein the cross section of the photoresist after exposure and development is an inverted trapezoid.

In the semiconductor device manufacturing method of the foregoing embodiment, the step of depositing multiple ohmic metal layers based on the barrier layer includes:

A multilayer ohmic metal layer is deposited on the surface of the photoresist and the position of the through hole of the barrier layer, so that the multilayer ohmic metal layer corresponding to the position of the through hole passes through the through hole and the groove. Layer contact

The manufacturing method of the semiconductor device further includes:

Peeling off the photoresist and the multilayer ohmic metal layer deposited on the photoresist;

The multilayer ohmic metal layer in contact with the channel layer is annealed at low temperature to form a tantalum-based ohmic contact.

In the semiconductor device manufacturing method of the foregoing embodiment, the temperature condition used when the low-temperature annealing treatment is performed on the multilayer ohmic metal layer in contact with the channel layer is 550°C-700°C.

In the semiconductor device manufacturing method of the above embodiment, before the step of coating photoresist on the side of the barrier layer away from the channel layer, the method further includes:

Using N-methylpyrrolidone or acetone to remove organic matter on the surface of the barrier layer;

The oxide layer on the surface of the barrier layer is removed by using a hydrochloric acid solution or an aqueous ammonia solution.

In the semiconductor device manufacturing method of the foregoing embodiment, the cross-sectional area of the through hole gradually increases from the channel layer to the barrier layer.

In the semiconductor device manufacturing method of the foregoing embodiment, in the multilayer ohmic metal layer, in the direction from the channel layer to the barrier layer, the multilayer ohmic metal layer is a Ta metal layer and a Ti metal layer. , Al metal layer, Ni metal layer, Au metal layer, or Ta metal layer, Al metal layer, Ta metal layer in sequence, or Ta metal layer, Al metal layer, Ni metal layer, Au metal layer, or in sequence Ta metal layer, Ti metal layer, Al metal layer, TiN metal layer.

In the semiconductor device manufacturing method of the foregoing embodiment, the thickness of the Ta metal layer in the multilayer ohmic metal layer is 3-15 nm.

Another embodiment of the present application provides a semiconductor device, including:

Substrate

A channel layer formed based on the substrate, and the channel layer is made of gallium nitride material;

A barrier layer formed on the side of the channel layer away from the substrate, and an ohmic contact area formed on the barrier layer;

A through hole penetrating the barrier layer prepared based on the ohmic contact region of the barrier layer;

Based on the multi-layer ohmic metal layer deposited on the barrier layer, the multi-layer ohmic metal layer is in contact with the channel layer through the through hole, wherein the multi-layer ohmic metal layer is in contact with the channel layer The ohmic metal layer in direct contact is a tantalum metal layer.

In the semiconductor device and the manufacturing method provided in the embodiments of the present application, after the channel layer and the barrier layer made of gallium nitride material are sequentially formed on the substrate, the penetrating barrier layer is prepared based on the ohmic contact region formed in the barrier layer Through holes to expose part of the channel layer. Then, a multilayer ohmic metal layer is deposited on the barrier layer, and the deposited multilayer ohmic metal layer is in contact with the channel layer through the through hole, wherein the ohmic metal layer directly in contact with the channel layer in the multilayer ohmic metal layer is tantalum Metal layer. In this way, the distance between the ohmic metal layer and the two-dimensional electron gas can be reduced, so that the temperature required for subsequent annealing is lower, and combined with the characteristics of the tantalum metal layer, the subsequently formed ohmic contact resistance can be reduced.

The beneficial effects of the invention

Beneficial effect

In order to make the above-mentioned objectives, features and advantages of the present application more obvious and understandable, the preferred embodiments and accompanying drawings are described in detail as follows.

Brief description of the drawings

Description of the drawings

In order to more clearly describe the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings that need to be used in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore do not It should be regarded as a limitation of the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative work.

FIG. 1 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the application.

Figures 2 to 6 are schematic diagrams of the device structures formed in each corresponding step in the above manufacturing method.

FIG. 7 is a schematic diagram of the ohmic morphology after high temperature annealing in the prior art.

FIG. 8 is a schematic diagram of the ohmic morphology after low-temperature annealing in the semiconductor device manufacturing method provided by the embodiment of the application.

Fig. 9 is a schematic diagram of an ohmic cross-section after high-temperature annealing in the prior art.

FIG. 10 is a schematic diagram of an ohmic cross-section after low-temperature annealing in a semiconductor device manufacturing method provided by an embodiment of the application.

Icons: 1-substrate; 2-channel layer; 3-barrier layer; 31-ohmic contact area; 32-via; 4-photoresist; 5-ohmic metal layer.

Invention embodiment

Embodiments of the invention

In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments It is only a part of the embodiments of the present application, but not all the embodiments. The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various different configurations.

Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the present application. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of this application.

Because GaN materials have high thermal stability and are not prone to chemical reactions, it is not easy to form ohmic contacts. Generally, when GaN materials need to form ohmic contact with low barrier active metal alloys such as Ti and Al, the alloy temperature needs to be above 800°C. However, the melting point of metal Al is low. The traditional ohmic contact metal Ti/Al/Ni/Au is in a molten state during alloying, which is prone to metal expansion and metal accumulation, and part of Al will form AlAu ₂ or AlAu ₄ crystals with Au. Particles make the surface of the ohmic metal rough and the edges of the metal are uneven. For power electronic devices, rough ohmic contact edges will cause the appearance of peak electric fields, which will reduce the breakdown characteristics of the device. For microwave devices, it will also cause uneven current distribution and high signal attenuation.

At present, there are many methods for improving the ohmic contact of GaN-based materials. For example, N-type doping in the source and drain regions can effectively increase the doping concentration of the ohmic contact, thereby reducing the ohmic contact resistivity. However, the cost of this method is relatively high, and the required high temperature annealing above 1000° C. will have a negative impact on the device.

For another example, the source and drain regions are dry-etched and slotted. Specifically, the thickness of the barrier layer is reduced by etching to increase the tunneling effect between the metal and the semiconductor and reduce the alloy temperature of the ohmic contact. However, this method must precisely control the plasma etching power and time, and the process repeatability is poor.

Based on the above research findings, the embodiments of the present application provide a semiconductor device and a manufacturing method. After a channel layer and a barrier layer made of gallium nitride material are sequentially formed on a substrate, based on the ohmic layer formed on the barrier layer. The contact area is prepared with a through hole penetrating the barrier layer to expose a part of the channel layer. Then, a multilayer ohmic metal layer is deposited on the barrier layer so that the multilayer ohmic metal layer is in contact with the channel layer through the through hole, wherein the metal layer directly in contact with the channel layer in the multilayer ohmic metal is a tantalum metal layer. By preparing through holes penetrating the barrier layer and depositing multiple layers of ohmic metal at the through hole position of the barrier layer, the distance between the ohmic metal and the two-dimensional electron gas can be reduced, so that the temperature required for subsequent annealing is lower, and it is combined with tantalum The metal properties reduce the resistance of the subsequent ohmic contact.

Please refer to FIG. 1, an embodiment of the present application provides a method for manufacturing a semiconductor device, which is used for manufacturing a semiconductor device. It should be noted that the manufacturing method of the semiconductor device provided in this application is not limited to the specific sequence described in FIG. 1 and the following. It should be understood that the order of some steps in the manufacturing method of the semiconductor device described in this application can be interchanged according to actual needs, or some of the steps can also be omitted or deleted, which is not limited in this embodiment.

In step 110, a substrate 1 is provided. Among them, the substrate 1 (also called substrate or substrate) can be sapphire, SiC, GaN, Si or any other substrate 1 suitable for growing nitride materials known to those skilled in the art. No specific restrictions.

In step 120, a channel layer 2 is formed based on the substrate 1, and the channel layer 2 is made of gallium nitride material.

In step 130, a barrier layer 3 is fabricated on the side of the channel layer 2 away from the substrate 1, and an ohmic contact region 31 is formed on the barrier layer 3.

In this embodiment, the schematic diagram after the channel layer 2 and the barrier layer 3 are formed on the substrate 1 is shown in FIG. 2, and the schematic diagram after the ohmic contact region 31 is formed on the barrier layer 3 is shown in FIG. Show. The method of sequentially fabricating the channel layer 2 and the barrier layer 3 based on the substrate 1 can be CVD, VPE, MOCVD, LPCVD, PECVD, pulsed laser deposition (PLD), atomic layer epitaxy, MBE, sputtering, evaporation, etc. , No specific restrictions.

The channel layer 2 and the barrier layer 3 thereon form a heterojunction structure together, and the channel layer 2 is used to provide a channel for carrier movement. In this embodiment, the channel layer 2 is unintentionally doped GaN.

The barrier layer 3 functions as a barrier, blocking the flow of carriers in the channel layer 2 to the barrier layer 3. The barrier layer 3 may include gallium nitride (GaN) and other gallium-based compound semiconductor materials, such as AlGaN, InGaN, etc., or may be a stack of gallium-based compound semiconductor materials and other semiconductor materials. In this embodiment, the barrier layer 3 is unintentionally doped AlGaN.

In this embodiment, the ohmic contact region 31 on the barrier layer 3 can be formed in the following manner:

After the channel layer 2 and the barrier layer 3 are sequentially formed on the substrate 1, a photoresist 4 is coated on the side of the barrier layer 3 away from the channel layer 2. Wherein, the coated photoresist 4 may be reversed adhesive AE5214 or reversed adhesive SPR220. Then, by partially exposing and developing the photoresist 4, a part of the barrier layer 3 is exposed to open an ohmic contact region 31, as shown in FIG. 3. Among them, in the process of gluing and exposure and development, the gluing speed and time during gluing, the baking time and temperature after gluing, the intensity of exposure and exposure time, and the developer ratio and development time and other process parameters are all Will affect the final development effect. In this embodiment, by controlling the relevant process parameters, photoresist patterns with different cross-sectional shapes can be produced. Taking into account that if the sidewall of the photoresist is vertical or sloped, after the metal is deposited on it, it will be easier to peel off when the metal layer is thin, but if the thickness of the metal increases, the metal will be covered in one piece. The surface of the photoresist 4 is not easy to peel off. Therefore, in this embodiment, by controlling the relevant process parameters, the finally formed photoresist 4 has an inverted trapezoidal cross-section. In this way, since the sidewalls of the photoresist 4 are not covered by metal, the The resist 4 is easily soluble in organic solvents, and the metal on the resist 4 is also removed at the same time.

In this embodiment, before coating the photoresist 4 on the barrier layer 3, the surface of the barrier layer 3 can be cleaned, and the organic matter on the surface of the barrier layer 3 can be removed by using N-methylpyrrolidone or acetone. Then, the oxide layer on the surface of the barrier layer 3 is removed by using a hydrochloric acid solution or an ammonia solution. Wherein, the concentration of the hydrochloric acid solution can be 3%-30%, and the concentration of the aqueous ammonia solution can be 3%-30%.

In step 140, a through hole 32 penetrating the barrier layer 3 is prepared based on the ohmic contact region 31 of the barrier layer 3, and a part of the channel layer 2 is exposed, as shown in FIG.

Step 150, depositing multiple ohmic metal layers 5 based on the barrier layer 3, the multiple ohmic metal layers 5 being in contact with the channel layer 2 through the through holes 32, as shown in FIG. Wherein, the ohmic metal layer 5 directly in contact with the channel layer 2 in the multi-layer ohmic metal layer 5 is a tantalum metal layer.

In this embodiment, based on the physical characteristics that the tunneling current between the ohmic metal and the two-dimensional electron gas channel increases as the distance between the two decreases, the barrier layer 3 is formed with a through hole that penetrates the barrier layer 3 32, so that the subsequently deposited ohmic metal layer 5 can be closer to the two-dimensional electron gas or directly in contact with the two-dimensional electron gas, so as to reduce the ohmic contact resistance and lower the temperature required for annealing.

After the ohmic contact region 31 is formed on the barrier layer 3, the barrier layer 3 is etched based on the ohmic contact region 31 on the barrier layer 3 to prepare a via 32 penetrating the barrier layer 3, as shown in FIG. 4 . Optionally, the barrier layer 3 may be etched from the ohmic contact region 31 by using inductively coupled plasma in a set etching atmosphere with a power of 30-300W in a pressure range of 3-15mTorr to form a through The through hole 32 of the barrier layer 3. Wherein, the etching atmosphere is any one of the mixed gas of Cl ₂ , BCl ₃ , Cl ₂ and BCl ₃ , and the etching time is 90 s to 300 s.

When the barrier layer 3 is etched, any one of dry etching technology, oxidation etching technology, and wet etching technology can be used, which is not specifically limited in this embodiment.

In this embodiment, from the channel layer 2 to the barrier layer 3, the cross-sectional area of the through hole 32 formed by etching gradually increases, that is, a through hole 32 with a larger opening is formed. The depth value of the through hole 32 can be determined according to the actual situation. For example, the through hole 32 can just penetrate the barrier layer 3, or extend through the barrier layer 3 and then extend to the channel layer 2, that is, etch to the channel layer 2. To form a groove on the channel layer 2. Specifically, it can be determined according to requirements or etching conditions.

After the through hole 32 penetrating the barrier layer 3 is obtained by etching, a multilayer ohmic metal layer 5 is deposited on the barrier layer 3, wherein the deposited multilayer ohmic metal layer 5 passes through the through hole 32 on the barrier layer 3 and The channel layer 2 is in contact, as shown in FIG. 5. At the same time, multiple ohmic metal layers 5 are deposited on the surface of the photoresist 4. Among them, the ohmic metal layer 5 directly in contact with the channel layer 2 in the multilayer ohmic metal layer 5 is a tantalum metal layer. The vapor deposition process can be used to deposit multiple ohmic metal layers 5 on the positions of the through holes 32 of the barrier layer 3 and the photoresist 4. In the multiple ohmic metal layers 5, the direction from the channel layer 2 to the barrier layer 3 The multilayer ohmic metal layer 5 is a Ta metal layer, a Ti metal layer, an Al metal layer, a Ni metal layer, and an Au metal layer in sequence, or a Ta metal layer, an Al metal layer, a Ta metal layer, or a Ta metal layer, Al metal layer, Ni metal layer, Au metal layer, or Ta metal layer, Ti metal layer, Al metal layer, TiN metal layer in sequence.

Optionally, in the deposited multilayer ohmic metal layer 5, the thickness of the Ta metal layer is 3-15 nm, and the thickness of the Al metal layer is 100-150 nm. When a Ti metal layer is included in the multilayer ohmic metal layer 5, the thickness of the Ti metal layer may be 3-20 nm. When the Ni metal layer is included, the thickness of the Ni metal layer may be 30-60 nm. When the Au metal layer is included, the thickness of the Au metal layer may be 5-50 nm. The specific thickness of each ohmic metal layer 5 can be adjusted according to the ohmic contact resistance after the final alloy and the feedback value of the ohmic morphology.

In this embodiment, before the step of evaporating the ohmic metal, a cleaning step may also be performed to maintain the cleanliness of the surface of the device. Optionally, a hydrochloric acid solution or a hydrofluoric acid solution is used for cleaning before the metal is evaporated. Wherein, the concentration ratio of the hydrochloric acid solution can be 1:3-1:10, the concentration ratio of the hydrofluoric acid solution can be 1:3-1:10, and the cleaning treatment time can be 15-120s to ensure the cleanliness of the device surface.

After depositing multiple ohmic metal layers 5 on the position of the through holes 32 and the photoresist 4, the photoresist 4 and the multiple ohmic metal layers 5 thereon can be removed. The photoresist 4 and the multilayer ohmic metal layer 5 deposited on the photoresist 4 can be removed by using N-methylpyrrolidone or acetone. Oxygen plasma is used to filter the removed device again to ensure that the photoresist 4 is completely removed. After removing the photoresist 4 and the multilayer ohmic metal layer 5 thereon, the device structure as shown in FIG. 6 is formed.

For the resulting device structure shown in FIG. 6, the multilayer ohmic metal layer 5 in contact with the channel layer 2 is annealed at low temperature to form a tantalum-based ohmic contact. Wherein, the multi-layer ohmic metal layer 5 deposited on the channel layer 2 can be continuously subjected to a low-temperature annealing treatment for 30-120s in a nitrogen atmosphere under a set temperature condition using a rapid thermal annealing furnace to form a low-temperature tantalum-based ohmic contact. , The set temperature condition is 550℃-700℃.

The manufacturing method provided in this embodiment is to etch the ohmic contact region 31 of the barrier layer 3 to prepare the through hole 32 penetrating the barrier layer 3, and combine to form a tantalum-based ohmic metal to reduce the ohmic metal to the two-dimensional electron gas. Even the ohmic metal can directly contact the two-dimensional electron gas, thereby reducing the ohmic contact resistance and lowering the annealing temperature. The tantalum and gallium nitride in the tantalum-based ohmic metal are annealed to generate tantalum nitride, which produces nitrogen vacancies on the gallium nitride surface to form an ohmic contact. Compared with the currently used titanium metal to form titanium nitride, tantalum nitride barrier The height is lower. In addition, tantalum metal is also an excellent barrier metal, which can block the diffusion of the upper ohmic metal to the gallium nitride layer during annealing and subsequent high temperature processes, thereby improving the thermal stability and reliability of the device.

Through the above production process, it can achieve low annealing temperature (less than 700℃), good ohmic metal morphology, low contact resistance (≤0.3Q·mm), and good thermal stability (the interface between the metal and gallium nitride is clear after tempering, and the There is metal sinking), and the gallium nitride ohmic contact process with good process repeatability. FIG. 7 shows the ohmic morphology after high temperature annealing in a traditional process, and FIG. 8 shows the ohmic morphology after low temperature annealing in the manufacturing method provided in this embodiment. It can be seen from FIGS. 7 and 8 that the ohmic metal formed in the traditional process has a rough surface and uneven edges, while the edges of the ohmic metal formed by the manufacturing method provided in this application are neat. FIG. 9 is a schematic diagram of an ohmic profile after high temperature annealing in a traditional process, and FIG. 10 is a schematic diagram of an ohmic profile after low temperature annealing of the manufacturing method provided in this embodiment. It can be seen from FIG. 9 and FIG. 10 that the ohmic metal formed in the traditional process has metal sinking at the gallium nitride interface, and the ohmic metal formed by the manufacturing method provided in this application is annealed between the ohmic metal and gallium nitride. The interface is clear, and there is no metal sinking.

The manufacturing method provided in this embodiment solves the problems of high annealing temperature, poor ohmic topography, large contact resistance, or poor process repeatability encountered in different ohmic manufacturing processes of gallium nitride devices.

Please refer to FIG. 6 again. Another embodiment of the present application also provides a semiconductor device, which is manufactured by the above-mentioned manufacturing method. The semiconductor device includes a substrate 1 and is formed based on the substrate 1. Channel layer 2 made of gallium material. An ohmic contact region 31 is formed on the barrier layer 3 based on the barrier layer 3 formed on the side of the channel layer 2 away from the substrate 1. A through hole 32 penetrating the barrier layer 3 is prepared based on the ohmic contact region 31 of the barrier layer 3. The multi-layer ohmic metal layer 5 deposited on the barrier layer 3 and contacting the channel layer 2 through the through holes 32 thereon, wherein the ohmic metal layer 5 in the multi-layer ohmic metal layer 5 directly in contact with the channel layer 2 is Tantalum metal layer.

It is understandable that the semiconductor device in this embodiment is manufactured by the above-mentioned manufacturing method. For the relevant features of the semiconductor device, reference may be made to the relevant description of the manufacturing method of the above-mentioned embodiment. This embodiment will not be repeated here. .

In summary, the semiconductor device and the manufacturing method provided by the embodiments of the present application are based on the formation of the channel layer 2 and the barrier layer 3 made of gallium nitride material on the substrate 1. The ohmic contact region 31 of 3 is prepared with a through hole 32 penetrating the barrier layer 3 to expose a part of the channel layer 2. Then, a multilayer ohmic metal layer 5 is deposited on the barrier layer 3. The deposited multilayer ohmic metal layer 5 is in contact with the channel layer 2 through the through hole 32, wherein the multilayer ohmic metal layer 5 is directly connected to the channel layer 2 The contacted ohmic metal layer 5 is a tantalum metal layer. By preparing through holes 32 penetrating the barrier layer 3 and depositing multiple ohmic metal layers 5 at the positions of the through holes 32 of the barrier layer 3, the distance between the ohmic metal layer 5 and the two-dimensional electron gas can be reduced, and the subsequent annealing process can be reduced. Temperature is required, and combined with the characteristics of the tantalum metal layer, the subsequent ohmic contact resistance is reduced.

The above descriptions are only preferred embodiments of the application, and are not used to limit the application. For those skilled in the art, the application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included in the protection scope of this application.

Claims

A method for manufacturing a semiconductor device, characterized in that the method includes:

Provide a substrate;

Forming a channel layer based on the substrate, and the channel layer is made of gallium nitride material;

Forming a barrier layer on the side of the channel layer away from the substrate, and forming an ohmic contact area on the barrier layer;

Preparing a through hole penetrating the barrier layer based on the ohmic contact region of the barrier layer, exposing part of the channel layer;

Depositing a multi-layer ohmic metal layer based on the barrier layer, the multi-layer ohmic metal layer is in contact with the channel layer through the through hole, wherein the multi-layer ohmic metal layer is directly connected to the channel layer The contacted ohmic metal layer is a tantalum metal layer.
The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming an ohmic contact region on the barrier layer comprises:

Coating photoresist on the side of the barrier layer away from the channel layer;

The photoresist is exposed and developed to expose a part of the barrier layer to form the ohmic contact area, wherein the cross section of the photoresist after exposure and development is an inverted trapezoid.
4. The method of manufacturing a semiconductor device according to claim 2, wherein the step of depositing multiple ohmic metal layers based on the barrier layer comprises:

A multilayer ohmic metal layer is deposited on the surface of the photoresist and the position of the through hole of the barrier layer, so that the multilayer ohmic metal layer corresponding to the position of the through hole passes through the through hole and the groove. Layer contact

The manufacturing method of the semiconductor device further includes:

Peeling off the photoresist and the multilayer ohmic metal layer deposited on the photoresist;

The multilayer ohmic metal layer in contact with the channel layer is annealed at low temperature to form a tantalum-based ohmic contact.
The method of manufacturing a semiconductor device according to claim 3, wherein the temperature condition used when the low-temperature annealing treatment is performed on the multilayer ohmic metal layer in contact with the channel layer is 550°C-700°C.
4. The method for manufacturing a semiconductor device according to claim 2, wherein before the step of coating photoresist on the side of the barrier layer away from the channel layer, the method further comprises:

Using N-methylpyrrolidone or acetone to remove organic matter on the surface of the barrier layer;

The oxide layer on the surface of the barrier layer is removed by using a hydrochloric acid solution or an aqueous ammonia solution.
The method of manufacturing a semiconductor device according to claim 1, wherein the cross-sectional area of the through hole gradually increases from the channel layer to the barrier layer.
The method for manufacturing a semiconductor device according to claim 1, wherein in the multilayer ohmic metal layer, the multilayer ohmic metal layer is Ta metal in order from the channel layer to the barrier layer. Layer, Ti metal layer, Al metal layer, Ni metal layer, Au metal layer, or Ta metal layer, Al metal layer, Ta metal layer, or Ta metal layer, Al metal layer, Ni metal layer, Au metal in sequence The layers, or in turn are Ta metal layer, Ti metal layer, Al metal layer, TiN metal layer.
7. The method for manufacturing a semiconductor device according to claim 7, wherein the thickness of the Ta metal layer in the multilayer ohmic metal layer is 3-15 nm.
A semiconductor device, characterized in that it comprises:

Substrate

A channel layer formed based on the substrate, and the channel layer is made of gallium nitride material;

A barrier layer formed on the side of the channel layer away from the substrate, and an ohmic contact area formed on the barrier layer;

A through hole penetrating the barrier layer prepared based on the ohmic contact region of the barrier layer;

Based on the multi-layer ohmic metal layer deposited on the barrier layer, the multi-layer ohmic metal layer is in contact with the channel layer through the through hole, wherein the multi-layer ohmic metal layer is in contact with the channel layer The ohmic metal layer in direct contact is a tantalum metal layer.