CN210897292U - Gallium nitride epitaxial layer and semiconductor device - Google Patents

Gallium nitride epitaxial layer and semiconductor device Download PDF

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Publication number
CN210897292U
CN210897292U CN201921620855.9U CN201921620855U CN210897292U CN 210897292 U CN210897292 U CN 210897292U CN 201921620855 U CN201921620855 U CN 201921620855U CN 210897292 U CN210897292 U CN 210897292U
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layer
buffer layer
gallium nitride
semiconductor device
buffer
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林信南
刘美华
刘岩军
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SHENZHEN JINGXIANG TECHNOLOGY CO LTD
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SHENZHEN JINGXIANG TECHNOLOGY CO LTD
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • H01L29/66204—Diodes
    • H01L29/66212—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Abstract

The utility model discloses a gallium nitride epitaxial layer and semiconductor device relates to semiconductor technology field. The utility model discloses a semiconductor device includes: the buffer layer structure comprises a semiconductor substrate, a first buffer layer, a nanometer buffer layer, a second buffer layer, a barrier layer, a dielectric layer, a source electrode, a drain electrode and a grid electrode. The utility model provides a great problem of lattice mismatch degree between substrate and the barrier layer among the semiconductor device.

Description

Gallium nitride epitaxial layer and semiconductor device
Technical Field
The utility model relates to the field of semiconductor technology, especially, relate to a gallium nitride epitaxial layer and semiconductor device.
Background
The semiconductor device is a semiconductor device manufactured by using a metal contact semiconductor layer, and has a characteristic that a reverse recovery time is extremely short compared with a conventional semiconductor diode, and therefore, the semiconductor device is widely applied to circuits such as a switching power supply, a frequency converter, a driver and the like. The gallium nitride material is a third generation wide bandgap semiconductor material, and has the characteristics of large bandgap width, high electronic saturation rate, high breakdown electric field, high thermal conductivity, corrosion resistance, radiation resistance and the like, so that the gallium nitride material becomes an optimal material for manufacturing short-wave photoelectronic devices and high-voltage high-frequency high-power devices. In conclusion, the semiconductor device prepared by using the gallium nitride material combines the advantages of the semiconductor device and the gallium nitride material, has the advantages of high switching speed, high field intensity, good thermal performance and the like, and has good development prospect in the market of power rectifiers.
However, due to the fact that the lattice mismatch degree between the substrate and the barrier layer of the conventional semiconductor device structure is large, defects in the barrier layer are large, and the performance and the service life of the final semiconductor device are affected.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a gallium nitride epitaxial layer and semiconductor device has solved the problem of high lattice mismatch between semiconductor substrate and the barrier layer, and it is more to cause the defect in the barrier layer, influences final semiconductor device's performance and life-span.
In order to solve the technical problem, the utility model discloses a realize through following technical scheme:
the utility model provides a semiconductor device, it includes:
a semiconductor substrate;
a first buffer layer disposed on the semiconductor substrate;
the nanometer buffer layer is arranged on one side of the first buffer layer far away from the semiconductor substrate;
the second buffer layer is arranged on one side, far away from the first buffer layer, of the nanometer buffer layer;
the barrier layer is arranged on one side of the second buffer layer far away from the nanometer buffer layer;
the dielectric layer is arranged on one side, far away from the second buffer layer, of the barrier layer;
the source electrode penetrates through the dielectric layer and extends into the barrier layer;
the drain electrode penetrates through the dielectric layer and extends into the barrier layer;
the grid electrode penetrates through the dielectric layer and extends into the barrier layer, one part of the grid electrode protrudes out of the top of the dielectric layer, the grid electrode is of a conical structure, and the ratio of the upper edge to the lower edge of the conical structure is 1: 2-1: 4.
in an embodiment of the present invention, the nano buffer layer is a gallium nitride nano crystal layer.
In one embodiment of the present invention, the barrier layer has a wider band gap than the second buffer layer band gap and induces a 2D electron gas (2DEG) in the channel.
In an embodiment of the present invention, a portion of the source electrode protrudes from the top of the dielectric layer.
In an embodiment of the present invention, a portion of the drain protrudes from the top of the dielectric layer.
In an embodiment of the present invention, a portion of the gate protrudes from the top of the dielectric layer.
In an embodiment of the present invention, the gate electrode penetrates through the dielectric layer and extends into the bottom of the barrier layer.
The utility model also provides a gallium nitride epitaxial layer, its characterized in that, it includes:
a semiconductor substrate;
a first buffer layer disposed on the semiconductor substrate;
the nanometer buffer layer is arranged on one side of the first buffer layer far away from the semiconductor substrate;
the second buffer layer is arranged on one side, far away from the first buffer layer, of the nanometer buffer layer;
a barrier layer disposed on a side of the second buffer layer distal from the nano-buffer layer.
In an embodiment of the present invention, the nano buffer layer is a gallium nitride nano crystal layer.
In one embodiment of the present invention, the thickness of the nanometer buffer layer is 0.5-2 nm.
The utility model discloses a gallium nitride epitaxial layer is through setting up multilayer buffer layer and nanometer buffer layer between substrate and barrier layer to reduce the lattice mismatch between semiconductor substrate and the barrier layer, the utility model discloses a semiconductor device passes through the special design of grid structure, can restrain the high electric field at grid edge, has guaranteed the stable characteristic of blocking of gallium nitride semiconductor device effectively, makes the device after high pressure is relapse, still can keep good reliability.
Of course, it is not necessary for any particular product to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a gallium nitride epitaxial layer according to the present invention;
FIG. 2 is a flow chart of a method for preparing the GaN epitaxial layer of FIG. 1;
FIG. 3 is a schematic view of a semiconductor device obtained by using the gallium nitride epitaxial layer of FIG. 1;
FIG. 4 is a flow chart of a method of fabricating the semiconductor device of FIG. 3;
fig. 5 is a schematic structural view of another semiconductor device obtained by using the gallium nitride epitaxial layer of fig. 1;
fig. 6 is a flowchart of a method of manufacturing the semiconductor device of fig. 5.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.
Gallium nitride materials have low heat generation rates and high breakdown electric fields, and are important materials for developing high-temperature high-power electronic devices and high-frequency microwave devices. The gallium nitride material can be used for preparing novel devices such as metal field effect transistors (MESFETs), Heterojunction Field Effect Transistors (HFETs), modulation-doped field effect transistors (MODFETs) and the like. The modulation doped AlGaN/GaN structure has high electron mobility (2000 cm)2The dielectric constant is lower, the material is the priority material for manufacturing microwave devices, gallium nitride has wider forbidden band width (3.4eV), materials such as sapphire and silicon carbide are used as substrates, the heat dissipation performance is good, and the device can work under the condition of high power.
The utility model provides a gallium nitride epitaxial layer and semiconductor device can use on power semiconductor device or radio frequency semiconductor device.
Referring to fig. 1, in another embodiment of the present invention, a gallium nitride epitaxial layer may further include: a semiconductor substrate 1400, a first buffer layer 1401, a nano-buffer layer 1402, a second buffer layer 1403, and a barrier layer 1404.
Referring to fig. 1, a first buffer layer 1401 is disposed on a semiconductor substrate 1400, the first buffer layer 1401 may be, for example, an aluminum nitride layer, and the thickness of the first buffer layer 1401 is, for example, 10nm to 300 nm. The nano-buffer layer 1402 is disposed on a side of the first buffer layer 1401 remote from the semiconductor substrate 1400. The second buffer layer 1403 is disposed on a side of the nano buffer layer 1402 away from the first buffer layer 1401, and the second buffer layer 1403 may be, for example, a gallium nitride or aluminum gallium nitride layer. The barrier layer 1400 is disposed on a side of the second buffer layer 1403 remote from the nanolayer 1402. The nano buffer layer 1402 may be, for example, a gallium nitride nanocrystal or an aluminum gallium nitride nanocrystal.
Referring to fig. 2, the present embodiment further provides a method for fabricating a gan-based epitaxial wafer, which includes the following steps: in step S1400, a first buffer layer 1401 is grown on a semiconductor substrate, the material of the semiconductor substrate 1400 is, for example, one of sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, aluminum nitride, or gallium nitride, an oxide layer on the surface of the semiconductor substrate 1400 is removed by a hydrofluoric acid solution treatment, and then the first buffer layer 1401, for example, a single-layer aluminum nitride buffer layer, is deposited by a PVD process, with a thickness range of, for example, 10-50nm, specifically, the epitaxial-grade semiconductor substrate 1400 (here, for example, a Si substrate) is placed on a tray made of SiC material, the tray is placed on a PVD sputtering machine, and is transported to a machine deposition chamber. After the semiconductor substrate 1400 is placed, the deposition chamber is evacuated, and the semiconductor substrate 1400 is heated while the chamber is evacuated. Background vacuum is drawn below, for example, 10-5-10-7The temperature is stabilized at 400 ℃ to 600 ℃ for Torr, and the semiconductor substrate 1400 is baked for 1 to 10 minutes, for example. After the semiconductor substrate 1400 is baked, Ar, N2, O2, Ar: the flow ratio of N2 is, for example, 10:2 to 1:1, and the flow ratio of O2 is, for example, 0to 5% of the sum of the flows of Ar and N2. The total gas flow is preferably maintained at a PVD deposition chamber pressure of, for example, 2-8 mTorr. Meanwhile, the heating temperature of the semiconductor substrate 1400 is set to the deposition temperature, preferably within a range of 400-600 ℃. And introducing reaction gas, switching on a sputtering power supply after the deposition temperature is stabilized for 10-60 seconds, and sputtering the Al target, wherein the AlN crystal film doped with O is deposited on the semiconductor substrate 1400. The sputtering power can be set, for example, to 1KW to 10KW depending on the requirement of the deposition rate, and the sputtering time can be set, for example, to 10 seconds to 1000 seconds depending on the thickness.
In step S1401, a molecular beam epitaxy process is used to prepare a nano buffer layer 1402, such as a gan nano buffer layer 1402, on a first buffer layer, a substrate and several molecular beam source furnaces are placed in an ultra-high vacuum system, and various elements constituting a compound, such as Ga, N and dopant, are respectively placed in different injection furnaces to be heated and cracked and ionized in different source furnaces, so that their molecules or atoms are injected onto the surface of the heated substrate at a certain thermal motion speed and a certain proportional intensity of beam, and the molecules or atoms interact with the surface, and a single crystal film is grown. The growth rate of the single crystal thin film is, for example, 0.01 to 1 μm/h, and the growth temperature is, for example, 500-. In step S1402, further, a second buffer layer 1403, such as a gallium nitride buffer layer, is prepared on the nano buffer layer 1402 by using a PVD process, and the gallium nitride buffer layer can also be prepared by the two-step method of the above embodiment.
In step S1403, further, a second buffer layer 1403, such as a gan buffer layer, is prepared on the post-processing layer 1402, and the preparation of the gan buffer layer can be achieved by a two-step method, in which a gan nucleation layer is grown at a temperature of, for example, 450-600 ℃ and a pressure of, for example, 200-500torr, and then a gan three-dimensional and two-dimensional cladding layer is grown by raising the temperature to 950-1200 ℃, and the nucleation layer and the subsequent three-dimensional two-dimensional gan buffer layer are collectively referred to as gan buffer layer.
In step S1404, a barrier layer 1404, such as a gan barrier layer 1404, is grown on the gan buffer layer at a temperature of, for example, 950 ℃ to 1100 ℃ and a pressure of, for example, 70torr to 200torr, and the gan barrier layer 1404 is grown on the gan buffer layer, wherein the thickness of the gan barrier layer 1404 is, for example, 50nm to 500 nm. And cooling after the epitaxy is finished to obtain the gallium nitride-based epitaxial layer.
The control of the temperature and the pressure refers to the control of the temperature and the pressure in a reaction chamber for growing the epitaxial wafer, and specifically relates to a reaction chamber of Metal Organic Chemical Vapor Deposition (MOCVD) equipment. During implementation, trimethyl gallium or triethyl gallium is used as a gallium source, high-purity ammonia gas is used as a nitrogen source, trimethyl indium is used as an indium source, trimethyl aluminum is used as an aluminum source, silane is used as a silicon source, tetramethyl germanium is used as a germanium source, and cyclopentadienyl magnesium is used as a magnesium source.
Referring to fig. 3, the present invention further provides a semiconductor device based on a gan epitaxial layer, including: the semiconductor device comprises a semiconductor substrate 1400, a first buffer layer 1401, a nanometer buffer layer 1402, a second buffer layer 1403, a barrier layer 1404, a dielectric layer 705, a source electrode 704, a drain electrode 706 and a gate electrode 707.
Referring to fig. 3, a first buffer layer 1401 is disposed on a semiconductor substrate 1400, a post-processing layer 1402 is disposed on a side of the first buffer layer 1401 remote from the semiconductor substrate 1400, a second buffer layer 1403 is disposed on a side of the post-processing layer 1402 remote from the first buffer layer 1401, a barrier layer 1404 is disposed on a side of the second buffer layer 1403 remote from the post-processing layer 1402, the barrier layer 1404 having a wider band gap than the band gap of the second buffer layer 1403 and inducing a 2D electron gas (2DEG) in the channel. Dielectric layer 705 is disposed on the side of barrier layer 1404 away from second buffer layer 1403. The source 704, the drain 706 and the gate 707 are disposed in the dielectric layer 705, the source 704, the drain 706 and the gate 707 respectively penetrate through the dielectric layer 705 and are connected with the barrier layer 1404, and a portion of the source 704, the drain 706 and the gate 707 protrudes from the top of the dielectric layer 705, wherein the gate 707 protrudes into the barrier layer 1404 to reach the bottom of the barrier layer 1404, the gate 707 has a tapered structure, and the ratio of the upper edge to the lower edge of the taper is, for example: 2. the utility model discloses grid 707 among the semiconductor device pierces through whole dielectric layer 705 and reachs barrier layer 1404, can restrain the high electric field at grid edge, has guaranteed the stable characteristic of blocking of gallium nitride semiconductor device effectively, makes the device after high pressure is relapsed, still can keep good reliability. Meanwhile, the gate 707 has a tapered structure, and the ratio of the upper edge to the lower edge of the taper is, for example, 1: 2.
referring to fig. 3, on the basis of the above embodiments, the nano buffer layer 1402 in this embodiment may be, for example, a gallium nitride nanocrystal or an aluminum gallium nitride nanocrystal.
Referring to fig. 3, in other embodiments, the nano buffer layer 1402 may be disposed between the semiconductor substrate 1400 and the buffer layer, between the multiple buffer layers, and between the buffer layer and the barrier layer 1404, and the nano buffer layer 1402 provides nucleation points for the growth of the subsequent growth layer, which is beneficial to improving the film-forming quality of the subsequent growth layer.
Referring to fig. 3, based on the above embodiment, in the present embodiment, the source 704 and the drain 706 are composed of a third metal layer, and the third metal layer sequentially includes a first titanium metal layer, an aluminum metal layer, a second titanium metal layer, and a titanium nitride layer. The gate 707 is composed of a fourth metal layer, which is nickel or gold alloy.
Referring to fig. 3, the present invention can grow the first buffer layer 1401 and the post-treatment layer 1402 by PVD, so as to obtain the first buffer layer 1401 with better quality, which facilitates the preparation and application of the subsequent gallium nitride-based semiconductor device.
Referring to fig. 4, the present embodiment further provides a method for manufacturing a semiconductor device, which includes the following steps:
in step S701, an oxide layer on the surface of the semiconductor substrate 1400 is treated with, for example, a hydrofluoric acid solution, and then a first buffer layer 1401, for example, a single-layer aluminum nitride buffer layer, is deposited by a PVD process, with a thickness range of, for example, 10-300 nm.
In step S702, a molecular beam epitaxy process is used to prepare a nano buffer layer 1402, such as a gan nano buffer layer 1402, a substrate and several molecular beam source furnaces are placed in an ultra-high vacuum system, and various elements constituting a compound, such as Ga, N and dopant, are respectively placed in different injection furnaces to be heated and cracked and ionized in the different source furnaces, so that their molecules or atoms are injected onto the surface of the heated substrate at a certain thermal motion speed and a certain proportional intensity of beam current, and the molecules or atoms interact with the surface and perform single crystal film growth. The growth rate of the single crystal thin film is, for example, 0.01 to 1 μm/h, and the growth temperature is, for example, 500-.
In step S703, a second buffer layer 1403, such as a gan buffer layer, is prepared on the nano buffer layer 1402 by a PVD process, and the preparation of the gan buffer layer can be achieved by the aforementioned two-step method.
In step S704, a barrier layer 1404, such as a gallium nitride layer, is grown by PVD process, and a gallium nitride layer 50, such as a gallium nitride layer with a thickness of 50-500nm, is grown on the gallium nitride buffer layer at a controlled temperature of 950-1100 ℃ and a controlled pressure of 70-200 torr, for example.
In step S705, a layer of hafnium oxide (HfO2) may then be deposited on the surface of the gan-based epitaxial wafer by using a plasma enhanced chemical vapor deposition (pecvd) method to form the dielectric layer 705. The thickness of the hafnium oxide may be 2000 angstroms, for example.
In step S706, the dielectric layer 705 is dry etched to form a source 704 contact hole and a drain 706 contact hole that are oppositely disposed.
In step S707, a first metal is deposited in the source 704 contact hole and the drain 706 contact hole, and on the surface of the dielectric layer 705. Specifically, a magnetron sputtering coating process may be adopted to sequentially deposit a first titanium metal layer, an aluminum metal layer, a second titanium metal layer and a titanium nitride layer in the contact hole of the source 704 and the contact hole of the drain 706 and on the surface of the dielectric layer 705 to form the first metal layer, where the thickness of the first titanium metal layer may be, for example, 200 angstroms, the thickness of the aluminum metal layer may be, for example, 1200 angstroms, the thickness of the second titanium metal layer may be, for example, 200 angstroms, and the thickness of the titanium nitride layer may be, for example, 200 angstroms. The first metal is then patterned and etched to expose a portion of the surface of dielectric layer 705. Wherein the photolithography process comprises gumming, exposing and developing. Thus, the first metal layer over the contact hole of the source 704 forms the source 704 of the device, and the first metal layer over the contact hole of the drain 706 forms the drain 706 of the device.
In step S708, the exposed surface of the dielectric layer 705 and the gan layer are dry etched to form a contact hole 707 for the gate. The contact hole of the gate 707 completely penetrates through the dielectric layer 705 and penetrates through the gallium nitride layer to reach the bottom of the gallium nitride layer, the gate 707 is in a conical structure, and the ratio of the upper edge to the lower edge of the conical structure is 1: 2-1: 4.
in step S709, a magnetron sputtering coating process is used to deposit a silicon nitride layer in the contact hole of the gate 707, the silicon nitride layer is not higher than the contact hole of the gate 707, and then Ni/Au is deposited on the silicon nitride layer and on the outer edge of the contact hole of the gate 707 as a second metal with a metal thickness of 0.01-0.04 μm/0.08-0.4 μm, thereby forming the gate 707. Thus, the gate 707 is a composite structure having multiple materials.
Referring to fig. 5, the present invention further provides a semiconductor device based on a gan epitaxial layer, including: the semiconductor device comprises a semiconductor substrate 1400, a first buffer layer 1401, a nano buffer layer 1402, a second buffer layer 1403, a barrier layer 1404, a passivation layer 803, a first anode contact hole 813, a first anode 804, a dielectric layer 805, a second anode contact hole 814, a second anode 806, a cathode contact hole 815, a cathode 807, a protective layer 808, a field plate layer 809, an anode opening 816, anode conducting metal 810, a cathode opening 817 and cathode conducting metal 811.
Referring to fig. 5, a first buffer layer 1401 is disposed on a semiconductor substrate 1400, wherein the first buffer layer 1401 may be, for example, an aluminum nitride layer, and the thickness of the first buffer layer 1401 is, for example, 10nm to 300 nm. The nano-buffer layer 1402 is disposed on a side of the first buffer layer 1401 remote from the semiconductor substrate 1400. The second buffer layer 1403 is disposed on a side of the nano buffer layer 1402 away from the first buffer layer 1401, and the second buffer layer 1403 may be, for example, a gallium nitride or aluminum gallium nitride layer. The barrier layer 1404 is disposed on a side of the second buffer layer 1403 remote from the nano-buffer layer 1402, and the passivation layer 803 is disposed on a side of the barrier layer 1404 remote from the second buffer layer 1403. A first anode contact hole 813 extends through the passivation layer 803 into the barrier layer 1404 and a dielectric layer 805 is disposed on the side of the passivation layer 803 remote from the barrier layer 1404 and within the first anode contact hole 813. The second anode contact hole 814 extends through the dielectric layer 805, the passivation layer 803, and into the barrier layer 1404. The first anode 804 and the second anode 806 include a first metal layer disposed on a side of the dielectric layer 805 away from the passivation layer 803 and extending into the first anode contact hole 813 and the second anode contact hole 814 to cover the bottom of the dielectric layer 805 and the second anode contact hole 814 at the bottom of the first anode contact hole 813, and a second metal layer disposed on the first metal layer and filling the first anode contact hole 813 and the second anode contact hole 814. The cathode contact hole 815 penetrates the dielectric layer 805 and the passivation layer 803. Cathode 807 is disposed on dielectric layer 805 and fills cathode contact hole 815. A protective layer 808 is disposed over the anode, cathode 807 and dielectric layer 805. An anode opening 816 extends through the protective layer 808 to expose the anode. A cathode opening 817 extends through protective layer 808 to expose cathode 807. The anode via metal 810 is disposed on a side of the passivation layer 808 away from the dielectric layer 805, and the anode via metal 810 fills the anode opening 816. Cathode via metal 811 is disposed on a side of the passivation layer 808 away from the dielectric layer 805, and the cathode via metal 811 fills the cathode opening 817. A field plate layer 809 is disposed on the protective layer 808 in a region between the anode conductive metal 810 and the cathode conductive metal 811 and connected to the anode conductive metal 810, wherein the anode conductive metal 810, the cathode conductive metal 811, and the field plate layer 809 may be formed simultaneously by an etching process.
Referring to fig. 5, on the basis of the above embodiments, the nano buffer layer 1402 in this embodiment may be, for example, a gallium nitride nanocrystal or an aluminum gallium nitride nanocrystal.
Referring to fig. 5, in other embodiments, the nano buffer layer 1402 may be disposed between the semiconductor substrate 1400 and the buffer layer, between the multiple buffer layers, and between the buffer layer and the barrier layer 1404, and the nano buffer layer 1402 provides nucleation points for the growth of the subsequent growth layer, which is beneficial to improving the film-forming quality of the subsequent growth layer.
Referring to fig. 6, the present invention further provides a method for manufacturing a semiconductor device, including the following steps:
in step S801, a surface oxide layer of the semiconductor substrate 1400 is treated with, for example, a hydrofluoric acid solution, and then a first buffer layer 1401, for example, a single-layer aluminum nitride buffer layer, is deposited by a PVD process, with a thickness interval of, for example, 10-300 nm.
In step S802, a molecular beam epitaxy process is used to prepare a nano buffer layer 1402, such as a gan nano buffer layer 1402, a substrate and several molecular beam source furnaces are placed in an ultra-high vacuum system, and various elements constituting a compound, such as Ga, N and a dopant, are respectively placed in different injection furnaces to be heated and cracked and ionized in the different source furnaces, so that their molecules or atoms are injected onto the surface of the heated substrate at a certain thermal motion speed and a certain proportional intensity of beam current, and the molecules or atoms interact with the surface of the heated substrate, and a single crystal film is grown. The growth rate of the single crystal thin film is, for example, 0.01 to 1 μm/h, and the growth temperature is, for example, 500-.
In step S803, a second buffer layer 1403, such as a gallium nitride buffer layer, is prepared on the nano buffer layer 1402 by a PVD process, and the preparation of the gallium nitride buffer layer can be achieved by the aforementioned two-step method.
In step S804, the barrier layer 1404, such as a gallium nitride layer, is grown by PVD process, and the gallium nitride layer 50 is grown on the gallium nitride buffer layer at a temperature of, for example, 950 ℃ to 1100 ℃ and a pressure of, for example, 70torr to 200torr, wherein the thickness of the gallium nitride layer is, for example, 50nm to 500 nm.
In step S805, a silicon nitride passivation layer 803 is deposited on the aluminum gallium nitride barrier layer 1404 using, but not limited to, a chemical vapor deposition process.
In step S806, the silicon nitride passivation layer 803 and the aluminum gallium nitride barrier layer 1404 are patterned to form a first anode contact hole 813, wherein the first anode contact hole 813 penetrates through the silicon nitride passivation layer 803 and extends into the aluminum gallium nitride barrier layer 1404.
In step S807, a dielectric layer 805 is formed on the silicon nitride passivation layer 803 and within the first anode contact hole 813, and the dielectric layer 805, the silicon nitride passivation layer 803, and the aluminum gallium nitride barrier layer 1404 are patterned to form a second anode contact hole 814 extending through the dielectric layer 805, the silicon nitride passivation layer 803, and into the aluminum gallium nitride barrier layer 1404.
In step S808, a metal layer is formed on the dielectric layer 805 and in the second anode contact hole 814, and the metal layer is patterned to obtain a first metal layer located in the first anode contact hole 813 and the second anode contact hole 814. The anode region AZ includes a first anode contact hole 813 and a second anode contact hole 814.
In step S809, the dielectric layer 805 and the silicon nitride passivation layer 803 are patterned to form a cathode contact hole 815 penetrating the dielectric layer 805 and the silicon nitride passivation layer 803.
In step S810, a second metal layer is formed on the dielectric layer 805 and the first metal layer located in the anode region AZ and within the cathode contact hole 815, and the second metal layer is patterned to obtain a second metal layer of the anode and the cathode 807. Wherein cathode 807 fills cathode contact hole 815.
In step S811, a protective layer 808 is formed on the dielectric layer 805, the first anode 804, the second anode 806, and the cathode 807.
In step S812, the passivation layer 808 is patterned to form an anode opening 816 and a cathode opening 817 through the passivation layer 808 exposing the first anode 804, the second anode 806, and the cathode 807, respectively.
In step S813, a third metal layer is formed on the protective layer 808 and within the anode opening 816 and the cathode opening 817, and patterned to form a field plate layer 809, an anode via metal 810 filling the anode opening 816, and a cathode via metal 811 filling the cathode opening 817. Wherein the field plate layer 809 is located at a region between the anode conductive metal 810 and the cathode conductive metal 811 and outside the anode region AZ, and is connected to the anode conductive metal 810.
The preferred embodiments of the present invention disclosed above are intended only to help illustrate the present invention. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best understand the invention for and utilize the invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims (10)

1. A semiconductor device, comprising:
a semiconductor substrate;
a first buffer layer disposed on the semiconductor substrate;
the nanometer buffer layer is arranged on one side of the first buffer layer far away from the semiconductor substrate;
the second buffer layer is arranged on one side, far away from the first buffer layer, of the nanometer buffer layer;
the barrier layer is arranged on one side of the second buffer layer far away from the nanometer buffer layer;
the dielectric layer is arranged on one side, far away from the second buffer layer, of the barrier layer;
the source electrode penetrates through the dielectric layer and extends into the barrier layer;
the drain electrode penetrates through the dielectric layer and extends into the barrier layer;
the grid electrode penetrates through the dielectric layer and extends into the barrier layer, one part of the grid electrode protrudes out of the top of the dielectric layer, the grid electrode is of a conical structure, and the ratio of the upper edge to the lower edge of the conical structure is 1: 2-1: 4.
2. the semiconductor device of claim 1, wherein the nano buffer layer is a gallium nitride nano crystal layer.
3. The semiconductor device according to claim 1, wherein the barrier layer has a wider band gap than that of the second buffer layer.
4. The semiconductor device of claim 1, wherein a portion of the source protrudes above the top of the dielectric layer.
5. The semiconductor device of claim 1, wherein a portion of the drain protrudes above the top of the dielectric layer.
6. The semiconductor device of claim 1, wherein a portion of the gate protrudes above the top of the dielectric layer.
7. The semiconductor device of claim 1, wherein the gate extends through the dielectric layer and into the bottom of the barrier layer.
8. An epitaxial layer of gallium nitride, comprising:
a semiconductor substrate;
a first buffer layer disposed on the semiconductor substrate;
the nanometer buffer layer is arranged on one side of the first buffer layer far away from the semiconductor substrate;
the second buffer layer is arranged on one side, far away from the first buffer layer, of the nanometer buffer layer;
a barrier layer disposed on a side of the second buffer layer distal from the nano-buffer layer.
9. The epitaxial layer of gallium nitride according to claim 8, wherein the nano-buffer layer is a nano-crystalline layer of gallium nitride.
10. The epitaxial layer of gallium nitride according to claim 8, wherein the thickness of the nano-buffer layer is 0.5-2 nm.
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