CN110620158A - Gallium nitride epitaxial layer, semiconductor device and preparation method of semiconductor device - Google Patents

Gallium nitride epitaxial layer, semiconductor device and preparation method of semiconductor device Download PDF

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CN110620158A
CN110620158A CN201910914006.2A CN201910914006A CN110620158A CN 110620158 A CN110620158 A CN 110620158A CN 201910914006 A CN201910914006 A CN 201910914006A CN 110620158 A CN110620158 A CN 110620158A
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layer
anode
metal
cathode
contact hole
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林信南
刘美华
刘岩军
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Shenzhen Crystal Phase Technology Co Ltd
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Shenzhen Crystal Phase Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • H01L29/66204—Diodes
    • H01L29/66212—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

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Abstract

The invention discloses a gallium nitride epitaxial layer, a semiconductor device and a preparation method of the semiconductor device, and relates to the technical field of semiconductors. The semiconductor device of the present invention includes: the semiconductor device comprises a semiconductor substrate, a first buffer layer, a post-processing layer and a second buffer layer; the field plate comprises a barrier layer, a passivation layer, a first anode contact hole, a first anode, a dielectric layer, a second anode contact hole, a second anode, a cathode contact hole, a cathode, a protective layer, an anode opening hole, anode conducting metal, a cathode opening hole, cathode conducting metal and a field plate layer. The invention solves the problem that when the buffer layer is a layer, leakage current exists between the buffer layer and the interface of the semiconductor substrate.

Description

Gallium nitride epitaxial layer, semiconductor device and preparation method of semiconductor device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a gallium nitride epitaxial layer, a semiconductor device and a preparation method of the semiconductor device.
Background
A semiconductor device is a semiconductor device made by contacting a semiconductor layer with a metal. Compared with the traditional semiconductor diode, the semiconductor diode has the characteristic of extremely short reverse recovery time, so that the semiconductor device is widely applied to circuits such as a switching power supply, a frequency converter, a driver and the like. The gallium nitride material is a third generation wide bandgap semiconductor material, and has the characteristics of large bandgap width, high electronic saturation rate, high breakdown electric field, high thermal conductivity, corrosion resistance, radiation resistance and the like, so that the gallium nitride material becomes an optimal material for manufacturing short-wave photoelectronic devices and high-voltage high-frequency high-power devices. In conclusion, the semiconductor device prepared by using the gallium nitride material combines the advantages of the semiconductor device and the gallium nitride material, has the advantages of high switching speed, high field intensity, good thermal performance and the like, and has good development prospect in the market of power rectifiers.
However, in the conventional semiconductor device structure, a large number of defects exist in the barrier layer due to lattice mismatch between the substrate and the barrier layer, so that the performance and the service life of the semiconductor device are affected. In the prior art, a buffer layer is often formed between a semiconductor substrate and a barrier layer to offset the influence caused by partial lattice mismatch, but the buffer layer has a limited function and cannot completely offset the influence caused by lattice mismatch, and a leakage current problem exists between the buffer layer and the interface of the semiconductor substrate, so that the performance and the service life of a semiconductor device cannot be fully improved.
Disclosure of Invention
The invention aims to provide a gallium nitride epitaxial layer, a semiconductor device and a preparation method of the semiconductor device.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the present invention provides a semiconductor device, which includes:
a semiconductor substrate;
a first buffer layer disposed on the semiconductor substrate;
the post-processing layer is arranged on one side, far away from the semiconductor substrate, of the first buffer layer;
the second buffer layer is arranged on one side, far away from the first buffer layer, of the post-treatment layer;
a barrier layer disposed on a side of the second buffer layer away from the post-treatment layer;
a passivation layer disposed on a side of the barrier layer away from the second buffer layer;
a first anode contact hole penetrating the passivation layer into the barrier layer;
a first anode disposed within the first anode contact hole;
the dielectric layer is arranged on one side of the passivation layer far away from the barrier layer and between the first anode and the barrier layer;
the second anode contact hole penetrates through the dielectric layer and the passivation layer and extends into the barrier layer;
a second anode disposed within the second anode contact hole;
a cathode contact hole penetrating the dielectric layer and the passivation layer;
the cathode is arranged on the dielectric layer and in the cathode contact hole;
a protective layer disposed over the first anode, the second anode, the cathode, and the dielectric layer;
an anode opening through the protective layer to expose the first anode and the second anode;
the anode conducting metal is arranged on one side of the protective layer, which is far away from the dielectric layer, and is connected with the first anode and the second anode;
a cathode opening through the protective layer to expose the cathode;
the cathode conducting metal is arranged on one side, far away from the dielectric layer, of the protective layer, and the cathode conducting metal is connected with the cathode;
a field plate layer disposed on the protective layer, the field plate layer being connected with the anode conductive metal, wherein the anode conductive metal, the cathode conductive metal, and the field plate layer are formed simultaneously.
In one embodiment of the present invention, the first anode and the second anode comprise a first metal layer and a second metal layer, wherein the first metal layer is disposed on a side of the dielectric layer away from the passivation layer and extends into the first anode contact hole and the second anode contact hole to cover the dielectric layer at the bottom of the first anode contact hole and the bottom of the second anode contact hole, and the second metal layer is disposed on the first metal layer and fills the first anode contact hole and the second anode contact hole.
In one embodiment of the invention, the first and second anodes are comprised of a first number of metal layers stacked, the cathode is comprised of a second number of metal layers stacked, and the first number is greater than the second number.
The present invention also provides a gallium nitride epitaxial layer comprising:
a semiconductor substrate;
a first buffer layer disposed on the semiconductor substrate;
the post-processing layer is arranged on one side, far away from the semiconductor substrate, of the first buffer layer;
the second buffer layer is arranged on one side, far away from the first buffer layer, of the post-treatment layer;
a barrier layer disposed on a side of the second buffer layer away from the post-treatment layer.
In one embodiment of the present invention, the first buffer layer is an aluminum nitride layer.
In one embodiment of the invention, the thickness of the first buffer layer is 10-300 nm.
In one embodiment of the invention, the post-treatment layer is an aluminum oxide layer.
In one embodiment of the invention, the thickness of the post-treatment layer is 0.5-2 nm.
The invention also provides a preparation method of the semiconductor device, which is characterized by at least comprising the following steps:
forming a first buffer layer on a substrate by using a Physical Vapor Deposition (PVD) process;
forming a post-treatment layer on the first buffer layer using an atomic deposition technology (ALD) process;
forming a second buffer layer on the post-treatment layer by using a Physical Vapor Deposition (PVD) process;
forming a barrier layer on the second buffer layer;
forming a passivation layer on the barrier layer;
forming a first anode contact hole in the passivation layer and the barrier layer, wherein the first anode contact hole penetrates through the passivation layer and extends into the barrier layer;
forming a dielectric layer on the passivation layer and in the first anode contact hole, and patterning the dielectric layer, the passivation layer and the barrier layer to form a second anode contact hole penetrating through the dielectric layer and the passivation layer and extending into the barrier layer;
forming a first metal layer of an anode in the dielectric layer and the second anode contact hole;
forming a cathode contact hole penetrating through the dielectric layer and the passivation layer on the dielectric layer and the passivation layer;
forming a second metal layer of an anode on the dielectric layer and the first metal layer of the anode and in the cathode contact hole, thereby obtaining a first anode and a second anode comprising the first metal layer and the second metal layer and a cathode comprising the second metal layer;
forming a protective layer on the dielectric layer, the first anode, the second anode and the cathode;
patterning the protective layer to form a field plate layer, the field plate layer being connected to the first anode and the second anode.
In one embodiment of the invention, the post-treatment layer is an aluminum oxide layer.
According to the invention, the first buffer layer and the post-treatment layer are grown through PVD (physical vapor deposition), so that the first buffer layer with better quality is obtained, and the subsequent preparation and application of the gallium nitride-based semiconductor device are facilitated. When the buffer layer is of a multilayer structure, lattice constants of different layers are gradually changed, the lattice constant near the surface of the semiconductor substrate is closest to the lattice constant of the semiconductor substrate, and the lattice constant of the top layer is closest to the lattice constant of a subsequently formed barrier layer, so that lattice defects caused by the lattice constant of the semiconductor substrate in the buffer layer can be reduced, the interface state on the interface between the buffer layer and the semiconductor substrate is reduced, and the interface leakage current on the interface is reduced. The invention increases the area of the anode and greatly reduces the reverse leakage by arranging the dielectric layer, and the dielectric layer can be formed with the grid dielectric layer of a GaN HEMT (High Electron Mobility Transistor) at the same time and is compatible with a CMOS process line. In addition, the invention expands the depletion region of the semiconductor device by adding the anode conducting metal, the cathode conducting metal and the field plate layer structure, thereby improving the voltage resistance of the semiconductor device.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1-1 is a schematic view of a GaN epitaxial layer according to the present invention;
FIG. 1-2 is a flow chart of a method for preparing an epitaxial layer of gallium nitride of FIG. 1-1;
FIG. 2-1 is a schematic view of another GaN epitaxial layer according to the invention;
FIG. 2-2 is a flow chart of a method for fabricating the GaN epitaxial layer of FIG. 2-1;
FIG. 3-1 is a schematic view of another GaN epitaxial layer according to the invention;
FIG. 3-2 is a flow chart of a method for preparing the GaN epitaxial layer of FIG. 3-1;
FIG. 4-1 is a schematic view of another GaN epitaxial layer according to the invention;
FIG. 4-2 is a flow chart of a method for fabricating the GaN epitaxial layer of FIG. 4-1;
FIG. 5-1 is a schematic view of a semiconductor device obtained by using the gallium nitride epitaxial layer of FIG. 1-1;
FIG. 5-2 is a flow chart of a method of fabricating the semiconductor device of FIG. 5-1;
fig. 6-1 is a schematic structural view of another semiconductor device obtained by using the gallium nitride epitaxial layer of fig. 1-1;
FIG. 6-2 is a flow chart of a method of fabricating the semiconductor device of FIG. 6-1;
fig. 7-1 is a schematic structural view of a semiconductor device obtained by using the gallium nitride epitaxial layer of fig. 2-1;
FIG. 7-2 is a flow chart of a method of fabricating the semiconductor device of FIG. 7-1;
fig. 8-1 is a schematic structural view of another semiconductor device obtained by using the gallium nitride epitaxial layer of fig. 2-1;
FIG. 8-2 is a flow chart of a method of fabricating the semiconductor device of FIG. 8-1;
fig. 9-1 is a schematic structural view of a semiconductor device obtained by using the gallium nitride epitaxial layer of fig. 3-1;
FIG. 9-2 is a flow chart of a method of fabricating the semiconductor device of FIG. 9-1;
fig. 10-1 is a schematic structural view of another semiconductor device obtained by using the gallium nitride epitaxial layer of fig. 3-1;
FIG. 10-2 is a flow chart of a method of fabricating the semiconductor device of FIG. 10-1;
FIG. 11-1 is a schematic view of a semiconductor device obtained using the gallium nitride epitaxial layer of FIG. 4-1;
fig. 11-2 is a flow chart of a method of fabricating the semiconductor device of fig. 11-1.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Gallium nitride materials have low heat generation rates and high breakdown electric fields, and are important materials for developing high-temperature high-power electronic devices and high-frequency microwave devices. The gallium nitride material can be used for preparing novel devices such as metal field effect transistors (MESFETs), Heterojunction Field Effect Transistors (HFETs), modulation-doped field effect transistors (MODFETs) and the like. The modulation doped AlGaN/GaN structure has high electron mobility (2000 cm)2The dielectric constant is lower, the material is the priority material for manufacturing microwave devices, gallium nitride has wider forbidden bandwidth (3.4eV) and materials such as sapphire, silicon carbide and the like are used as substrates, the heat dissipation performance is good, and the device can work under the condition of high power.
The gallium nitride epitaxial layer and the semiconductor device provided by the invention can be applied to power semiconductor devices and radio frequency semiconductor devices.
Referring to fig. 1-1, the present invention provides an epitaxial layer of gallium nitride, comprising: semiconductor substrate 1100, buffer layer 1101, barrier layer 1102. Wherein a buffer layer 1101 is provided on the semiconductor substrate 1100 and a barrier layer 1102 is provided on a side of the buffer layer 1101 facing away from the semiconductor substrate 1100. Wherein the material of the semiconductor substrate 1100 is, for example, one of sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, aluminum nitride or gallium nitride, and the material of the buffer layer 1101 may be one or more of aluminum oxide, hafnium oxide, titanium nitride, aluminum gallium nitride or gallium nitride. When the buffer layer 1101 is a multilayer structure, lattice constants of different layers gradually change, and the lattice constant near the surface of the semiconductor substrate 1100 is closest to the lattice constant of the semiconductor substrate 1100, and the lattice constant of the top layer is closest to the lattice constant of the subsequently formed barrier layer 1102, so that lattice defects in the buffer layer due to the lattice constant of the semiconductor substrate 1100 can be reduced, the interface state at the interface between the buffer layer and the semiconductor substrate 1100 can be reduced, and the interface leakage current at the interface can be reduced. The barrier layer 1102 material may be, for example, one of aluminum gallium nitride or gallium nitride.
Referring to fig. 1-2, the method for preparing the gan epitaxial layer of the present embodiment at least includes the following steps:
in step S1100, a buffer layer 1101 is grown on the semiconductor substrate 1100 using an epitaxial growth process, and then in step S1101, a barrier layer 1102 is grown on the buffer layer 1101 using an epitaxial growth process.
Referring to fig. 2-1, in another embodiment of the present invention, an epitaxial layer of gallium nitride may further include: a semiconductor substrate 1200, a first buffer layer 1201, a second buffer layer 1202, a third buffer layer 1203, and a barrier layer 1204.
Wherein a first buffer layer 1201 is disposed on the semiconductor substrate 1200. The second buffer layer 1202 is provided on a side of the first buffer layer 1201 away from the semiconductor substrate 1200, and the third buffer layer 1203 is provided on a side of the second buffer layer 1202 away from the first buffer layer 1201. The barrier layer 1204 is provided on a side of the third buffer layer 1203 remote from the second buffer layer 1202. On the basis of the above embodiments, the first buffer layer 1201 in this embodiment may be, for example, an aluminum nitride layer, the thickness of the first buffer layer 1201 is, for example, 10nm to 300nm, the second buffer layer 1202 may be, for example, a gallium nitride or aluminum gallium nitride layer, and the third buffer layer 1203 may be, for example, a gallium nitride layer. The materials used for the first buffer layer 1201, the second buffer layer 1202, and the third buffer layer 1203 may be selected adaptively according to, for example, the semiconductor substrate material and the material used for the barrier layer.
Referring to fig. 2-2, the method for preparing the gan epitaxial layer of the present embodiment at least includes the following steps:
in step S1200, a first buffer layer 1201, for example, an aluminum nitride buffer layer, is grown on a semiconductor substrate 1200, for example, a silicon substrate or a silicon carbide substrate, using an epitaxial growth process. In step S1201, a second buffer layer 1202, for example, a gallium nitride buffer layer, is grown on the first buffer layer 1201 using an epitaxial growth process. In step S1202, a third buffer layer 1203, for example, an aluminum gallium nitride buffer layer, is grown on the second buffer layer 1202 using an epitaxial growth process. In step S1203, an aluminum gallium nitride barrier layer 1204 is grown on the third buffer layer 1203 using an epitaxial growth process.
Referring to fig. 3-1, in another embodiment of the present invention, an epitaxial layer of gallium nitride may further include: the semiconductor device includes a semiconductor substrate 1300, a first buffer layer 1301, a post-treatment layer 1302, a second buffer layer 1303, and a barrier layer 1304.
The first buffer layer 1301 is disposed on the semiconductor substrate 1300, the post-processing layer 1302 is disposed on a side of the first buffer layer 1301 away from the semiconductor substrate 1300, the second buffer layer 1303 is disposed on a side of the post-processing layer 1302 away from the first buffer layer 1301, and the barrier layer 1304 is disposed on a side of the second buffer layer 1303 away from the post-processing layer 1302. The material of the semiconductor substrate 1300 is, for example, one of sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, aluminum nitride, or gallium nitride. The first buffer layer 1301 may be, for example, an aluminum nitride layer, and the thickness of the first buffer layer 1301 is, for example, 10nm to 300 nm. The post-treatment layer 1302 may be, for example, a thin layer of aluminum oxide (Al2O3), and the post-treatment layer 1302 may have a thickness of 0.5-2 nm. The second buffer layer 1303 may be, for example, a gallium nitride layer or an aluminum gallium nitride layer. The material of the barrier layer 1304 is, for example, a gallium nitride layer or an aluminum gallium nitride layer. According to the invention, the first buffer layer 1301 and the post-processing layer 1302 are grown through PVD, so that the first buffer layer 1301 with better quality is obtained, and the subsequent preparation and application of the gallium nitride-based semiconductor device are facilitated.
Referring to fig. 3-2, a method for fabricating a gan epitaxial wafer according to the present embodiment includes the following steps:
in step S1301, a material of the semiconductor substrate 1300 is, for example, one of sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, aluminum nitride, or gallium nitride, and a hydrofluoric acid solution is used to treat and remove the semiconductorThe method comprises the steps of oxidizing an oxide layer on the surface of a bulk substrate 1300, depositing a first buffer layer 1301, such as a single-layer aluminum nitride buffer layer, with a thickness of 10-50nm, on a tray made of SiC, placing the epitaxial semiconductor substrate 1300 (for example, a Si substrate is used here) on the tray, placing the tray on a PVD sputtering machine, and transferring the tray to a machine deposition chamber. After the semiconductor substrate 1300 is placed, the deposition chamber is evacuated, and the semiconductor substrate 1300 is heated while the chamber is evacuated. Background vacuum is drawn below, for example, 10-5-10-7The temperature is stabilized at 400 to 600 ℃ for Torr, and the semiconductor substrate 1300 is baked for 1 to 10 minutes, for example. After the semiconductor substrate 1300 is baked, Ar, N2, O2, Ar: the flow ratio of N2 is, for example, 10:2 to 1:1, and the flow ratio of O2 is, for example, 0to 5% of the sum of the flows of Ar and N2. The total gas flow is preferably maintained at a PVD deposition chamber pressure of, for example, 2-8 mTorr. Meanwhile, the heating temperature of the semiconductor substrate 1300 is set to the deposition temperature, and the deposition temperature is preferably within a range of 400 to 600 ℃. And introducing reaction gas, enabling the deposition temperature to be stable for 10-60 seconds, and then turning on a sputtering power supply to sputter the Al target, wherein the AlN crystal film doped with O is deposited on the semiconductor substrate 1300. The sputtering power can be set, for example, to 1KW to 10KW depending on the requirement of the deposition rate, and the sputtering time can be set, for example, to 10 seconds to 1000 seconds depending on the thickness.
In step S1302, further, an ALD process is employed to prepare a post-treatment layer 1302, such as Al2O3The layer, ALD chamber, is evacuated to, for example, 0.05MPa to 0.5MPa, the temperature is raised to, for example, 100 ℃, the precursors are trimethylaluminum and high purity water, the deposition thickness is, for example, 0.5 to 2nm, and the deposition time is, for example, 3 to 25 min.
In step S1303, a second buffer layer 1303, such as a gan buffer layer, is further prepared on the post-processing layer 1302, wherein the preparation of the gan buffer layer can be realized by a two-step method, the temperature is controlled at 450-600 ℃, the pressure is controlled at 200-500torr, a gan nucleation layer is grown, and then the temperature is raised to 950-1200 ℃ to grow a three-dimensional and two-dimensional gan cladding layer, wherein the nucleation layer and the subsequent three-dimensional two-dimensional gan buffer layer are collectively referred to as gan buffer layer.
In step S1304, a barrier layer 1304, such as a gan barrier layer 1304, is grown in the last step, wherein the gan barrier layer 1304 is grown on the gan buffer layer at a temperature of 950 ℃ to 1100 ℃ and a pressure of 70torr to 200torr, and the thickness of the gan barrier layer 1304 is 50nm to 500nm, for example.
And cooling after the epitaxy is finished to obtain the gallium nitride epitaxial layer.
The control of the temperature and the pressure refers to the control of the temperature and the pressure in a reaction chamber for growing the epitaxial wafer, and specifically relates to a reaction chamber of Metal Organic Chemical Vapor Deposition (MOCVD) equipment. During implementation, trimethyl gallium or triethyl gallium is used as a gallium source, high-purity ammonia gas is used as a nitrogen source, trimethyl indium is used as an indium source, trimethyl aluminum is used as an aluminum source, silane is used as a silicon source, tetramethyl germanium is used as a germanium source, and cyclopentadienyl magnesium is used as a magnesium source.
Referring to fig. 4-1, in another embodiment of the present invention, an epitaxial layer of gallium nitride may further include: a semiconductor substrate 1400, a first buffer layer 1401, a nano-buffer layer 1402, a second buffer layer 1403, and a barrier layer 1404.
In which a first buffer layer 1401 is disposed on a semiconductor substrate 1400, the first buffer layer 1401 may be, for example, an aluminum nitride layer, and the thickness of the first buffer layer 1401 is, for example, 10nm to 300 nm. The nano-buffer layer 1402 is disposed on a side of the first buffer layer 1401 remote from the semiconductor substrate 1400. The second buffer layer 1403 is disposed on a side of the nano buffer layer 1402 away from the first buffer layer 1401, and the second buffer layer 1403 may be, for example, a gallium nitride or aluminum gallium nitride layer. The barrier layer 1400 is disposed on a side of the second buffer layer 1403 remote from the nanolayer 1402. The nano buffer layer 1402 may be, for example, a gallium nitride nanocrystal or an aluminum gallium nitride nanocrystal.
Referring to fig. 4-2, the present embodiment further provides a method for fabricating a gan-based epitaxial wafer, which includes the following steps: in step S1401, a first buffer layer 1401 is grown over a semiconductor substrate; in step S1402, a molecular beam epitaxy process is used to prepare a nano buffer layer 1402, such as a gan nano buffer layer 1402, on the first buffer layer, a substrate and several molecular beam source furnaces are placed in an ultra-high vacuum system, and various elements constituting a compound, such as Ga, N and dopant, are respectively placed in different injection furnaces to be heated and cracked and ionized in the different source furnaces, so that their molecules or atoms are injected onto the surface of the heated substrate at a certain thermal motion rate and a certain proportional intensity of beam current, and the molecules or atoms interact with the surface, and a single crystal film is grown. The growth rate of the single crystal thin film is, for example, 0.01 to 1 μm/h, and the growth temperature is, for example, 500-. In step S1403, further, a second buffer layer 1403, such as a gallium nitride buffer layer, is prepared on the nano buffer layer 1402 by using a PVD process, and the gallium nitride buffer layer can also be prepared by the two-step method of the above embodiment. In step S1404, a barrier layer 1404 is grown on the second buffer layer 1403. And cooling after the epitaxy is finished to obtain the gallium nitride epitaxial wafer layer.
Referring to fig. 5-1, the present invention further provides a semiconductor device based on gan epitaxial layer, for example, comprising: semiconductor substrate 1100, buffer layer 1101, barrier layer 1102, passivation layer 103, anode 104, cathode 107, protective layer 108, field plate layer 109, anode conduction metal 110, and cathode conduction metal 111.
Referring to fig. 5-1, a buffer layer 1101 is disposed on a semiconductor substrate 1100, a barrier layer 1102 is disposed on a side of the buffer layer 1101 away from the semiconductor substrate 1100, and a passivation layer 103 is disposed on a side of the barrier layer 1102 away from the buffer layer 1101. The anode electrode 104 extends through the passivation layer 1103 into the barrier layer 1102, and the cathode electrode 107 is connected to the barrier layer 1102 through the passivation layer 1103. The protective layer 108 is provided on the anode 104 and the cathode 107. A field plate layer 109 is disposed on the protective layer 108, the field plate layer 109 being located between the anode 104 and the cathode 107. An anode conductive metal 110 is disposed on the field plate layer 109 in communication with the anode 104, and a cathode conductive metal 111 is disposed on the field plate layer 109 in communication with the cathode 107. The anode 104 and the cathode 107 may include a multi-layer metal layer structure including, but not limited to, a titanium metal layer, a metal aluminum layer, a metal titanium layer, and a metal titanium nitride layer. The protection layer 108 may be, for example, a tetraethylorthosilicate (PETEOS) oxide layer, the anode conductive metal 110 and the cathode conductive metal 111 may be formed simultaneously with the field plate layer 109, and the constituent material is, for example, copper aluminum silicon (AlSiCu).
In this embodiment, the buffer layer 1101 is provided to reduce lattice defects of the barrier layer 1102 due to the lattice constant of the semiconductor substrate 1100, reduce the interface state at the interface between the barrier layer 1102 and the semiconductor substrate 1100, and reduce the interface leakage current at the interface. The anode conducting metal 110, the cathode conducting metal 111 and the field plate layer 109 structure balance electric field distribution, reduce electric field intensity of the main Schottky junction and improve pressure resistance of the semiconductor device.
Referring to fig. 5-2, the present invention further provides a method for manufacturing a semiconductor device, which comprises the following steps:
in step S101, an epitaxial growth process is employed to grow, for example, an aluminum gallium nitride barrier layer 1102 on, for example, a silicon substrate or a silicon carbide substrate.
In step S102, a passivation layer 103 of, for example, silicon nitride is deposited on, for example, the aluminum gallium nitride barrier layer 1102 using, but not limited to, a chemical vapor deposition process.
In step S103, the silicon nitride passivation layer 103 and the aluminum gallium nitride barrier layer 1102 are patterned to form an anode 104 and a cathode 107, the anode 104 and the cathode 107 penetrating the silicon nitride passivation layer 103 and protruding into the aluminum gallium nitride barrier layer 1102. More specifically, the steps of patterning the silicon nitride passivation layer 103 and the aluminum gallium nitride barrier layer 1102 to obtain the anode 104 are, for example: coating photoresist on the silicon nitride passivation layer 103, exposing and developing the photoresist to obtain a patterned photoresist layer, then etching the silicon nitride passivation layer 103 and the aluminum gallium nitride barrier layer 1102 by using the patterned photoresist layer as a mask, determining an anode region AZ and a cathode region, and depositing and patterning a first metal to obtain a first metal layer in the anode region AZ. More specifically, the specific steps of obtaining the first metal layer located in the anode region AZ may be: the method comprises the steps of depositing metal by a magnetron sputtering coating process to form a first metal layer, coating photoresist on the first metal layer, exposing and developing the photoresist to obtain a patterned photoresist layer, and etching the first metal layer by using the patterned photoresist layer as a mask to remove the first metal layer outside an anode area AZ shown in the figure so as to obtain the first metal layer positioned in the anode area AZ.
In step S104, depositing and patterning a second metal on the first metal layer in the anode region AZ and in the cathode region to obtain a second metal layer and a cathode 107, and more specifically, the specific steps of obtaining the anode 104 and the cathode 107 may be: depositing a titanium metal layer, a metal aluminum layer, a metal titanium layer and a metal titanium nitride layer in sequence in the passivation layer 103, the first metal layer positioned in the anode region AZ and the cathode region by adopting a process of evaporating metal by using an electron beam, but not limited to, so as to form a second metal layer, namely the second metal layer is a laminated multilayer metal structure, including but not limited to a titanium metal layer, a metal aluminum layer, a metal titanium layer and a metal titanium nitride layer; the second metal layer is then subjected to photolithography and etching processes to form the second metal layer of the anode 104 and the cathode 107, and more specifically, the anode 104 includes the first metal layer and the second metal layer located in the anode region AZ.
In step S105, a protection layer 108 is formed on the passivation layer 103, the anode 104 and the cathode 107, more specifically, the protection layer 108 is, for example, a PETEOS (plasma enhanced tetra ethyl orthosilicate) oxide layer, and the specific step of forming the protection layer 108, for example, the PETEOS oxide layer, may be: a silicon dioxide film, namely a protective layer 108, is prepared on the passivation layer 103, the anode 104 and the cathode 107 by using tetraethoxysilane as a raw material through a microwave plasma chemical vapor deposition method at a low temperature. A photoresist is coated on the protective layer 108, then the photoresist is exposed and developed to obtain a patterned photoresist layer, then the protective layer 108 is etched by using the patterned photoresist layer as a mask until the anode 104 and the cathode 107 are exposed, and the residual patterned photoresist layer is removed.
In steps S106 and S107, a third metal layer is formed on the protective layer 108 and on the exposed anode 104 and cathode 107, and the third metal layer is patterned to form a field plate layer 109. An anode-via metal 110 is formed on the exposed anode 104 and a cathode-via metal 111 is formed on the exposed cathode 107. More specifically, the steps of forming the anode conductive metal 110, the cathode conductive metal 111, and the field plate layer 109 are specifically: a third metal layer, such as copper aluminum silicon (AlSiCu), is deposited on the protective layer 108 using, but not limited to, an electron beam evaporation of metal, and then the third metal layer is subjected to photolithography (gumming, exposure, and development) and etching processes to form an anode via metal 110, a cathode via metal 111, and a field plate layer 109. Wherein the field plate layer 109 is located in a region between the anode conductive metal 110 and the cathode conductive metal 111 and outside the anode region AZ, and is connected to the anode conductive metal 110.
In summary, the present embodiment provides a method for manufacturing a semiconductor device, in which the buffer layer 1101 is disposed to reduce lattice defects of the barrier layer 1102 caused by the lattice constant of the semiconductor substrate 1100, reduce the interface state at the interface between the barrier layer 1102 and the semiconductor substrate 1100, and reduce the interface leakage current at the interface. By arranging the anode conducting metal 110, the cathode conducting metal 111 and the field plate, the depletion region of the semiconductor device is expanded, the electric field distribution is balanced, the electric field intensity of the main Schottky junction is reduced, and the withstand voltage of the semiconductor device is improved.
Referring to fig. 6-1, the present invention further provides a semiconductor device based on gan epitaxial layer, for example, comprising: semiconductor substrate 1100, buffer layer 1101, barrier layer 1102, passivation layer 203, first anode 204, dielectric layer 205, second anode 206, cathode 207, protective layer 208, field plate layer 209, anode conductive metal 210, and cathode conductive metal 211. Wherein the buffer layer 1101 is disposed on the semiconductor substrate 1100, the barrier layer 1102 is disposed on a side of the buffer layer 1101 away from the semiconductor substrate 1100, and the passivation layer 203 is disposed on a side of the barrier layer 1102 away from the semiconductor substrate 1100. The first anode 204 extends through the passivation layer 203 into the barrier layer 1102. A dielectric layer 205 is disposed on a side of the passivation layer 203 away from the barrier layer 1102 and between the first anode 204 and the barrier layer 1102. The second anode 206 extends through the dielectric layer 205, the passivation layer 203, and into the barrier layer 1102. The cathode 207 is disposed on the dielectric layer 205 and penetrates the dielectric layer 205 and the passivation layer 203. The protective layer 208 is disposed on the first anode 204, the second anode 206, the cathode 207, and the dielectric layer 205. A field plate layer 209, anode conductive metal 210 and cathode conductive metal 211 are disposed on the protective layer 208, the field plate layer 209 being located between the anode conductive metal 210 and the cathode conductive metal 211, the field plate layer 209 being in communication with the anode conductive metal 210. On the basis of the above embodiment, in this embodiment, the material of the dielectric layer 205 is, for example, one of silicon nitride, silicon oxide and tetraethoxysilane, a first metal layer and a second metal layer with a multilayer structure are disposed in the first anode 204 and the second anode 206, the material of the first metal layer may be a titanium metal layer or a titanium nitride metal layer, where the second metal layer may include, but is not limited to, a titanium metal layer, a metal aluminum layer, a metal titanium layer and a metal titanium nitride layer, which are stacked in sequence. The cathode 207 includes a second metal layer, and the second metal layer of the cathode 207 and the second metal layer of the anode can be formed simultaneously and have a multi-layer metal structure. In other words, the first anode 204 and the second anode 206 are composed of a first number of metal layers stacked, the cathode 207 is composed of a second number of metal layers stacked, and the first number is larger than the second number.
Referring to fig. 6-1, in the present embodiment, the buffer layer 1101 is disposed to reduce lattice defects of the barrier layer 1102 due to the lattice constant of the semiconductor substrate 1100, reduce the interface state at the interface between the barrier layer 1102 and the semiconductor substrate 1100, and reduce the interface leakage current at the interface. By forming the dielectric layer 205 on the passivation layer 203, the anode area is greatly increased, reverse leakage is reduced, and in addition, by arranging the anode conducting metal 210, the cathode conducting metal 211 and the field plate layer 209, the electric field distribution is balanced, the electric field strength of the main schottky junction is reduced, and the voltage resistance of the semiconductor device is improved.
Referring to fig. 6-2, the present invention further provides a method for manufacturing a semiconductor device, which comprises the following steps:
in step S201, an epitaxial growth process is used to grow a buffer layer 1101 and an aluminum gallium nitride barrier layer 1102 on a silicon substrate or a silicon carbide substrate.
In step S202, a silicon nitride passivation layer 203 is deposited on the aluminum gallium nitride barrier layer 1102 using, but not limited to, a chemical vapor deposition process.
In steps S203, S204, and S205, the silicon nitride passivation layer 203 and the aluminum gallium nitride barrier layer 1102 are patterned to form a first anode 204, a dielectric layer 205 is formed on the silicon nitride passivation layer 203 and within the first anode 204, and the dielectric layer 205, the silicon nitride passivation layer 203, and the aluminum gallium nitride barrier layer 1102 are patterned to form a second anode 206 that penetrates through the dielectric layer 205, the silicon nitride passivation layer 203, and extends into the aluminum gallium nitride barrier layer 1102. More specifically, the dielectric layer 205 is, for example, one of silicon nitride, silicon oxide and ethyl orthosilicate, and the step of patterning the dielectric layer 205, the silicon nitride passivation layer 203 and the aluminum gallium nitride barrier layer 1102 to form the second anode 206 penetrating through the dielectric layer 205, the silicon nitride passivation layer 203 and extending into the aluminum gallium nitride barrier layer 1102 includes, for example: and coating photoresist on the dielectric layer 205, exposing and developing the photoresist to obtain a patterned photoresist layer, and etching the dielectric layer 205, the silicon nitride passivation layer 203 and the aluminum gallium nitride barrier layer 1102 by using the patterned photoresist layer as a mask to form the second anode 206. Forming a first metal layer on the dielectric layer 205 and in the second anode 206, and patterning the first metal layer to obtain the first metal layer located in the first anode 204 and the second anode 206, more specifically, the specific steps of obtaining the first metal layer located in the first anode 204 and the second anode 206 may be: a magnetron sputtering coating process is adopted to deposit metal in the second anode 206 region and on the dielectric layer 205 to form a first metal layer, the material of the first metal layer may be one of titanium nitride and titanium, a photoresist is coated on the first metal layer, then the photoresist is exposed and developed to obtain a patterned photoresist layer, and then the patterned photoresist layer is used as a mask to etch the first metal layer to remove the first metal layer outside the first anode 204 and the second anode 206, so as to obtain the first metal layer inside the first anode 204 and the second anode 206.
In step S206, the dielectric layer 205 and the silicon nitride passivation layer 203 are patterned to form a cathode 207 region extending through the dielectric layer 205 and the silicon nitride passivation layer 203. More specifically, the step of patterning the dielectric layer 205 and the silicon nitride passivation layer 203 to form the cathode 207 region penetrating through the dielectric layer 205 and the silicon nitride passivation layer 203 may specifically be: and coating a photoresist on the dielectric layer 205, then exposing and developing the photoresist to obtain a patterned photoresist layer, then etching the dielectric layer 205 and the silicon nitride passivation layer 203 by using the patterned photoresist layer as a mask until the surface of the aluminum gallium nitride barrier layer 1102 is exposed, forming a cathode 207 region, and removing the residual patterned photoresist layer. A second metal layer is formed on the dielectric layer 205 and the first metal layer in the first anode 204 and the second anode 206 and in the cathode 207 region and patterned to obtain a second metal layer for the anode and the cathode 207. More specifically, the specific steps to obtain the complete anode and cathode 207 may be: a titanium metal layer, an aluminum metal layer, a titanium metal layer and a titanium nitride metal layer are sequentially deposited in the dielectric layer 205, the first metal layer located in the first anode 204 and the second anode 206 and the cathode 207 region by a process of, but not limited to, electron beam evaporation of metal to form a second metal layer, i.e., the second metal layer is a laminated multi-layer metal structure including, but not limited to, a titanium metal layer, an aluminum metal layer, a titanium metal layer and a titanium nitride metal layer, and then the second metal layer is subjected to a photolithography and etching process to form the second metal layer of the anode and the cathode 207, more specifically, the anode includes the first metal layer and the second metal layer located in the first anode 204 and the second anode 206.
In step S207, a protective layer 208 is formed on the dielectric layer 205 and the anode and cathode 207. More specifically, the protection layer 208 is, for example, a PETEOS (Plasma Enhanced tetra ethyl orthosilicate) oxide layer, and the specific steps for forming the protection layer 208 is, for example, a PETEOS oxide layer may be: a silicon dioxide film, i.e., a protective layer 208, is prepared on the dielectric layer 205, the first anode 204, the second anode 206 and the cathode 207 by using tetraethoxysilane as a raw material at a low temperature by, for example, a microwave plasma chemical vapor deposition method.
In step 208, the protective layer 208 is patterned to expose the first anode 204, the second anode 206, and the cathode 207, respectively. More specifically, the step of exposing the first anode 204, the second anode 206 and the cathode 207 may specifically be: a photoresist is coated on the protection layer 208, then the photoresist is exposed and developed to obtain a patterned photoresist layer, then the protection layer 208 is etched by using the patterned photoresist layer as a mask until the first anode 204, the second anode 206 and the cathode 207 are exposed, and the residual patterned photoresist layer is removed.
In step S209, a third metal layer is formed on the passivation layer 208 and the exposed first anode 204, second anode 206, and cathode 207, and patterned to form a field plate layer 209, an anode via metal 210 is formed on the exposed first anode 204 and second anode 206, and a cathode via metal 211 is formed on the exposed cathode 207. More specifically, the steps of forming the anode conducting metal 210, the cathode conducting metal 211 and the field plate are specifically: depositing a third metal layer on the protective layer 208 by, but not limited to, a process of evaporating metal by electron beam, wherein the third metal layer is made of a material such as copper-silicon-aluminum (AlSiCu); the third metal layer is then subjected to photolithography (glue coating, exposure, and development) and etching processes to form anode conductive metal 210, cathode conductive metal 211, and field plate layer 209. Wherein the field plate layer 209 is located in a region between the anode conductive metal 210 and the cathode conductive metal 211 and outside the anode region AZ, and is connected to the anode conductive metal 210.
Referring to fig. 7-1, the present invention further provides a semiconductor device based on gan epitaxial layer, which comprises: the semiconductor device comprises a semiconductor substrate 1100, a buffer layer 1101, a barrier layer 1102, a passivation layer 303, a first anode contact hole 313, a dielectric layer 305, a second anode contact hole 314, a first anode 304, a second anode 306, a cathode contact hole 315, a cathode 307, a protective layer 308, an anode opening 316, a cathode opening 317, an anode conducting metal 310, a cathode conducting metal 311 and a field plate layer 309. Wherein the buffer layer 312 is disposed on the semiconductor substrate 1100. The barrier layer 1102 is provided on a side of the buffer layer 1101 remote from the semiconductor substrate 1100. A passivation layer 303 is disposed on a side of the barrier layer 1102 away from the buffer layer 1101. The first anode contact hole 313 penetrates the passivation layer 303 and protrudes into the barrier layer 1102. Dielectric layer 305 is disposed on a side of passivation layer 303 away from barrier layer 1102 and within first anode contact hole 313. The second anode contact hole 314 penetrates the dielectric layer 305, the passivation layer 303 and extends into the barrier layer 1102. The first anode 304 and the second anode 306 are disposed in the first anode contact hole 313 and the second anode contact hole 314, the first anode 304 and the second anode 306 include a first metal layer and a second metal layer therein, wherein the first metal layer is disposed on a side of the dielectric layer 305 away from the passivation layer 303 and extends into the first anode contact hole 313 and the second anode contact hole 314 to cover the bottom of the dielectric layer 305 and the second anode contact hole 314 at the bottom of the first anode contact hole 313, and the second metal layer is disposed on the first metal layer and fills the first anode contact hole 313 and the second anode contact hole 314. Cathode contact hole 315 extends through dielectric layer 305 and passivation layer 303. The cathode 307 is disposed on the dielectric layer 305 and fills the cathode contact hole 315. A protective layer 308 is disposed over the first anode 304, the second anode 306, the cathode 307, and the dielectric layer 305. An anode opening 316 extends through the protective layer 308 to expose the first anode 304 and the second anode 306. A cathode opening 317 extends through the protective layer 308 to expose the cathode 307. An anode via metal 310 is disposed on a side of the protection layer 308 away from the dielectric layer 305, and the anode via metal 310 fills the anode opening 316. Cathode via metal 311 is disposed on a side of the passivation layer 308 away from the dielectric layer 305, and the cathode via metal 311 fills the cathode opening 317. The field plate layer 309 is disposed on the protection layer 308 and located in the region between the anode conductive metal 310 and the cathode conductive metal 311 and connected to the anode conductive metal 310, wherein the anode conductive metal 310, the cathode conductive metal 311 and the field plate layer 309 can be formed simultaneously, for example, in the same photolithography and etching process. On the basis of the above embodiments, the first anode contact hole 313 and the second anode contact hole 314 of the present embodiment are, for example, strip-shaped grooves, the material of the first metal layer included in the first anode 304 and the second anode 306 may be a titanium metal layer or a titanium nitride metal layer, and the second metal layer included in the first anode 304 and the second anode 306 is a multilayer structure, which may include, but is not limited to, a titanium metal layer, a metal aluminum layer, a metal titanium layer, and a metal titanium nitride layer, which are stacked in sequence. The cathode 307 and the second metal layer are formed simultaneously, for example, in the same electron beam evaporation process, and are all multi-layered metal structures. In other words, the first anode 304 and the second anode 306 are composed of a first number of metal layers stacked, the cathode 307 is composed of a second number of metal layers stacked, and the first number is larger than the second number.
In this embodiment, the semiconductor device greatly increases the area of the anode and reduces reverse leakage by forming the dielectric layer 305 on the passivation layer 303. In addition, by arranging the anode conducting metal 310, the cathode conducting metal 311 and the field plate structure, the electric field distribution is equalized, the electric field strength of the main schottky junction is reduced, and the withstand voltage of the semiconductor device is improved.
Referring to fig. 7-2, the present invention further provides a method for manufacturing a semiconductor device, the method comprising:
in step S301, a gallium nitride layer, for example, is grown on a silicon substrate or a silicon carbide substrate using an epitaxial growth process, and then an aluminum gallium nitride layer, for example, is grown on the gallium nitride layer using an epitaxial growth process.
In step S302, a silicon nitride passivation layer 303 is deposited on the aluminum gallium nitride layer using, but not limited to, a chemical vapor deposition process.
In step S303, the silicon nitride passivation layer 303 and the aluminum gallium nitride layer are patterned to form a first anode contact hole 313, wherein the first anode contact hole 313 penetrates through the silicon nitride passivation layer 303 and extends into the aluminum gallium nitride layer. More specifically, the steps of patterning the silicon nitride passivation layer 303 and the aluminum gallium nitride layer to form the first anode contact hole 313 are, for example: and coating photoresist on the silicon nitride passivation layer 303, exposing and developing the photoresist to obtain a patterned photoresist layer, and etching the silicon nitride passivation layer 303 and the aluminum gallium nitride layer by using the patterned photoresist layer as a mask to form a first anode contact hole 313, wherein the first anode contact hole 313 is a strip-shaped groove.
In step S304, a dielectric layer 305 is formed on the silicon nitride passivation layer 303 and within the first anode contact hole 313, and the dielectric layer 305, the silicon nitride passivation layer 303 and the aluminum gallium nitride layer are patterned to form a second anode contact hole 314 penetrating through the dielectric layer 305, the silicon nitride passivation layer 303 and extending into the aluminum gallium nitride layer. More specifically, the material of the dielectric layer 305 is, for example, one of silicon nitride, silicon oxide and ethyl orthosilicate, and the step of patterning the dielectric layer 305, the silicon nitride passivation layer 303 and the aluminum gallium nitride layer to form the second anode contact hole 314 penetrating through the dielectric layer 305, the silicon nitride passivation layer 303 and extending into the aluminum gallium nitride layer includes, for example: a photoresist is coated on the dielectric layer 305, the photoresist is exposed and developed to obtain a patterned photoresist layer, and then the dielectric layer 305, the silicon nitride passivation layer 303 and the aluminum gallium nitride layer are etched by using the patterned photoresist layer as a mask to form a second anode contact hole 314. The areas where the first anode contact hole 313 and the second anode contact hole 314 are located constitute an anode region AZ, and the first anode electrode 304 and the second anode electrode 306 fill the first anode contact hole 313 and the second anode contact hole 314, respectively.
In step S305, a first metal layer is formed on the dielectric layer 305 and in the second anode contact hole 314, and the first metal layer is patterned to obtain a first metal layer located in the anode region AZ. More specifically, the specific steps of obtaining the first metal layer located in the anode region AZ may be: and depositing metal in the second anode contact hole 314 and on the dielectric layer 305 by using a magnetron sputtering coating process to form a first metal layer, wherein the material of the first metal layer may be one of titanium nitride and titanium, coating a photoresist on the first metal layer, then exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the first metal layer by using the patterned photoresist layer as a mask to remove the first metal layer outside the anode region AZ so as to obtain the first metal layer located in the anode region AZ.
In step S306, the dielectric layer 305 and the silicon nitride passivation layer 303 are patterned to form a cathode contact hole 315 penetrating the dielectric layer 305 and the silicon nitride passivation layer 303. More specifically, the step of patterning the dielectric layer 305 and the silicon nitride passivation layer 303 to form the cathode contact hole 315 penetrating through the dielectric layer 305 and the silicon nitride passivation layer 303 may specifically be: a photoresist is coated on the dielectric layer 305, then the photoresist is exposed and developed to obtain a patterned photoresist layer, and then the dielectric layer 305 and the silicon nitride passivation layer 303 are etched by using the patterned photoresist layer as a mask until the surface of the aluminum gallium nitride layer is exposed, so as to form a cathode contact hole 315 and remove the residual patterned photoresist layer.
In step S307, a second metal layer is formed on the dielectric layer 305 and the first metal layer located in the anode region AZ and in the cathode contact hole 315, and the second metal layer is patterned to obtain the second metal layer of the first anode 304 and the second anode 306 and the cathode 307, wherein the cathode 307 fills the cathode contact hole 315. More specifically, the specific steps of obtaining the first anode 304, the second anode 306 and the cathode 307 may be: a titanium metal layer, an aluminum metal layer, a titanium metal layer and a titanium nitride metal layer are sequentially deposited in the dielectric layer 305, the first metal layer located in the anode region AZ and the cathode contact hole 315 by a process of, but not limited to, electron beam evaporation of metal to form a second metal layer, i.e., the second metal layer is a stacked multilayer metal structure including, but not limited to, a titanium metal layer, an aluminum metal layer, a titanium metal layer and a titanium nitride metal layer, and then the second metal layer is subjected to a photolithography and etching process to form a second metal layer of the first anode 304 and the second anode 306 and the cathode 307, and more specifically, the first anode 304 and the second anode 306 include the first metal layer and the second metal layer located in the anode region AZ.
In step S308, a protective layer 308 is formed on the dielectric layer 305, the first anode 304, the second anode 306, and the cathode 307.
In step S309, the protection layer 308 is patterned to form an anode opening 316 and a cathode opening 317 through the protection layer 308 exposing the first anode 304, the second anode 306 and the cathode 307, respectively. More specifically, the step of patterning the passivation layer 308 to form the anode opening 316 and the cathode opening 317 penetrating the passivation layer 308 may specifically be: a photoresist is coated on the protection layer 308, and then the photoresist is exposed and developed to obtain a patterned photoresist layer, and then the protection layer 308 is etched by using the patterned photoresist layer as a mask until the first anode 304, the second anode 306 and the cathode 307 are exposed, so as to form an anode opening 316 and a cathode opening 317, and remove the residual patterned photoresist layer.
In step S310, a third metal layer is formed on the protection layer 308 and the anode opening 316 and the cathode opening 317, and the third metal layer is patterned to form a field plate layer 309, an anode via metal 310 filling the anode opening 316, and a cathode via metal 311 filling the cathode opening 317. More specifically, the steps of forming the anode conductive metal 310, the cathode conductive metal 311 and the field plate are specifically: a third metal layer, such as copper aluminum silicon (AlSiCu), is deposited on the protective layer 308 by, but not limited to, an electron beam evaporation metal process, and then the third metal layer is subjected to photolithography (gumming, exposure and development) and etching processes to form the anode via metal 310, the cathode via metal 311 and the field plate. Wherein the field plate layer 309 is located in a region between the anode conductive metal 310 and the cathode conductive metal 311 and outside the anode region AZ, and is connected to the anode conductive metal 310.
In summary, in the method for manufacturing a semiconductor device according to the present embodiment, the dielectric layer 305 is formed by depositing a layer of dielectric material on the surface of the silicon nitride passivation layer 303 and in the first anode contact hole 313, so that the area of the anode is increased, the reverse leakage is greatly reduced, and the dielectric layer can be formed simultaneously with the gate dielectric layer of the GaN HEMT and is compatible with the CMOS process line. Furthermore, by arranging the anode conducting metal 310, the cathode conducting metal 311 and the field plate layer 309, the depletion region of the semiconductor device is expanded, the electric field distribution is balanced, the electric field intensity of the main Schottky junction is reduced, and the withstand voltage of the semiconductor device is improved.
Referring to fig. 8-1, the present invention further provides a semiconductor device based on gan epitaxial layer, for example, comprising: the semiconductor device includes a semiconductor substrate 1200, a first buffer layer 1201, a second buffer layer 1202, a third buffer layer 1203, a barrier layer 1204, a passivation layer 503, a first anode contact hole 513, a first anode 504, a dielectric layer 505, a second anode contact hole 514, a second anode 506, a cathode contact hole 515, a cathode 507, a protective layer 508, a field plate layer 509, an anode opening 516, an anode conducting metal 510, a cathode opening 517 and a cathode conducting metal 511.
Referring to fig. 8-1, the semiconductor device of the present embodiment is fabricated by using the gan epitaxial layer of fig. 2-1 as a substrate, and fabricating the semiconductor device of the previous embodiment thereon.
Referring to fig. 8-2, the present embodiment further provides a method for manufacturing a semiconductor device, which includes the following steps:
in step S501, an epitaxial layer of gallium nitride as in fig. 2-1 is prepared.
In steps S502-S510, a semiconductor device is fabricated on the gallium nitride epitaxial layer as in fig. 2-1 in accordance with steps S302-S310 in fig. 7-2.
Referring to fig. 9-1, the present invention further provides a semiconductor device based on gan epitaxial layer, for example, comprising: the semiconductor device comprises a semiconductor substrate 1300, a first buffer layer 1301, a post-processing layer 1302, a second buffer layer 1303, a barrier layer 1304, a passivation layer 603, a first anode contact hole 613, a first anode 604, a dielectric layer 605, a second anode contact hole 614, a second anode 606, a cathode contact hole 617, a cathode 607, a protective layer 608, a field plate layer 609, an anode opening 616, an anode conducting metal 610, a cathode opening 617 and a cathode conducting metal 611.
Referring to fig. 9-1, the semiconductor device of the present embodiment is fabricated by using the gan epitaxial layer of fig. 3-1 as a substrate, and fabricating the semiconductor device of the previous embodiment thereon.
Referring to fig. 9-2, the present embodiment further provides a method for manufacturing a semiconductor device, which includes the following steps:
in steps S601-S604, on the semiconductor substrate 1300, an epitaxial layer of gallium nitride as shown in fig. 3-1 is prepared.
In steps S605 to S613, a semiconductor device is fabricated on the gallium nitride epitaxial layer shown in fig. 3-1 in accordance with steps S302 to S310 in fig. 7-2.
Referring to fig. 10-1, the present invention further provides a semiconductor device based on a gan epitaxial layer, comprising: the semiconductor device comprises a semiconductor substrate 1300, a first buffer layer 1301, a post-processing layer 1302, a second buffer layer 1303, a barrier layer 1304, a dielectric layer 705, a source 704, a drain 706 and a gate 707.
Referring to fig. 10-1, a first buffer layer 1301 is disposed on a semiconductor substrate 1300, a post-treatment layer 1302 is disposed on a side of the first buffer layer 1301 away from the semiconductor substrate 1300, a second buffer layer 1303 is disposed on a side of the post-treatment layer 1302 away from the first buffer layer 1301, a barrier layer 1304 is disposed on a side of the second buffer layer 1303 away from the post-treatment layer 1302, the barrier layer 1304 has a wider band gap than that of the second buffer layer 1303 and induces a 2D electron gas (2DEG) in the channel. The dielectric layer 705 is disposed on a side of the barrier layer 1304 away from the second buffer layer 1303. The source 704, the drain 706 and the gate 707 are arranged in the dielectric layer 705, the source 704, the drain 706 and the gate 707 respectively penetrate through the dielectric layer 705 and are connected with the barrier layer 1304, and a part of the source 704, the drain 706 and the gate 707 protrudes out of the top of the dielectric layer 705, wherein the gate 707 extends into the barrier layer 1304 to reach the bottom of the barrier layer 1304, the gate 707 is in a tapered structure, and the ratio of the upper edge to the lower edge of the taper is 1: 2-1: 4.
referring to fig. 10-1, in the present embodiment, based on the above embodiment, the source 704 and the drain 706 are formed by a third metal layer, and the third metal layer sequentially includes a first titanium metal layer, an aluminum metal layer, a second titanium metal layer, and a titanium nitride layer. The gate 707 is composed of a fourth metal layer, which is nickel or gold alloy.
Referring to fig. 10-2, the present embodiment further provides a method for manufacturing a semiconductor device, which includes the following steps:
in step 701, an epitaxial layer of gallium nitride as shown in fig. 3-1 is prepared on a semiconductor substrate 1300.
In step 702, a layer of hafnium oxide (HfO2) may then be deposited on the surface of the gan-based epitaxial wafer using a plasma enhanced chemical vapor deposition process to form a dielectric layer 705. The thickness of the hafnium oxide may be 2000 angstroms, for example.
In step 703, the dielectric layer 705 is dry etched to form a source 704 contact hole and a drain 706 contact hole that are oppositely disposed.
In step 704, a first metal is deposited in the source 704 contact holes and the drain 706 contact holes, and on the surface of the dielectric layer 705. Specifically, a magnetron sputtering coating process may be adopted to sequentially deposit a first titanium metal layer, an aluminum metal layer, a second titanium metal layer and a titanium nitride layer in the contact hole of the source 704 and the contact hole of the drain 706 and on the surface of the dielectric layer 705 to form the first metal layer, where the thickness of the first titanium metal layer may be, for example, 200 angstroms, the thickness of the aluminum metal layer may be, for example, 1200 angstroms, the thickness of the second titanium metal layer may be, for example, 200 angstroms, and the thickness of the titanium nitride layer may be, for example, 200 angstroms. The first metal is then patterned and etched to expose a portion of the surface of dielectric layer 705. Wherein the photolithography process comprises gumming, exposing and developing. Thus, the first metal layer over the contact hole of the source 704 forms the source 704 of the device, and the first metal layer over the contact hole of the drain 706 forms the drain 706 of the device.
In step 705, dry etching is performed on the exposed surface of the dielectric layer 705 and the gallium nitride layer to form a contact hole 707 for the gate. The contact hole of the gate 707 completely penetrates through the dielectric layer 705 and penetrates through the gallium nitride layer to reach the bottom of the gallium nitride layer, the gate 707 is in a conical structure, and the ratio of the upper edge to the lower edge of the conical structure is 1: 2-1: 4.
in step 706, a magnetron sputtering coating process is adopted to deposit a silicon nitride layer in the contact hole of the gate 707, wherein the silicon nitride layer is not higher than the contact hole of the gate 707, and then Ni/Au is deposited on the silicon nitride layer and on the outer edge of the contact hole of the gate 707 to be used as a second metal, wherein the thickness ratio of the Ni/Au metal is 0.01-0.04 μm/0.08-0.4 μm, so that the gate 707 is formed. Thus, the gate 707 is a composite structure having multiple materials.
Referring to fig. 11-1, the present invention further provides a semiconductor device based on gan epitaxial layer, for example, comprising: the semiconductor device comprises a semiconductor substrate 1400, a first buffer layer 1401, a nano buffer layer 1402, a second buffer layer 1403, a barrier layer 1404, a passivation layer 803, a first anode contact hole 813, a first anode 804, a dielectric layer 805, a second anode contact hole 814, a second anode 806, a cathode contact hole 815, a cathode 807, a protective layer 808, a field plate layer 809, an anode opening 816, anode conducting metal 810, a cathode opening 817 and cathode conducting metal 811.
Referring to fig. 11-1, the semiconductor device of the present embodiment is fabricated by using the gan epitaxial layer of fig. 4-1 as a substrate, and fabricating the semiconductor device of the previous embodiment thereon.
As shown in fig. 11-1, in other embodiments, the nano buffer layer 1402 may be disposed between the semiconductor substrate 1400 and the buffer layer, between the multiple buffer layers, and between the buffer layer and the barrier layer 1404, and the nano buffer layer 1402 provides nucleation points for the growth of the subsequent growth layer, which is beneficial to improving the film-forming quality of the subsequent growth layer.
Referring to fig. 11-2, the present invention also provides a method for manufacturing a semiconductor device, comprising the following steps:
in steps S801-S804, an epitaxial layer of gallium nitride as in fig. 4-1 is prepared.
In steps S805 to S813, a semiconductor device is fabricated on the gallium nitride epitaxial layer as shown in fig. 4-1 in accordance with steps S302 to S310 in fig. 7-2.
The preferred embodiments of the invention disclosed above are intended to be illustrative only. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
The preferred embodiments of the invention disclosed above are intended to be illustrative only. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims (10)

1. A semiconductor device, comprising:
a semiconductor substrate;
a first buffer layer disposed on the semiconductor substrate;
the post-processing layer is arranged on one side, far away from the semiconductor substrate, of the first buffer layer;
the second buffer layer is arranged on one side, far away from the first buffer layer, of the post-treatment layer;
a barrier layer disposed on a side of the second buffer layer away from the post-treatment layer;
a passivation layer disposed on a side of the barrier layer away from the second buffer layer;
a first anode contact hole penetrating the passivation layer into the barrier layer;
a first anode disposed within the first anode contact hole;
the dielectric layer is arranged on one side of the passivation layer far away from the barrier layer and between the first anode and the barrier layer;
the second anode contact hole penetrates through the dielectric layer and the passivation layer and extends into the barrier layer;
a second anode disposed within the second anode contact hole;
a cathode contact hole penetrating the dielectric layer and the passivation layer;
the cathode is arranged on the dielectric layer and in the cathode contact hole;
a protective layer disposed over the first anode, the second anode, the cathode, and the dielectric layer;
an anode opening through the protective layer to expose the first anode and the second anode;
the anode conducting metal is arranged on one side of the protective layer, which is far away from the dielectric layer, and is connected with the first anode and the second anode;
a cathode opening through the protective layer to expose the cathode;
the cathode conducting metal is arranged on one side, far away from the dielectric layer, of the protective layer, and the cathode conducting metal is connected with the cathode;
a field plate layer disposed on the protective layer, the field plate layer being connected with the anode conductive metal, wherein the anode conductive metal, the cathode conductive metal, and the field plate layer are formed simultaneously.
2. The semiconductor device according to claim 1, wherein the first anode and the second anode comprise a first metal layer and a second metal layer, wherein the first metal layer is disposed on a side of the dielectric layer away from the passivation layer and extends into the first anode contact hole and the second anode contact hole to cover the dielectric layer at the bottom of the first anode contact hole and the bottom of the second anode contact hole, and the second metal layer is disposed on the first metal layer and fills the first anode contact hole and the second anode contact hole.
3. A semiconductor device according to claim 1, wherein the first and second anodes are formed of a first number of metal layers stacked, the cathode is formed of a second number of metal layers stacked, and the first number is greater than the second number.
4. An epitaxial layer of gallium nitride, comprising:
a semiconductor substrate;
a first buffer layer disposed on the semiconductor substrate;
the post-processing layer is arranged on one side, far away from the semiconductor substrate, of the first buffer layer;
the second buffer layer is arranged on one side, far away from the first buffer layer, of the post-treatment layer;
a barrier layer disposed on a side of the second buffer layer away from the post-treatment layer.
5. The epitaxial layer of gallium nitride according to claim 4, wherein the first buffer layer is an aluminum nitride layer.
6. The epitaxial layer of gallium nitride according to claim 4, wherein the thickness of the first buffer layer is 10-300 nm.
7. The epitaxial layer of gallium nitride according to claim 4, wherein the post-treatment layer is an aluminum oxide layer.
8. An epitaxial layer of gallium nitride according to claim 4, wherein the thickness of the post-treatment layer is 0.5-2 nm.
9. A method for manufacturing a semiconductor device, comprising at least the steps of:
forming a first buffer layer on a substrate by using a Physical Vapor Deposition (PVD) process;
forming a post-treatment layer on the first buffer layer using an atomic deposition technology (ALD) process;
forming a second buffer layer on the post-treatment layer by using a Physical Vapor Deposition (PVD) process;
forming a barrier layer on the second buffer layer;
forming a passivation layer on the barrier layer;
forming a first anode contact hole in the passivation layer and the barrier layer, wherein the first anode contact hole penetrates through the passivation layer and extends into the barrier layer;
forming a dielectric layer on the passivation layer and in the first anode contact hole, and patterning the dielectric layer, the passivation layer and the barrier layer to form a second anode contact hole penetrating through the dielectric layer and the passivation layer and extending into the barrier layer;
forming a first metal layer of an anode in the dielectric layer and the second anode contact hole;
forming a cathode contact hole penetrating through the dielectric layer and the passivation layer on the dielectric layer and the passivation layer;
forming a second metal layer of an anode on the dielectric layer and the first metal layer of the anode and in the cathode contact hole, thereby obtaining a first anode and a second anode comprising the first metal layer and the second metal layer and a cathode comprising the second metal layer;
forming a protective layer on the dielectric layer, the first anode, the second anode and the cathode;
patterning the protective layer to form a field plate layer, the field plate layer being connected to the first anode and the second anode.
10. The method according to claim 9, wherein the post-treatment layer is an aluminum oxide layer.
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