CN112420827A - N-surface GaN HEMT device and manufacturing method thereof - Google Patents

N-surface GaN HEMT device and manufacturing method thereof Download PDF

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Publication number
CN112420827A
CN112420827A CN202011319555.4A CN202011319555A CN112420827A CN 112420827 A CN112420827 A CN 112420827A CN 202011319555 A CN202011319555 A CN 202011319555A CN 112420827 A CN112420827 A CN 112420827A
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layer
resistance
substrate
hemt device
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张丽
于国浩
张宝顺
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Suzhou Nengwu Electronic Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Abstract

The application discloses an N-surface GaN HEMT device and a manufacturing method thereof. The HEMT device comprises an epitaxial structure, and a source, a drain and a grid which are matched with the epitaxial structure; the epitaxial structure comprises a high-resistance layer, a channel layer and a barrier layer which are sequentially grown and formed along a set direction, and two-dimensional electron gas is further formed at the interface of the channel layer and the barrier layer; the high-resistance layer at least serves as an in-situ passivation layer, and the grid electrode is distributed on the high-resistance layer. According to the method, direct growth is replaced by a transfer technology, the high-quality N-surface GaN material can be easily and controllably obtained, wherein high-resistance (Al) GaN is used as an in-situ passivation layer, on one hand, damage of etching to a GaN-AlGaN heterojunction is effectively reduced, high two-dimensional electron gas mobility and carrier concentration can be maintained, on the other hand, the problem that the secondary growth passivation layer introduces surface state to deteriorate device performance is avoided, and the obtained N-surface GaN HEMT device has various remarkably improved performances.

Description

N-surface GaN HEMT device and manufacturing method thereof
Technical Field
The present disclosure relates to a High Electron Mobility Transistor (HEMT), and particularly to an N-plane GaN HEMT device and a method for fabricating the same, and belongs to the field of semiconductor technology.
Background
The GaN-based material has the characteristics of wide band gap, high saturated electron rate, high thermal conductivity and stable chemical property, so that the GaN-based material is suitable for manufacturing electronic devices with high frequency, high power, radiation resistance and high-temperature operation. A non-doped heterojunction interface made by utilizing the polarization effect of the GaN material can form high-concentration Two-dimensional electron gas (2DEG), so that impurity scattering is avoided, and the electron mobility is greatly improved. The High Electron Mobility Transistor (HEMT) prepared based on the two-dimensional electron gas has the characteristics of high power density, strong breakdown electric field, high cut-off frequency, high switching speed and the like, is very suitable for working under high-frequency, high-power and high-voltage conditions, and has good application prospects in the fields of communication, phased array radar, satellite communication, military electronic countermeasure and power electronics.
Compared with a Ga polar surface HEMT, an N polar surface HEMT device can obtain lower ohmic contact resistance, electron leakage can be effectively prevented due to a back potential barrier formed by the AlGaN layer, the high concentration of the 2DEG is kept, meanwhile, the thickness of the GaN layer can be reduced in equal proportion along with the equal proportion reduction of the device when the length of a grid electrode is reduced, the control of the grid electrode on the 2DEG is improved, and higher working frequency can be obtained. Fig. 1 shows a conventional N-plane GaN HEMT device including an (Al) GaN buffer layer 12, an AlGaN barrier layer 13, a GaN channel layer 14, a passivation layer 15 covering the GaN channel layer 14, and the like, which are sequentially grown on a substrate 11, and source, drain, and gate electrodes 16, 17, 18. Referring to fig. 2, the device is mainly prepared by a process including growing a required N-plane GaN-AlGaN heterostructure on a substrate by using MOCVD (metal organic Vapor Deposition), MBE (molecular beam epitaxy) and other material epitaxy equipment, depositing a surface Passivation layer (Passivation) by using LPCVD (Low Pressure Chemical Vapor Deposition), PECVD (plasma enhanced Chemical Vapor Deposition) and other equipment, and respectively manufacturing source and drain metals and gate metals by using a photolithography technique. The source electrode (source) and the drain electrode (drain) are in ohmic contact with the 2DEG, when bias voltage is applied between the source electrode and the drain electrode, a transverse electric field can be formed, the 2DEG can be subjected to the action of the transverse electric field to transport along a heterojunction interface to form current, the grid electrode (Gate) and the heterojunction (such as AlGaN/GaN heterojunction) are in Schottky contact, and the grid voltage is applied to the grid electrode to control the opening and closing of a 2DEG channel.
Although the N-polar GaN material has outstanding advantages in the preparation of HEMT devices, the application of the N-polar surface material is limited by the difficulty in material preparation, the existing N-polar surface GaN preparation method mainly adopts MOCVD and MBE epitaxial techniques, but the quality (surface appearance, impurity concentration and threading dislocation quantity) of the N-polar surface GaN material can not reach the application level of the devices due to the immature growth process and the characteristics of the material. In addition, the surface passivation layer of the current N-plane GaN HEMT device grows in a secondary epitaxial mode, that is, a device structure grows on a substrate by using MOCVD or MBE equipment, and then the device structure is transferred to thin film deposition equipment such as PECVD to grow the passivation layer, surface states can be introduced into the device when the device is in contact with air, and the surface states can capture electrons in a GaN channel in the switching process of the device to cause a current collapse phenomenon, so that the performance of the device is deteriorated.
Disclosure of Invention
The application mainly aims to provide an N-surface GaN HEMT device and a manufacturing method thereof, so that the defects in the prior art are overcome.
In order to achieve the above purpose, the present application adopts a technical solution comprising:
some embodiments of the present application provide an N-plane GaN HEMT device comprising an epitaxial structure and a source, a drain, a gate cooperating with the epitaxial structure; the epitaxial structure comprises a high-resistance layer, a channel layer and a barrier layer which are sequentially grown and formed along a set direction, and two-dimensional electron gas is further formed at the interface of the channel layer and the barrier layer; wherein, the high-resistance layer at least serves as an in-situ passivation layer, and the grid electrode is distributed on the high-resistance layer.
In some embodiments, the barrier layer further has an insulating dielectric layer formed thereon, the insulating dielectric layer being bonded to the substrate.
Some embodiments of the present application provide a method of fabricating the N-plane GaN HEMT device, comprising:
at least growing a buffer layer, a high-resistance layer, a channel layer and a barrier layer on a substrate in sequence to obtain an epitaxial structure;
separating the substrate from the epitaxial structure and removing at least the buffer layer;
and manufacturing a source electrode, a drain electrode and a grid electrode, distributing the grid electrode on the high-resistance layer, and electrically contacting the source electrode, the drain electrode and the channel layer.
In some embodiments, the manufacturing method further comprises: the method comprises the steps of growing a buffer layer, a high-resistance layer, a channel layer, a barrier layer and a cap layer on a substrate in sequence, growing an insulating medium layer on the cap layer, and bonding the insulating medium layer and a substrate.
Compared with the prior art, the technical scheme provided by the embodiment of the application at least has the following advantages:
(1) the manufacturing of the N-surface GaN epitaxial structure adopts a transfer technology to replace direct growth, thereby overcoming the difficult growth process of the N-surface GaN and obtaining a high-quality N-surface GaN material;
(2) by means of the Ga-face GaN HEMT basic structure, the back is etched to the high-resistance layer, on one hand, a heterojunction behind the high-resistance layer is protected, damage caused by etching is avoided, high carrier concentration and mobility of two-dimensional electron gas are maintained, on the other hand, the high-resistance layer is used as an in-situ passivation layer, the secondary epitaxial passivation layer is prevented from being introduced into a surface state, and a foundation can be laid for realizing a follow-up microwave high-power device.
Drawings
Fig. 1 is a schematic structural view of a conventional N-plane GaN HEMT device;
FIG. 2 is a schematic diagram of a conventional fabrication process for an N-plane GaN HEMT device;
fig. 3 is a schematic structural diagram of an N-plane GaN HEMT device according to an exemplary embodiment of the present application;
fig. 4 is a schematic view of a process for fabricating an N-plane GaN HEMT device according to an exemplary embodiment of the present application;
fig. 5 is a flowchart of a manufacturing process of an N-plane GaN HEMT device according to an embodiment of the present application.
Detailed Description
In view of the deficiencies in the prior art, the inventors of the present application have made extensive studies and extensive practices to provide the technical solutions of the present application. The technical solution, the implementation process and the principle thereof will be further explained with reference to the drawings.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the term "connected" or the like is to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
One aspect of the embodiments of the present application provides an N-plane GaN HEMT device comprising an epitaxial structure, and a source, a drain, and a gate cooperating with the epitaxial structure; the epitaxial structure comprises a high-resistance layer, a channel layer and a barrier layer which are sequentially grown and formed along a set direction, and two-dimensional electron gas is further formed at the interface of the channel layer and the barrier layer; wherein, the high-resistance layer at least serves as an in-situ passivation layer, and the grid electrode is distributed on the high-resistance layer.
Wherein the high resistance layer, the channel layer and the barrier layer are formed by one time of epitaxial growth.
In some embodiments, the barrier layer further has an insulating dielectric layer formed thereon, the insulating dielectric layer being bonded to the substrate.
The material of the insulating dielectric layer may be known in the art, and may be S, for exampleiO2、Si3N4Or AlN, etc., without being limited thereto. Further, the thickness of the insulating medium layer can be 200nm-1000 nm.
In some embodiments, the insulating dielectric layer and the substrate are bonded by a bonding process. The bonding process may be a metal bonding or an organic bonding, for example, an Au-Au bonding or an HSQ (hydrogen silsesquioxane) adhesive bonding.
In some embodiments, the substrate may be selected from a Si substrate, a sapphire substrate, a silicon carbide substrate, a diamond substrate, or the like, but is not limited thereto.
In some embodiments, the barrier layer is grown with a capping layer having an insulating dielectric layer formed thereon.
The high-resistance layer, the channel layer, the barrier layer and the cap layer are formed by one-time epitaxial growth.
In some embodiments, the source and drain form ohmic contacts with the channel layer.
In some embodiments, the material of the channel layer includes GaN, but is not limited thereto.
In some embodiments, the channel layer may have a thickness of 20-100 nm.
In some embodiments, the material of the barrier layer includes AlGaN, and is not limited thereto.
In some embodiments, the barrier layer has a thickness of 15-35 nm.
In some embodiments, the material of the high resistance layer comprises high resistance (Al) GaN (Al)xGa1-xN, 0 ≦ x ≦ 1), and is not limited thereto.
In some embodiments, the thickness of the high resistance layer may be 20nm to 500 nm.
In some embodiments, the material of the cap layer includes GaN, but is not limited thereto.
In some embodiments, the cap layer may have a thickness of 2-5 nm.
Furthermore, the materials of the structural layers such as the channel layer, the barrier layer, the high-resistance layer and the like can also be other III-V group semiconductor materials.
In some embodiments, an intervening layer is also disposed between the channel layer and the barrier layer. The material of the insertion layer includes, but is not limited to, AlN and the like. Further, the thickness of the insertion layer may also be known in the art, and may be, for example, 1-10 nm.
In some embodiments, the gate region of the high resistance layer is formed with a recess structure, and the gate is at least partially disposed within the recess structure.
Further, the N-plane GaN HEMT device may further comprise other structural layers or functional parts known to those skilled in the art.
Furthermore, the materials, sizes, etc. of the source, the drain, and the gate may also be known in the art, and the arrangement manner may also be adjusted according to actual requirements, for example, the gate may be distributed between the source and the drain and close to the source.
Another aspect of the embodiments of the present application provides a method of manufacturing the N-plane GaN HEMT device, including:
at least growing a buffer layer, a high-resistance layer, a channel layer and a barrier layer on a substrate in sequence to obtain an epitaxial structure;
separating the substrate from the epitaxial structure and removing at least the buffer layer;
and manufacturing a source electrode, a drain electrode and a grid electrode, distributing the grid electrode on the high-resistance layer, and electrically contacting the source electrode, the drain electrode and the channel layer.
Wherein the substrate may be separated from the epitaxial structure by dry etching, wet etching, or a combination thereof, as is known in the art.
In some embodiments, the manufacturing method specifically includes: a buffer layer, a high-resistance layer, a channel layer, a barrier layer and a cap layer are sequentially grown on a substrate, and an insulating medium layer is grown on the cap layer.
In some embodiments, the manufacturing method specifically includes: and growing a nucleation layer, a buffer layer, a high-resistance layer, a channel layer, a barrier layer and a cap layer on the substrate in sequence, and growing an insulating medium layer on the cap layer.
Wherein, the nucleation layer, the buffer layer, the high resistance layer, the channel layer, the barrier layer and the cap layer can be formed by the epitaxial growth known in the field such as MOCVD, MBE and the like.
Wherein the insulating dielectric layer can be formed by depositing by LPCVD, PECVD and other methods known in the art.
In some embodiments, the manufacturing method further comprises: and bonding the insulating medium layer with the substrate.
In some embodiments, the manufacturing method further comprises: and etching to remove the buffer layer and part of the high-resistance layer, and then manufacturing a source electrode, a drain electrode and a grid electrode on the remaining high-resistance layer.
In some embodiments, the manufacturing method further comprises: and performing active region mesa isolation on the high-resistance layer.
The electrical isolation of the source region may be achieved by ion implantation or ICP etching, but is not limited thereto.
The source, drain and gate electrodes may be fabricated by a method known in the art, such as photolithography of the high resistance layer as an in-situ passivation layer, followed by formation of the source, drain and gate electrodes by magnetron sputtering or other metal evaporation-stripping processes.
And forming ohmic contact between the source electrode and the drain electrode and the channel layer and between the source electrode and the drain electrode and the cap layer by adopting annealing and other modes.
The manufacturing method of the N-surface GaN HEMT device provided by the embodiment of the invention adopts the transfer technology to replace direct growth to obtain the high-quality N-surface GaN material, has simple process and good controllability, and can utilize high-resistance (Al) GaN formed by primary epitaxial growth with the channel layer, the barrier layer and the like as the in-situ passivation layer, thereby reducing or even avoiding the damage of etching to the GaN-AlGaN heterojunction on one hand, maintaining the high two-dimensional electron gas mobility and the carrier concentration, and avoiding the secondary growth of the passivation layer to introduce the surface state to deteriorate the performance of the device on the other hand.
The technical solutions and the working principles of the present application will be further explained with reference to the drawings and several specific embodiments, but it should not be understood that the scope of the subject matter of the present application is limited to the following embodiments. Various substitutions and alterations can be made without departing from the technical idea of the application and according to the common technical knowledge and the conventional means in the field, and all the substitutions and alterations are included in the protection scope of the application.
Fig. 3 shows an N-plane GaN HEMT device according to an exemplary embodiment of the present invention, which includes a high resistance layer 1, a channel layer 2, and a barrier layer 3 formed by one epitaxial growth, wherein the channel layer 2 and the barrier layer 3 cooperate to form a heterojunction, a two-dimensional electron gas 9(2DEG) is formed in the heterojunction, an insulating dielectric layer 4 is further formed on the barrier layer 3, and the insulating dielectric layer 4 is bonded to a substrate 5. The gate region of the high-resistance layer 1 is formed with a groove structure, the gate 6 is arranged in the groove structure, and the source 7 and the drain 8 both penetrate through the high-resistance layer 1 and form ohmic contact with the channel layer 2. The gate 6 is distributed between the source 7 and the drain 8. The source electrode 7 and the drain electrode 8 are electrically connected to each other through the 2 DEG.
Referring to fig. 4, a method for manufacturing an N-plane GaN HEMT device in the exemplary embodiment may include the following steps:
epitaxially growing a buffer layer 10, a high-resistance layer 1, a channel layer 2 and a barrier layer 3 on a substrate 11 (a cap layer can also be epitaxially grown on the barrier layer at one time, which is not shown in the figure);
depositing an insulating medium layer 4 on the barrier layer;
removing the substrate and the buffer layer by an etching process to expose the high-resistance layer (or removing part of the high-resistance layer to thin the high-resistance layer);
and manufacturing source, drain and grid electrodes 6, 7 and 8 on the high-resistance layer, and bonding the insulating medium layer 4 and the substrate 5.
In a more specific example, referring to fig. 5, a method for fabricating an N-plane GaN HEMT device with a high resistance (Al) GaN in-situ passivation layer based on a transfer technique includes the steps of:
s1: selecting a Si (111) substrate;
s2: growing a 100-200nmAlN nucleating layer, a 1000-2000nmAlGaN buffer layer, a high-resistance (Al) GaN layer, a 50-100nm GaN channel layer, a 1nm AlN insert layer, a 25nm AlGaN barrier layer and a 2nm GaN cap layer on a substrate in sequence by using MOCVD equipment;
s3: growing an insulating dielectric layer of 200nm-1000nm on the cap layer;
s4: preparing a semiconductor wafer as a substrate, and bonding the insulating medium layer and the substrate through a bonding process;
s5: etching and stripping the Si substrate by combining dry etching with wet etching;
s6: removing the AlN nucleating layer, the AlGaN buffer layer and part of the high-resistance (Al) GaN layer by an ICP dry etching mode, and remaining the 20nm-500nm high-resistance (Al) GaN layer;
s7: performing active region mesa isolation on the high-resistance (Al) GaN layer;
s8: manufacturing a source-drain ohmic contact electrode on the high-resistance (Al) GaN layer;
s9: making a gate metal electrode on the high-resistance (Al) GaN layer;
further, step S3 may include: growing SiO by PECVD or LPCVD2、Si3N4Or an insulating medium layer made of AlN or the like;
further, step S4 may include:
(1) the substrate can be selected from a Si substrate, a sapphire substrate, a silicon carbide substrate or a diamond substrate;
(2) the bonding process can adopt Au-Au bonding or HSQ (hydrogen silsesquioxane ethylene oxide) glue bonding.
The Au — Au bonding may specifically include:
firstly, growing 200nm SiO on the surface of a substrate2A medium;
secondly, growing 30nm/500nm Ti/Au metal on two sides of the substrate and the insulating medium layer respectively;
bonding the substrate and the insulating medium layer by using a bonding machine.
The HSQ adhesive bonding may specifically include:
uniformly coating HSQ glue on the surface of a substrate by using a glue homogenizing machine;
uniformly coating HSQ glue on the surface of the insulating medium layer by using a glue homogenizing machine;
thirdly, pre-baking the coated HSQ adhesive for 1min at 250 ℃ to remove the organic solvent;
and fourthly, bonding the substrate and the insulating medium layer through glue, then pressurizing, heating to 400 ℃, and carrying out hot-press bonding for 60 min.
Further, step S5 may include:
(1) etching the Si substrate by using a deep silicon etching machine in a dry method until the residual thickness of the Si substrate is 100 mu m;
(2) adding nitric acid: hydrofluoric acid: and preparing a Si etching solution with the volume ratio of acetic acid being 1:1:1, removing the residual Si substrate in a wet etching mode, and obtaining the residual GaN HEMT epitaxial structure.
Further, step S7 may include:
(1) etching an electrically isolated region of an active region on the high-resistance (Al) GaN layer;
(2) ion implantation or ICP etching can be selected to realize the electric isolation of the active area;
(3) the ICP etching mode is to etch the high-resistance (Al) GaN layer, the GaN channel layer, the AlN insert layer, the AlGaN barrier layer and the GaN cap layer corresponding to the electric isolation region in sequence to complete the mesa isolation of the active region.
The ion implantation method may specifically be: f ion implantation is adopted, and three times of implantation are carried out according to different implantation energies and measurement, so that the electrical isolation of the high-resistance (Al) GaN layer, the GaN channel layer, the AlN insert layer, the AlGaN barrier layer and the GaN cap layer is realized.
Further, step S8 may include:
(1) photoetching source electrode and drain electrode regions on the high-resistance (Al) GaN layer;
(2) etching the source and drain regions to the AlGaN barrier layer to form a groove;
(3) and carrying out metal evaporation and metal stripping on the groove region to form the source electrode and the drain electrode.
Further, step S9 may include:
(1) photoetching a gate electrode region on the high-resistance (Al) GaN layer;
(2) etching the grid region until a residual 20nm high-resistance (Al) GaN layer is formed, and forming a groove;
(3) and carrying out metal evaporation and metal stripping in the groove region to form the gate electrode.
In the specific embodiment, direct growth is replaced by a transfer technology, so that a high-quality N-surface GaN material can be easily and controllably obtained, wherein high-resistance (Al) GaN is used as an in-situ passivation layer, so that on one hand, the damage of etching on a GaN-AlGaN heterojunction is effectively reduced, the high two-dimensional electron gas mobility and the carrier concentration can be maintained, on the other hand, the problem that the performance of the device is deteriorated due to the introduction of a secondary growth passivation layer is avoided, and the obtained N-surface GaN HEMT device has various remarkably improved performances.
While the application has been described with reference to illustrative embodiments, it will be understood by those skilled in the art that various other changes, omissions or additions may be made and substantial equivalents may be substituted for elements thereof without departing from the spirit and scope of the application. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the application without departing from the scope thereof. Therefore, it is intended that the present application not be limited to the particular embodiments disclosed for carrying out the present application, but that the present application will include all embodiments falling within the scope of the appended claims.

Claims (10)

1. An N-face GaN HEMT device is characterized by comprising an epitaxial structure, and a source electrode, a drain electrode and a grid electrode which are matched with the epitaxial structure; the epitaxial structure comprises a high-resistance layer, a channel layer and a barrier layer which are sequentially grown and formed along a set direction, and two-dimensional electron gas is further formed at the interface of the channel layer and the barrier layer; wherein, the high-resistance layer at least serves as an in-situ passivation layer, and the grid electrode is distributed on the high-resistance layer.
2. The N-face GaN HEMT device of claim 1, wherein: an insulating medium layer is further formed on the barrier layer and combined with the substrate.
3. The N-face GaN HEMT device of claim 2, wherein: and the insulating medium layer and the substrate are bonded through a bonding process.
4. The N-face GaN HEMT device of claim 2, wherein: and a cap layer grows on the barrier layer, and an insulating dielectric layer is formed on the cap layer.
5. The N-face GaN HEMT device of claim 1, wherein: the high-resistance layer, the channel layer and the barrier layer are formed by one-time epitaxial growth; and/or the source electrode and the drain electrode form ohmic contact with the channel layer; and/or the thickness of the high-resistance layer is 20nm-500 nm; and/or the thickness of the channel layer is 20-100 nm; and/or the barrier layer has a thickness of 15-35 nm; and/or the material of the channel layer comprises GaN; and/or the barrier layer is made of AlGaN; and/or the material of the high-resistance layer comprises AlxGa1-xN, 0 ≦ x ≦ 1; and/or an insertion layer is also distributed between the channel layer and the barrier layer, and the material of the insertion layer comprises AlN; and/or a gate region of the high-resistance layer is formed with a groove structure, and the gate is at least partially arranged in the groove structure.
6. The method of fabricating the N-face GaN HEMT device of any one of claims 1-5, comprising:
at least growing a buffer layer, a high-resistance layer, a channel layer and a barrier layer on a substrate in sequence to obtain an epitaxial structure;
separating the substrate from the epitaxial structure and removing at least the buffer layer;
and manufacturing a source electrode, a drain electrode and a grid electrode, distributing the grid electrode on the high-resistance layer, and electrically contacting the source electrode, the drain electrode and the channel layer.
7. The manufacturing method according to claim 6, characterized by specifically comprising: a buffer layer, a high-resistance layer, a channel layer, a barrier layer and a cap layer are sequentially grown on a substrate, and an insulating medium layer is grown on the cap layer.
8. The method of manufacturing according to claim 7, further comprising: and bonding the insulating medium layer with the substrate.
9. The method of manufacturing according to claim 6, further comprising: and etching to remove the nucleation layer and part of the high-resistance layer, and then manufacturing a source electrode, a drain electrode and a grid electrode on the remaining high-resistance layer.
10. The method of manufacturing according to claim 6 or 9, further comprising: and performing active region mesa isolation on the high-resistance layer.
CN202011319555.4A 2020-11-23 2020-11-23 N-surface GaN HEMT device and manufacturing method thereof Pending CN112420827A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113471284A (en) * 2021-07-01 2021-10-01 广东省科学院半导体研究所 Preparation method of N-polarity GaN transistor structure and semiconductor structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113471284A (en) * 2021-07-01 2021-10-01 广东省科学院半导体研究所 Preparation method of N-polarity GaN transistor structure and semiconductor structure
WO2023273252A1 (en) * 2021-07-01 2023-01-05 广东省科学院半导体研究所 Manufacturing method for n-polar gan transistor structure and semiconductor structure

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