CN210866192U - Gallium nitride epitaxial layer and semiconductor device - Google Patents

Gallium nitride epitaxial layer and semiconductor device Download PDF

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CN210866192U
CN210866192U CN201921614642.5U CN201921614642U CN210866192U CN 210866192 U CN210866192 U CN 210866192U CN 201921614642 U CN201921614642 U CN 201921614642U CN 210866192 U CN210866192 U CN 210866192U
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layer
anode
contact hole
cathode
metal
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林信南
刘美华
刘岩军
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SHENZHEN JINGXIANG TECHNOLOGY CO LTD
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SHENZHEN JINGXIANG TECHNOLOGY CO LTD
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • H01L29/66204—Diodes
    • H01L29/66212—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

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Abstract

The utility model discloses a gallium nitride epitaxial layer, semiconductor device relates to semiconductor technology field. The utility model discloses a semiconductor device includes: the device comprises a semiconductor substrate, a first buffer layer, a post-processing layer, a second buffer layer, a barrier layer, a passivation layer, a first anode contact hole, a first anode, a dielectric layer, a second anode contact hole, a second anode, a cathode contact hole, a cathode, a protective layer, an anode opening hole, anode conducting metal, a cathode opening hole, cathode conducting metal and a field plate layer. The utility model provides a have the problem of leakage current between buffer layer and the semiconductor substrate interface.

Description

Gallium nitride epitaxial layer and semiconductor device
Technical Field
The utility model relates to the field of semiconductor technology, especially, relate to a gallium nitride epitaxial layer and semiconductor device.
Background
A semiconductor device is a semiconductor device made by contacting a semiconductor layer with a metal. Compared with the traditional semiconductor diode, the semiconductor diode has the characteristic of extremely short reverse recovery time, so that the semiconductor device is widely applied to circuits such as a switching power supply, a frequency converter, a driver and the like. The gallium nitride material is a third generation wide bandgap semiconductor material, and has the characteristics of large bandgap width, high electronic saturation rate, high breakdown electric field, high thermal conductivity, corrosion resistance, radiation resistance and the like, so that the gallium nitride material becomes an optimal material for manufacturing short-wave photoelectronic devices and high-voltage high-frequency high-power devices. In conclusion, the semiconductor device prepared by using the gallium nitride material combines the advantages of the semiconductor device and the gallium nitride material, has the advantages of high switching speed, high field intensity, good thermal performance and the like, and has good development prospect in the market of power rectifiers.
However, in the conventional semiconductor device structure, a large number of defects exist in the barrier layer due to lattice mismatch between the substrate and the barrier layer, so that the performance and the service life of the semiconductor device are affected. In the prior art, a buffer layer is often formed between a semiconductor substrate and a barrier layer to offset the influence caused by partial lattice mismatch, but the buffer layer has a limited function and cannot completely offset the influence caused by lattice mismatch, and a leakage current problem exists between the buffer layer and the interface of the semiconductor substrate, so that the performance and the service life of a semiconductor device cannot be fully improved.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a gallium nitride epitaxial layer and semiconductor device grows multilayer buffer layer and aftertreatment layer through PVD, has solved when only having the buffer layer between semiconductor substrate and the barrier layer, has the problem of leakage current between buffer layer and the semiconductor substrate interface.
In order to solve the technical problem, the utility model discloses a realize through following technical scheme:
the utility model provides a semiconductor device, it includes:
a semiconductor substrate;
a first buffer layer disposed on the semiconductor substrate;
the post-processing layer is arranged on one side, far away from the semiconductor substrate, of the first buffer layer;
the second buffer layer is arranged on one side, far away from the first buffer layer, of the post-treatment layer;
a barrier layer disposed on a side of the second buffer layer away from the post-treatment layer;
a passivation layer disposed on a side of the barrier layer away from the second buffer layer;
a first anode contact hole penetrating the passivation layer into the barrier layer;
a first anode disposed within the first anode contact hole;
the dielectric layer is arranged on one side of the passivation layer far away from the barrier layer and between the first anode and the barrier layer;
the second anode contact hole penetrates through the dielectric layer and the passivation layer and extends into the barrier layer;
a second anode disposed within the second anode contact hole;
a cathode contact hole penetrating the dielectric layer and the passivation layer;
the cathode is arranged on the dielectric layer and in the cathode contact hole;
a protective layer disposed over the first anode, the second anode, the cathode, and the dielectric layer;
an anode opening through the protective layer to expose the first anode and the second anode;
the anode conducting metal is arranged on one side of the protective layer, which is far away from the dielectric layer, and is connected with the first anode and the second anode;
a cathode opening through the protective layer to expose the cathode;
the cathode conducting metal is arranged on one side, far away from the dielectric layer, of the protective layer, and the cathode conducting metal is connected with the cathode;
a field plate layer disposed on the protective layer, the field plate layer being connected with the anode conductive metal, wherein the anode conductive metal, the cathode conductive metal, and the field plate layer are formed simultaneously.
In an embodiment of the present invention, the first anode and the second anode include a first metal layer and a second metal layer, wherein the first metal layer is disposed on one side of the passivation layer away from the dielectric layer and extends into the first anode contact hole and the second anode contact hole to cover the dielectric layer and the second anode contact hole bottom, and the second metal layer is disposed on the first metal layer and fills the first anode contact hole and the second anode contact hole.
In one embodiment of the invention, the first anode and the second anode are formed by a first number of metal layers stacked, the cathode is formed by a second number of metal layers stacked, and the first number is greater than the second number.
In one embodiment of the present invention, the post-treatment layer is an aluminum oxide layer.
In one embodiment of the invention, the thickness of the post-treatment layer is 0.5-2 nm.
The utility model also provides a gallium nitride epitaxial layer, it includes:
a semiconductor substrate;
a first buffer layer disposed on the semiconductor substrate;
the post-processing layer is arranged on one side, far away from the semiconductor substrate, of the first buffer layer;
the second buffer layer is arranged on one side, far away from the first buffer layer, of the post-treatment layer;
a barrier layer disposed on a side of the second buffer layer away from the post-treatment layer.
In one embodiment of the present invention, the first buffer layer is an aluminum nitride layer.
In one embodiment of the present invention, the thickness of the first buffer layer is 10-300 nm.
In one embodiment of the present invention, the post-treatment layer is an aluminum oxide layer.
In one embodiment of the invention, the thickness of the post-treatment layer is 0.5-2 nm.
The utility model discloses a PVD grows first buffer layer and aftertreatment layer, obtains the better first buffer layer of quality, makes things convenient for preparation and the application of follow-up gallium nitride base semiconductor device. When the buffer layer is of a multilayer structure, lattice constants of different layers are gradually changed, the lattice constant near the surface of the semiconductor substrate is closest to the lattice constant of the semiconductor substrate, and the lattice constant of the top layer is closest to the lattice constant of a subsequently formed barrier layer, so that lattice defects caused by the lattice constant of the semiconductor substrate in the buffer layer can be reduced, the interface state on the interface between the buffer layer and the semiconductor substrate is reduced, and the interface leakage current on the interface is reduced. By arranging the dielectric layer, the area of the anode is increased, the reverse leakage is greatly reduced, and the dielectric layer can be formed simultaneously with a gate dielectric layer of a GaN HEMT (High Electron Mobility Transistor) and is compatible with a CMOS (complementary metal oxide semiconductor) process line; in addition, by adding the anode conducting metal, the cathode conducting metal and the field plate layer structure, the depletion region of the gallium nitride-based semiconductor device is expanded, and the voltage resistance of the gallium nitride-based semiconductor device is improved.
Of course, it is not necessary for any particular product to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a gallium nitride epitaxial layer according to the present invention;
FIG. 2 is a flow chart of a method for preparing the GaN epitaxial layer of FIG. 1;
FIG. 3 is a schematic view of a semiconductor device obtained by using the gallium nitride epitaxial layer of FIG. 1;
FIG. 4 is a flow chart of a method of fabricating the semiconductor device of FIG. 3;
fig. 5 is a schematic structural view of another semiconductor device obtained by using the gallium nitride epitaxial layer of fig. 1;
fig. 6 is a flowchart of a method of manufacturing the semiconductor device of fig. 5.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.
Gallium nitride materials have low heat generation rates and high breakdown electric fields, and are important materials for developing high-temperature high-power electronic devices and high-frequency microwave devices. The gallium nitride material can be used for preparing novel devices such as metal field effect transistors (MESFETs), Heterojunction Field Effect Transistors (HFETs), modulation-doped field effect transistors (MODFETs) and the like. The modulation doped AlGaN/GaN structure has high electron mobility (2000 cm)2V.s), high saturation velocity (1 × 107cm/s), low dielectric constant, and a wide bandgap (3.4eV) for gallium nitride, sapphire, and silicon carbideAnd the materials are used as the substrate, so that the heat dissipation performance is good, and the device can work under the condition of high power.
The utility model provides a gallium nitride epitaxial layer and semiconductor device can use can also use on the radio frequency semiconductor device on the power semiconductor device.
Referring to fig. 1, the present invention provides a gan epitaxial layer, which may include: the semiconductor device includes a semiconductor substrate 1300, a first buffer layer 1301, a post-treatment layer 1302, a second buffer layer 1303, and a barrier layer 1304.
As shown in fig. 1, a first buffer layer 1301 is disposed on a semiconductor substrate 1300, a post-processing layer 1302 is disposed on a side of the first buffer layer 1301 away from the semiconductor substrate 1300, a second buffer layer 1303 is disposed on a side of the post-processing layer 1302 away from the first buffer layer 1301, and a barrier layer 1304 is disposed on a side of the second buffer layer 1303 away from the post-processing layer 1302. The material of the semiconductor substrate 1300 is, for example, one of sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, aluminum nitride, or gallium nitride. The first buffer layer 1301 may be, for example, an aluminum nitride layer, and the thickness of the first buffer layer 1301 is, for example, 10nm to 300 nm. The post-treatment layer 1302 may be, for example, a thin layer of aluminum oxide (Al2O3), and the post-treatment layer 1302 may have a thickness of 0.5-2 nm. The second buffer layer 1303 may be, for example, a gallium nitride layer or an aluminum gallium nitride layer. The material of the barrier layer 1304 is, for example, a gallium nitride layer or an aluminum gallium nitride layer.
Referring to fig. 1, the present invention uses PVD to grow the first buffer layer 1301 and the post-treatment layer 1302, so as to obtain the first buffer layer 1301 with better quality, thereby facilitating the preparation and application of the subsequent gallium nitride-based semiconductor device.
As shown in fig. 1, when the buffer layer has a multi-layer structure, lattice constants of different layers gradually change, and the lattice constant near the surface of the semiconductor substrate 1300 is closest to the lattice constant of the semiconductor substrate 1300, and the lattice constant of the top layer is closest to the lattice constant of the subsequently formed barrier layer 1304, so that lattice defects in the buffer layer due to the lattice constant of the semiconductor substrate 1300 can be reduced, interface states at the interface between the buffer layer and the semiconductor substrate 1300 can be reduced, and interface leakage current at the interface can be reduced.
Referring to fig. 2, a method for fabricating a gan epitaxial wafer according to the present embodiment includes the following steps:
referring to fig. 2, in step S1301, a material of the semiconductor substrate 1300 is, for example, one of sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, aluminum nitride, or gallium nitride, a hydrofluoric acid solution is used to treat and remove an oxide layer on the surface of the semiconductor substrate 1300, and then a PVD process is used to deposit a first buffer layer 1301, for example, a single-layer aluminum nitride buffer layer, with a thickness range of, for example, 10-50nm, specifically, the epitaxial semiconductor substrate 1300 (here, for example, a Si substrate) is placed on a SiC tray, and the tray is placed into a PVD sputtering machine and transferred to a machine deposition chamber. After the semiconductor substrate 1300 is placed, the deposition chamber is evacuated, and the semiconductor substrate 1300 is heated while the chamber is evacuated. Background vacuum is drawn below, for example, 10-5-10-7The temperature is stabilized at 400 to 600 ℃ for Torr, and the semiconductor substrate 1300 is baked for 1 to 10 minutes, for example. After the semiconductor substrate 1300 is baked, Ar, N2, O2, Ar: the flow ratio of N2 is, for example, 10:2 to 1:1, and the flow ratio of O2 is, for example, 0to 5% of the sum of the flows of Ar and N2. The total gas flow is preferably maintained at a PVD deposition chamber pressure of, for example, 2-8 mTorr. Meanwhile, the heating temperature of the semiconductor substrate 1300 is set to the deposition temperature, and the deposition temperature is preferably within a range of 400 to 600 ℃. And introducing reaction gas, enabling the deposition temperature to be stable for 10-60 seconds, and then turning on a sputtering power supply to sputter the Al target, wherein the AlN crystal film doped with O is deposited on the semiconductor substrate 1300. The sputtering power can be set, for example, to 1KW to 10KW depending on the requirement of the deposition rate, and the sputtering time can be set, for example, to 10 seconds to 1000 seconds depending on the thickness.
Referring also to FIG. 2, in step S1302, an ALD process is further employed to form a post-treatment layer 1302, such as Al2O3Layer, ALD chamber evacuated to, for example, 0.05MPa-0.5MPa, temperature raised to, for example, 100 deg.C, precursors of trimethylaluminum and highly purified water, deposition thickness of, for example, 0.5-2nm, deposition time profileSuch as 3-25 min.
Referring to fig. 2, in step S1303, a second buffer layer 1303, such as a gan buffer layer, is further formed on the post-processing layer 1302, wherein the gan buffer layer is formed by a two-step method, the temperature is controlled at 450-600 ℃, the pressure is controlled at 200-500torr, a gan nucleation layer is grown, and then the temperature is raised to 950-1200 ℃ to grow a three-dimensional and two-dimensional gan cladding layer, wherein the nucleation layer and the subsequent three-dimensional gan are collectively referred to as gan buffer layer.
Referring to fig. 2, in step S1304, a barrier layer 1304, such as a gan barrier layer 1304, is grown in the last step, wherein the gan barrier layer 1304 is grown on the gan buffer layer at a temperature of 950 ℃ to 1300 ℃ and a pressure of 70torr to 200torr, and the thickness of the gan barrier layer 1304 is 50nm to 500nm, for example.
Referring to fig. 2, after the epitaxy is finished, the temperature is decreased to obtain the gan-based epitaxial wafer.
Referring to fig. 2, the controlling of the temperature and the pressure refers to controlling the temperature and the pressure in a reaction chamber for growing an epitaxial wafer, and more particularly, to controlling the temperature and the pressure in a reaction chamber of a Metal Organic Chemical Vapor Deposition (MOCVD) apparatus. During implementation, trimethyl gallium or triethyl gallium is used as a gallium source, high-purity ammonia gas is used as a nitrogen source, trimethyl indium is used as an indium source, trimethyl aluminum is used as an aluminum source, silane is used as a silicon source, tetramethyl germanium is used as a germanium source, and cyclopentadienyl magnesium is used as a magnesium source.
Referring to fig. 3, the present invention further provides a semiconductor device based on a gan epitaxial layer, for example, including: the semiconductor device comprises a semiconductor substrate 1300, a first buffer layer 1301, a post-processing layer 1302, a second buffer layer 1303, a barrier layer 1304, a passivation layer 603, a first anode contact hole 613, a first anode 604, a dielectric layer 605, a second anode contact hole 614, a second anode 606, a cathode contact hole 617, a cathode 607, a protective layer 608, a field plate layer 609, an anode opening 616, an anode conducting metal 610, a cathode opening 617 and a cathode conducting metal 611.
Referring to fig. 3, a first buffer layer 1301 is disposed on a semiconductor substrate 1300, a post-processing layer 1302 is disposed on a side of the first buffer layer 1301 away from the semiconductor substrate 1300, a second buffer layer 1303 is disposed on a side of the post-processing layer 1302 away from the first buffer layer 1301, a barrier layer 1304 is disposed on a side of the second buffer layer 1303 away from the post-processing layer 1302, and a passivation layer 603 is disposed on a side of the barrier layer 1304 away from the second buffer layer 1303. The first anode contact hole 613 penetrates through the passivation layer 603 and extends into the barrier layer 1304, and the dielectric layer 605 is disposed on a side of the passivation layer 603 away from the barrier layer 1304 and within the first anode contact hole 613. The second anode contact hole 614 penetrates the dielectric layer 605, the passivation layer 603, and extends into the barrier layer 1304. The first anode 604 and the second anode 606 include a first metal layer disposed on a side of the dielectric layer 605 away from the passivation layer 603 and extending into the first anode contact hole 613 and the second anode contact hole 614 to cover the dielectric layer 605 and the bottom of the second anode contact hole 614 at the bottom of the first anode contact hole 613, and a second metal layer disposed on the first metal layer and filling the first anode contact hole 613 and the second anode contact hole 614. The cathode contact hole 617 penetrates the dielectric layer 605 and the passivation layer 603. Cathode 607 is disposed on dielectric layer 605 and fills cathode contact hole 617. A protective layer 608 is disposed over the anode, cathode 607, and dielectric layer 605. An anode opening 616 extends through the protective layer 608 to expose the anode. A cathode opening 617 extends through the protective layer 608 to expose the cathode 607. The anode via metal 610 is disposed on a side of the protection layer 608 away from the dielectric layer 605, and the anode via metal 610 fills the anode opening 616. Cathode via metal 611 is disposed on a side of the passivation layer 608 away from the dielectric layer 605, and the cathode via metal 611 fills the cathode opening 617. A field plate layer 609 is disposed on the protective layer 608 in a region between the anode conductive metal 610 and the cathode conductive metal 611 and connected to the anode conductive metal 610, wherein the anode conductive metal 610, the cathode conductive metal 611 and the field plate layer 609 may be formed simultaneously by an etching process.
Referring to fig. 3, in the embodiment, a material of the dielectric layer 605 is, for example, one of silicon nitride, silicon oxide and tetraethyl orthosilicate, the first anode contact hole 613 and the second anode contact hole 614 are, for example, a stripe-shaped groove, a material of a first metal layer included in the first anode 604 and the second anode 606 may be a titanium metal layer or a titanium nitride metal layer, and a second metal layer included in the first anode 604 and the second anode 606 is a multilayer structure, which may include, but is not limited to, a titanium metal layer, a metal aluminum layer, a metal titanium layer and a metal titanium nitride layer stacked in sequence. The cathode 607 and the second metal layer are formed simultaneously, for example, in the same e-beam evaporation process, and are all multi-layered metal structures. In other words, the first anode 604 and the second anode 606 are composed of a first number of metal layers stacked, the cathode 607 is composed of a second number of metal layers stacked, and the first number is larger than the second number.
Referring to fig. 4, the present invention further provides a method for manufacturing a semiconductor device, the method comprising the following steps:
in step S601, a first buffer layer, a post-treatment layer, a second buffer layer, and a barrier layer 1304 are sequentially formed on the semiconductor substrate 1300;
in step S602, a passivation layer 603 is formed on the barrier layer 1304;
in step S603, patterning the passivation layer 603 and the barrier layer 1304 to form a first anode contact hole 613, wherein the first anode contact hole 613 penetrates through the passivation layer 603 and protrudes into the barrier layer 1304;
in step S604, a dielectric layer 605 is formed on the passivation layer 603 and in the first anode contact hole 613, and the dielectric layer 605, the passivation layer 603 and the barrier layer 1304 are patterned to form a second anode contact hole 614 penetrating through the dielectric layer 605, the passivation layer 603 and extending into the barrier layer 1304;
in step S605, forming a first metal layer on the dielectric layer 605 and in the first and second anode contact holes 613 and 614, and patterning the first metal layer to obtain the first metal layer located in the first and second anode contact holes 613 and 614;
in step S606, the dielectric layer 605 and the passivation layer 603 are patterned to form cathode contact holes 615 penetrating through the dielectric layer 605 and the passivation layer 603;
in step S607, forming a second metal layer on the dielectric layer 605 and the first metal layer located in the first anode contact hole 613 and the second anode contact hole 614 and in the cathode contact hole 615, and patterning the second metal layer to obtain a second metal layer and a cathode 607 in the first anode contact hole 613 and the second anode contact hole 614; wherein the cathode 607 fills the cathode contact hole 615, the first metal layer and the second metal layer are included in the first anode 604 and the second anode 606;
in step S608, a protective layer 608 is formed on the dielectric layer 605, the first anode 604, the second anode 606, and the cathode 607;
in step S609, the protection layer 608 is patterned to form an anode opening 616 and a cathode opening 617 through the protection layer 608 to expose the first anode 604, the second anode 606 and the cathode 607, respectively;
in step S610, a third metal layer is formed on the protection layer 608 and the anode opening 616 and the cathode opening 617, and the third metal layer is patterned to form a field plate layer 609, an anode conductive metal 610 filling the anode opening 616, and a cathode conductive metal 611 filling the cathode opening 617, wherein the field plate layer 609 is located in a region between the anode conductive metal 610 and the cathode conductive metal 611 and is connected to the anode conductive metal 610.
Specifically, taking the preparation of the semiconductor device in this embodiment as an example, in step S301, an oxide layer on the surface of the semiconductor substrate 1300 is removed by, for example, a hydrofluoric acid solution treatment, and then a first buffer layer 1301, for example, a single-layer aluminum nitride buffer layer, is deposited by a PVD process, with a thickness range of, for example, 10 to 300nm, specifically, an epitaxial-level substrate (here, for example, a Si substrate) is placed on a tray made of SiC material, and the tray is placed in a PVD sputtering machine and transferred to a machine deposition chamber. And after the substrate is placed, vacuumizing the deposition chamber, and heating the substrate to raise the temperature while vacuumizing. Background vacuum is drawn below, for example, 10-5-10-7The substrate is baked while the temperature is stabilized at, for example, 400 to 600 ℃ under Torr for, for exampleIs 1 to 10 minutes. After the substrate is baked, Ar and N are introduced2、O2，Ar：N2The flow rate ratio is, for example, 10:2 to 1:1, O2Flow rates of Ar and N2The sum of the flow rates is, for example, 0to 5%. The total gas flow is preferably maintained at a PVD deposition chamber pressure of, for example, 2-8 mTorr. Meanwhile, the heating temperature of the substrate is set to the deposition temperature, and the preferred deposition temperature range is, for example, 400-600 ℃. And introducing reaction gas, enabling the deposition temperature to be stable for 10-60 seconds, and then switching on a sputtering power supply to sputter the Al target material, wherein the AlN crystal film doped with O is deposited on the substrate. The sputtering power can be set, for example, to 1KW to 10KW depending on the requirement of the deposition rate, and the sputtering time can be set, for example, to 10 seconds to 1000 seconds depending on the thickness.
In step S601, further, an atomic deposition technique (ALD) process is used to prepare a post-treatment layer 1302, such as Al2O3The layer, ALD chamber, is evacuated to, for example, 0.05MPa to 0.5MPa, the temperature is raised to, for example, 100 ℃, the precursors are trimethylaluminum and high purity water, the deposition thickness is, for example, 0.5 to 2nm, and the deposition time is, for example, 3 to 25 min.
In step S601, a PVD process is used to prepare a second buffer layer 1303, such as a gan buffer layer, on the post-processing layer 1302, wherein the gan buffer layer can be prepared by a two-step method, a gan nucleation layer is grown at a controlled temperature of, for example, 450-600 ℃ and a pressure of, for example, 200-500torr, and then a gan three-dimensional and two-dimensional cladding layer is grown at a raised temperature of 950-1200 ℃, and the nucleation layer and the subsequent three-dimensional and two-dimensional gan buffer layer are collectively referred to as gan buffer layer.
In step S601, a barrier layer 1304, such as a gan barrier layer 1304, is grown by PVD, wherein the gan barrier layer 1304 is grown on the gan buffer layer at a temperature of 950 ℃ to 1300 ℃ and a pressure of 70torr to 200torr, and the thickness of the gan barrier layer 1304 is 50nm to 500nm, for example.
In step S602, a silicon nitride passivation layer 603 is deposited on the aluminum gallium nitride layer using, but not limited to, a chemical vapor deposition process.
In step S603, the silicon nitride passivation layer 603 and the aluminum gallium nitride layer are patterned to form a first anode contact hole 613, wherein the first anode contact hole 613 penetrates through the silicon nitride passivation layer 603 and extends into the aluminum gallium nitride layer. More specifically, the steps of patterning the silicon nitride passivation layer 603 and the aluminum gallium nitride layer to form the first anode contact hole 613 are, for example: coating photoresist on the silicon nitride passivation layer 603, exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the silicon nitride passivation layer 603 and the aluminum gallium nitride layer by using the patterned photoresist layer as a mask to form a first anode contact hole 613, wherein the first anode contact hole 613 is a strip-shaped groove.
In step S604, a dielectric layer 605 is formed on the silicon nitride passivation layer 603 and in the first anode contact hole 613, and the dielectric layer 605, the silicon nitride passivation layer 603 and the aluminum gallium nitride layer are patterned to form a second anode contact hole 614 penetrating through the dielectric layer 605, the silicon nitride passivation layer 603 and extending into the aluminum gallium nitride layer. More specifically, the material of the dielectric layer 605 is, for example, one of silicon nitride, silicon oxide and ethyl orthosilicate, and the step of patterning the dielectric layer 605, the silicon nitride passivation layer 603 and the aluminum gallium nitride layer to form the second anode contact hole 614 penetrating through the dielectric layer 605, the silicon nitride passivation layer 603 and extending into the aluminum gallium nitride layer includes, for example: and coating photoresist on the dielectric layer 605, exposing and developing the photoresist to obtain a patterned photoresist layer, and etching the dielectric layer 605, the silicon nitride passivation layer 603 and the aluminum gallium nitride layer by using the patterned photoresist layer as a mask to form a second anode contact hole 614. The areas where the first anode contact hole 613 and the second anode contact hole 614 are located constitute an anode area AZ, and the first anode 604 and the second anode 606 fill the first anode contact hole 613 and the second anode contact hole 614, respectively.
In step S605, a first metal layer is formed on the dielectric layer 605 and in the second anode contact hole 614, and the first metal layer is patterned to obtain a first metal layer located in the anode region AZ. More specifically, the specific steps of obtaining the first metal layer located in the anode region AZ may be: and depositing metal in the second anode contact hole 614 and on the dielectric layer 605 by using a magnetron sputtering coating process to form a first metal layer, wherein the material of the first metal layer may be one of titanium nitride and titanium, coating a photoresist on the first metal layer, then exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the first metal layer by using the patterned photoresist layer as a mask to remove the first metal layer outside the anode region AZ so as to obtain the first metal layer located in the anode region AZ.
In step S606, the dielectric layer 605 and the silicon nitride passivation layer 603 are patterned to form cathode contact holes 615 that penetrate the dielectric layer 605 and the silicon nitride passivation layer 603. More specifically, the step of patterning the dielectric layer 605 and the silicon nitride passivation layer 603 to form the cathode contact hole 615 penetrating through the dielectric layer 605 and the silicon nitride passivation layer 603 may specifically be: a photoresist is coated on the dielectric layer 605, then the photoresist is exposed and developed to obtain a patterned photoresist layer, then the dielectric layer 605 and the silicon nitride passivation layer 603 are etched by using the patterned photoresist layer as a mask until the surface of the aluminum gallium nitride layer is exposed, a cathode contact hole 615 is formed, and the residual patterned photoresist layer is removed.
In step S607, a second metal layer is formed on the dielectric layer 605 and the first metal layer located in the anode region AZ and in the cathode contact hole 615, and the second metal layer is patterned to obtain the second metal layer of the first anode 604 and the second anode 606 and the cathode 607, wherein the cathode 607 fills the cathode contact hole 615. More specifically, the specific steps of obtaining the first anode 604, the second anode 606 and the cathode 607 may be: a titanium metal layer, an aluminum metal layer, a titanium metal layer and a titanium nitride metal layer are sequentially deposited in the dielectric layer 605, the first metal layer located in the anode region AZ and the cathode contact hole 615 by a process of, but not limited to, electron beam evaporation of metal to form a second metal layer, i.e., the second metal layer is a stacked multilayer metal structure including, but not limited to, a titanium metal layer, an aluminum metal layer, a titanium metal layer and a titanium nitride metal layer, and then the second metal layer is subjected to a photolithography and etching process to form a second metal layer of the first anode 604 and the second anode 606 and the cathode 607, more specifically, the first anode 604 and the second anode 606 include the first metal layer and the second metal layer located in the anode region AZ.
In step S608, a protective layer 608 is formed on the dielectric layer 605, the first anode 604, the second anode 606, and the cathode 607.
In step S609, the protection layer 608 is patterned to form an anode opening 616 and a cathode opening 617 through the protection layer 608 exposing the first anode 604, the second anode 606, and the cathode 607, respectively. More specifically, the step of patterning the passivation layer 608 to form the anode opening 616 and the cathode opening 617 through the passivation layer 608 may specifically be: a photoresist is coated on the protection layer 608, and then the photoresist is exposed and developed to obtain a patterned photoresist layer, and then the protection layer 608 is etched using the patterned photoresist layer as a mask until the first anode 604, the second anode 606 and the cathode 607 are exposed, an anode opening 616 and a cathode opening 617 are formed, and the residual patterned photoresist layer is removed.
In step S610, a third metal layer is formed on the protection layer 608 and within the anode opening 616 and the cathode opening 617, and the third metal layer is patterned to form a field plate layer 609, an anode via metal 610 filling the anode opening 616, and a cathode via metal 611 filling the cathode opening 617. More specifically, the steps of forming the anode conductive metal 610, the cathode conductive metal 611 and the field plate are specifically: a third metal layer, such as copper aluminum silicon (AlSiCu), is deposited on the protective layer 608 by, but not limited to, an electron beam evaporation process, and then the third metal layer is subjected to photolithography (gumming, exposure and development) and etching processes to form an anode via metal 610, a cathode via metal 611 and a field plate. Wherein the field plate layer 609 is located at a region between the anode conductive metal 610 and the cathode conductive metal 611 and outside the anode region AZ, and is connected to the anode conductive metal 610.
In summary, in the method for manufacturing a semiconductor device according to the present embodiment, a dielectric layer 605 is formed by depositing a layer of dielectric material on the surface of the silicon nitride passivation layer 603 and in the first anode contact hole 613, so that the area of the anode is increased, the reverse leakage is greatly reduced, and the dielectric layer can be formed simultaneously with the gate dielectric layer of the GaN HEMT and is compatible with the CMOS process line. In addition, by arranging the anode conducting metal 610, the cathode conducting metal 611 and the field plate layer 609, the depletion region of the semiconductor device is expanded, the electric field distribution is balanced, the electric field intensity of the main Schottky junction is reduced, and the withstand voltage of the semiconductor device is improved.
Referring to fig. 5, the present invention further provides a semiconductor device based on a gan epitaxial layer, comprising: the semiconductor device comprises a semiconductor substrate 1300, a first buffer layer 1301, a post-processing layer 1302, a second buffer layer 1303, a barrier layer 1304, a dielectric layer 705, a source 704, a drain 706 and a gate 707.
Referring to fig. 5, a first buffer layer 1301 is disposed on a semiconductor substrate 1300, a post-treatment layer 1302 is disposed on a side of the first buffer layer 1301 away from the semiconductor substrate 1300, a second buffer layer 1303 is disposed on a side of the post-treatment layer 1302 away from the first buffer layer 1301, a barrier layer 1304 is disposed on a side of the second buffer layer 1303 away from the post-treatment layer 1302, the barrier layer 1304 has a wider band gap than that of the second buffer layer 1303 and induces a 2D electron gas (2DEG) in the channel. The dielectric layer 705 is disposed on a side of the barrier layer 1304 away from the second buffer layer 1303. The source 704, the drain 706 and the gate 707 are arranged in the dielectric layer 705, the source 704, the drain 706 and the gate 707 respectively penetrate through the dielectric layer 705 and are connected with the barrier layer 1304, and a part of the source 704, the drain 706 and the gate 707 protrudes out of the top of the dielectric layer 705, wherein the gate 707 extends into the barrier layer 1304 to reach the bottom of the barrier layer 1304, the gate 707 is in a tapered structure, and the ratio of the upper edge to the lower edge of the taper is 1: 2-1: 4.
referring to fig. 5, based on the above embodiment, in the present embodiment, the source 704 and the drain 706 are composed of a third metal layer, and the third metal layer sequentially includes a first titanium metal layer, an aluminum metal layer, a second titanium metal layer, and a titanium nitride layer. The gate 707 is composed of a fourth metal layer, which is nickel or gold alloy.
Referring to fig. 5, in the invention, the first buffer layer 1301 and the post-treatment layer 1302 can be grown by PVD, so that the first buffer layer 1301 with better quality can be obtained, and the subsequent preparation and application of the gallium nitride-based semiconductor device can be facilitated.
Referring to fig. 6, the present embodiment further provides a method for manufacturing a semiconductor device, which includes the following steps:
in step 701, for example, an aluminum nitride first buffer layer 1301, an aluminum oxide post-treatment layer 1302, an aluminum gallium nitride second buffer layer 1303, and a gallium nitride barrier layer 1304 are sequentially deposited on a semiconductor substrate 1300, thereby obtaining a gallium nitride-based epitaxial wafer.
In step 702, a layer of hafnium oxide (HfO2) may then be deposited on the surface of the gan-based epitaxial wafer using a plasma enhanced chemical vapor deposition process to form a dielectric layer 705. The thickness of the hafnium oxide may be 2000 angstroms, for example.
In step 703, the dielectric layer 705 is dry etched to form a source 704 contact hole and a drain 706 contact hole that are oppositely disposed.
In step 704, a first metal is deposited in the source 704 contact holes and the drain 706 contact holes, and on the surface of the dielectric layer 705. Specifically, a magnetron sputtering coating process may be adopted to sequentially deposit a first titanium metal layer, an aluminum metal layer, a second titanium metal layer and a titanium nitride layer in the contact hole of the source 704 and the contact hole of the drain 706 and on the surface of the dielectric layer 705 to form the first metal layer, where the thickness of the first titanium metal layer may be, for example, 200 angstroms, the thickness of the aluminum metal layer may be, for example, 1200 angstroms, the thickness of the second titanium metal layer may be, for example, 200 angstroms, and the thickness of the titanium nitride layer may be, for example, 200 angstroms. The first metal is then patterned and etched to expose a portion of the surface of dielectric layer 705. Wherein the photolithography process comprises gumming, exposing and developing. Thus, the first metal layer over the contact hole of the source 704 forms the source 704 of the device, and the first metal layer over the contact hole of the drain 706 forms the drain 706 of the device.
In step 705, dry etching is performed on the exposed surface of the dielectric layer 705 and the gallium nitride layer to form a contact hole 707 for the gate. The contact hole of the gate 707 completely penetrates through the dielectric layer 705 and penetrates through the gallium nitride layer to reach the bottom of the gallium nitride layer, the gate 707 is in a conical structure, and the ratio of the upper edge to the lower edge of the conical structure is 1: 2-1: 4.
in step 706, a magnetron sputtering coating process is adopted to deposit a silicon nitride layer in the contact hole of the gate 707, wherein the silicon nitride layer is not higher than the contact hole of the gate 707, and then Ni/Au is deposited on the silicon nitride layer and on the outer edge of the contact hole of the gate 707 to be used as a second metal, wherein the thickness ratio of the Ni/Au metal is 0.01-0.04 μm/0.08-0.4 μm, so that the gate 707 is formed. Thus, the gate 707 is a composite structure having multiple materials.
The preferred embodiments of the present invention disclosed above are intended only to help illustrate the present invention. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best understand the invention for and utilize the invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims (10)

1. A semiconductor device, comprising:
a semiconductor substrate;
a first buffer layer disposed on the semiconductor substrate;
the post-processing layer is arranged on one side, far away from the semiconductor substrate, of the first buffer layer;
the second buffer layer is arranged on one side, far away from the first buffer layer, of the post-treatment layer;
a barrier layer disposed on a side of the second buffer layer away from the post-treatment layer;
a passivation layer disposed on a side of the barrier layer away from the second buffer layer;
a first anode contact hole penetrating the passivation layer into the barrier layer;
a first anode disposed within the first anode contact hole;
the dielectric layer is arranged on one side of the passivation layer far away from the barrier layer and between the first anode and the barrier layer;
the second anode contact hole penetrates through the dielectric layer and the passivation layer and extends into the barrier layer;
a second anode disposed within the second anode contact hole;
a cathode contact hole penetrating the dielectric layer and the passivation layer;
the cathode is arranged on the dielectric layer and in the cathode contact hole;
a protective layer disposed over the first anode, the second anode, the cathode, and the dielectric layer;
an anode opening through the protective layer to expose the first anode and the second anode;
the anode conducting metal is arranged on one side of the protective layer, which is far away from the dielectric layer, and is connected with the first anode and the second anode;
a cathode opening through the protective layer to expose the cathode;
the cathode conducting metal is arranged on one side, far away from the dielectric layer, of the protective layer, and the cathode conducting metal is connected with the cathode;
a field plate layer disposed on the protective layer, the field plate layer being connected with the anode conductive metal, wherein the anode conductive metal, the cathode conductive metal, and the field plate layer are formed simultaneously.
2. The semiconductor device according to claim 1, wherein the first anode and the second anode comprise a first metal layer and a second metal layer, wherein the first metal layer is disposed on a side of the dielectric layer away from the passivation layer and extends into the first anode contact hole and the second anode contact hole to cover the dielectric layer at the bottom of the first anode contact hole and the bottom of the second anode contact hole, and the second metal layer is disposed on the first metal layer and fills the first anode contact hole and the second anode contact hole.
3. A semiconductor device according to claim 1, wherein the first anode and the second anode are formed of a first number of metal layers stacked, the cathode is formed of a second number of metal layers stacked, and the first number is greater than the second number.
4. The semiconductor device according to claim 1, wherein the post-treatment layer is an aluminum oxide layer.
5. The semiconductor device of claim 1, wherein the post-treatment layer is 0.5-2nm thick.
6. An epitaxial layer of gallium nitride, comprising:
a semiconductor substrate;
a first buffer layer disposed on the semiconductor substrate;
the post-processing layer is arranged on one side, far away from the semiconductor substrate, of the first buffer layer;
the second buffer layer is arranged on one side, far away from the first buffer layer, of the post-treatment layer;
a barrier layer disposed on a side of the second buffer layer away from the post-treatment layer.
7. The epitaxial layer of gallium nitride according to claim 6, wherein the first buffer layer is an aluminum nitride layer.
8. The epitaxial layer of gallium nitride according to claim 6, wherein the thickness of the first buffer layer is 10-300 nm.
9. The epitaxial layer of gallium nitride according to claim 6, wherein the post-treatment layer is an aluminum oxide layer.
10. An epitaxial layer of gallium nitride according to claim 6, wherein the thickness of the post-treatment layer is 0.5-2 nm.
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