CN109638073B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 230000004888 barrier function Effects 0.000 claims abstract description 177
- 239000013078 crystal Substances 0.000 claims abstract description 66
- 238000005530 etching Methods 0.000 claims abstract description 49
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000000203 mixture Substances 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 373
- 239000002356 single layer Substances 0.000 claims description 49
- 239000000463 material Substances 0.000 claims description 16
- 238000002161 passivation Methods 0.000 claims description 15
- 238000000231 atomic layer deposition Methods 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 230000008569 process Effects 0.000 abstract description 27
- 229910002601 GaN Inorganic materials 0.000 description 49
- 238000005516 engineering process Methods 0.000 description 20
- 238000000137 annealing Methods 0.000 description 14
- 230000015572 biosynthetic process Effects 0.000 description 14
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 230000008439 repair process Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 238000000407 epitaxy Methods 0.000 description 7
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 6
- 239000000460 chlorine Substances 0.000 description 6
- 229910052801 chlorine Inorganic materials 0.000 description 6
- 239000010408 film Substances 0.000 description 6
- 238000011031 large-scale manufacturing process Methods 0.000 description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000005566 electron beam evaporation Methods 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 238000001755 magnetron sputter deposition Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 3
- 238000009616 inductively coupled plasma Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 230000001105 regulatory effect Effects 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 2
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 2
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 2
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000004886 process control Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- OCGWQDWYSQAFTO-UHFFFAOYSA-N tellanylidenelead Chemical compound [Pb]=[Te] OCGWQDWYSQAFTO-UHFFFAOYSA-N 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 229910000952 Be alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
Abstract
The invention is applicable to the technical field of semiconductor devices, and provides a semiconductor structure and a forming method thereof, wherein the semiconductor structure sequentially comprises the following components from bottom to top: a substrate; a buffer layer; the channel layer is made of GaN crystals or InGaN crystals; thick barrier layer of In m Al n Ga (1‑m‑n) N crystal, al component molar content 0.80 not less than 0.15, in component molar content 0.45 not less than 0, thickness not less than 10nm, gate electrode window formed in the thick barrier layer, channel layer or thick barrier layer not greater than 3nm in bottom; thin barrier layer of low Al composition In x Al y Ga (1‑x‑y) N crystal with thickness of 0.5-5 nm, al component molar content of 0.15-0.01, in component molar content of 0.3-0 and in component molar content of 0.3-0 inside the gate electrode window; the P-type gate layer is made of P-type conductive GaN crystals or AlGaN crystals; and the gate electrode is positioned in the gate electrode window, and the bottom of the gate electrode is contacted with the P-type gate layer. The etching damage layer on the side wall and the bottom of the groove-shaped gate can be repaired when the low Al component Bao Shilei layer grows in an epitaxial mode, the interface state of the gate dielectric is reduced, the reliability of the gate is enhanced, and the process window and the device yield are improved.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and provides a semiconductor structure and a forming method thereof.
Background
With the development of modern weaponry and aerospace, nuclear energy, communication technology, automotive electronics, switching power supplies, higher demands are being placed on the performance of semiconductor devices. As a wide forbiddenTypical representatives of the band semiconductor material, gaN-based materials have the characteristics of large forbidden band width, high electron saturation drift speed, high critical breakdown field strength, high thermal conductivity, good stability, corrosion resistance, radiation resistance and the like, and can be used for manufacturing high-temperature, high-frequency and high-power electronic devices. In addition, gaN has excellent electronic characteristics, and can form a modulation doped AlGaN/GaN heterostructure with AlGaN, and the structure can obtain a wavelength higher than 1500cm at room temperature 2 Electron mobility of/Vs up to 3X 10 7 Peak electron velocity in cm/s and 2X 10 7 Saturated electron velocity of cm/s and obtaining two-dimensional electron gas density higher than that of a second generation compound semiconductor heterostructure are known as ideal materials for developing microwave power devices. Therefore, the microwave power device based on the AlGaN/GaN heterojunction has very good application prospect in the fields of high-frequency and high-power wireless communication, radar and the like.
The main working part of a typical AlGaN/GaN HEMT device structure is the two-dimensional electron gas (2 DEG) at the AlGaN/GaN heterojunction interface, which has a high surface concentration and electron mobility because it is hardly subject to the scattering of ionized impurities. The working principle of the device is that the 2DEG density at the heterojunction interface is regulated and controlled by changing the magnitude of the gate voltage, so that the source leakage current is changed. Okamoto et al reported a recessed gate AlGaN/GaN HFET with a modulated field plate, the recessed gate technique increased the threshold voltage of the device from-4.2V to-1.7V, W.Saito et al proposed a recessed gate structured enhancement AlGaN/GaN HFET, by etching the AlGaN barrier layer, a threshold voltage of +1V was achieved, and a lower specific on-resistance of 4mΩ cm could be achieved 2 The withstand voltage was 435V. However, the AlGaN barrier layer is etched with a groove, so that the AlGaN barrier layer is damaged on one hand, the surface defects of the etched barrier layer are more, the reliability of the device is affected, the thickness uniformity and consistency of the AlGaN barrier layer remained in the groove after etching are very high, the thickness of about 3-5 nm is required to be remained, and strict requirements are put on the consistency and repeatability of the epitaxy and etching processes. The two factors cause the problems of lower enhanced threshold, unstable threshold, poor reliability and the like of the groove gate type GaN HEMT device, and the etching processDifficult to control, narrow in process window, low in yield and unfavorable for large-scale production.
Disclosure of Invention
The invention aims to at least solve one of the technical defects, in particular to solve the problems that the etching damage and the surface defect of an AlGaN barrier layer are caused when the AlGaN barrier layer is etched by a groove gate technology, the etching process window is narrow, the large-scale production is difficult, and the like.
To achieve the above object, in one aspect, the present invention provides a semiconductor structure, which includes, in order from bottom to top: a substrate; a buffer layer on the substrate surface; the channel layer is made of GaN crystals or InGaN crystals; a thick barrier layer made of In m Al n Ga (1-m-n) N crystal, wherein the molar content of Al component is more than or equal to 0.80 and more than or equal to 0.15, the molar content of in component is more than or equal to 0.45 and more than or equal to 0, the thickness of the thick barrier layer is not less than 10nm, a gate electrode window is formed on the thick barrier layer, and the bottom of the gate electrode window is the channel layer or the thick barrier layer with the thickness not more than 3 nm; a thin barrier layer of In with low Al composition x Al y Ga (1-x-y) N crystal with thickness of 0.5-5 nm, al component molar content of 0.15-0.01, in component molar content of 0.3-0, and side wall and bottom of the concave gate groove inside the gate electrode window; the P-type gate layer is made of P-type conductive GaN crystals or AlGaN crystals; and the gate electrode is positioned in the gate electrode window, and the bottom of the gate electrode is contacted with the P-type gate layer.
In one embodiment of the present invention, the semiconductor structure further comprises: the source electrode window and the drain electrode window are respectively positioned at two sides of the gate electrode window, and the bottoms of the source electrode window and the drain electrode window are the channel layer or a thick barrier layer with the thickness not more than 3 nm; a thin barrier layer located within the source electrode window and the drain electrode window; and the source electrode and the drain electrode are respectively positioned in the source electrode window and the drain electrode window, and the side wall and the bottom of the source electrode and the drain electrode are contacted with the thin barrier layer.
In one embodiment of the present invention, the semiconductor structure further comprises: and the gate dielectric layer is positioned between the P-type gate layer and the gate electrode.
In one embodiment of the invention, the thin barrier layer extends to the upper surface of the thick barrier layer on both sides of the gate electrode window.
In one embodiment of the present invention, the semiconductor structure further comprises: and the passivation layer is positioned on the thin barrier layer or the thick barrier layer between the source electrode and the gate electrode and between the drain electrode and the gate electrode.
In one embodiment of the invention, the thin barrier layer is an N-type conductive crystal.
In one embodiment of the present invention, the buffer layer is one or a combination of several of an AlN layer, an AlGaN layer with graded Al composition, an AlN/AlGaN stack, and an AlGaN/GaN stack.
In one embodiment of the present invention, the portion of the buffer layer adjacent to the channel layer is a high-resistance layer, and the high-resistance layer is one or a combination of several of a GaN layer, an AlN/GaN stack, and an AlGaN/GaN stack with high resistivity.
In one embodiment of the invention, the gate dielectric layer is SiO 2 Single layer, al 2 O 3 Monolayer, sc 2 O 3 Monolayer, hfO 2 Monolayer, ta 2 O 5 A single layer, a ZnO single layer, a silicon nitride single layer and a silicon oxynitride single layer.
In one embodiment of the invention, the passivation layer is SiN or AlN material.
In another aspect, the embodiment of the invention further provides a method for forming a semiconductor structure, which includes the following steps: step S0, providing a substrate; step S1, sequentially epitaxially growing a buffer layer, a channel layer made of GaN crystal or InGaN crystal and a thick barrier layer made of In on the substrate m Al n Ga (1-m-n) N crystal, wherein the molar content of Al component is 0.80-0.15, the molar content of In component is 0.45-0, and the thickness of the thick barrier layer is not less than 10nm; step S2, etching the thick barrier layer until the channel is etchedForming a gate electrode window at a layer or a thick barrier layer not more than 3nm from the channel layer; s3, forming a thin barrier layer In the gate electrode window, wherein the thin barrier layer is In with low Al component x Al y Ga (1-x-y) N crystal with thickness of 0.5-5 nm, molar content of Al component of 0.15-0.01, molar content of in component of 0.3-0; s4, forming a P-type grid layer on the thin barrier layer, wherein the P-type grid layer is made of a P-type conductive GaN crystal or AlGaN crystal, and the thickness of the P-type grid layer is 20-200 nm; and S5, forming a gate electrode on the P-type gate layer.
In one embodiment of the present invention, after step S4, before step S5, further comprising: and S41, forming a gate dielectric layer on the P-type gate layer.
In one embodiment of the present invention, in step S2, while etching the thick barrier layer to form a gate electrode window, etching partial regions on both sides of the gate electrode to form a source electrode window and a drain electrode window, wherein the bottoms of the source electrode window and the drain electrode window are channel layers or thick barrier layers not more than 3nm away from the channel layers; in step S3, a thin barrier layer is formed in the gate electrode window and simultaneously in the source electrode window and the drain electrode window; in step S5, a source electrode and a drain electrode are formed on the P-type gate layer thin barrier layer in the source electrode window and the drain electrode window, respectively, simultaneously with, before or after forming the gate electrode.
In one embodiment of the present invention, the buffer layer is one or a combination of several of an AlN layer, an AlGaN layer with graded Al composition, an AlN/AlGaN stack, and an AlGaN/GaN stack.
In one embodiment of the present invention, the portion of the buffer layer adjacent to the channel layer is a high-resistance layer, and the high-resistance layer is one or a combination of several of a GaN layer, an AlN/GaN stack, and an AlGaN/GaN stack with high resistivity.
In one embodiment of the invention, the thin barrier layer and the P-type gate layer are formed by a metal-organic chemical vapor deposition technique or an atomic layer deposition technique.
In one embodiment of the invention, the gate dielectric layer is SiO 2 Single layer, al 2 O 3 Monolayer, sc 2 O 3 Monolayer, hfO 2 Monolayer, ta 2 O 5 A single layer, a ZnO single layer, a silicon nitride single layer and a silicon oxynitride single layer.
The GaN HEMT device in the embodiment of the invention epitaxially grows the low Al component thin barrier layer on the thick barrier layer, and has the following beneficial effects:
1. in general, when a groove gate etching is carried out on a GaN HEMT device with a groove gate structure, material damage caused by etching is strictly controlled, and the process control difficulty of non-damage GaN etching is high; the etching damage layer of the side wall of the gate groove and the bottom material can be repaired during epitaxy by utilizing the low Al component thin barrier layer of epitaxial growth, so that the interface state density of a gate interface is reduced, and the reliability of the device is improved.
2. In general, when a device with a groove gate structure is used for groove gate etching, a barrier layer with the thickness of 3-5 nm is reserved, the etching depth is required to be accurately controlled, the strict requirements are put on the consistency and repeatability of epitaxy and etching processes, the difficulty of large-scale production is high, the barrier layer can be completely etched by adopting a mode of epitaxially growing a low Al component thin barrier layer, a small amount of barrier layer can be overetched to a channel layer, and the barrier layer with the thickness of less than 3nm can be reserved, so that the etching process window is greatly widened, the process is easy to control, and the large-scale production is easy to realize;
3. the low Al component thin barrier layer and the P-type gate layer are epitaxially grown, so that the GaN HEMT device is realized, the gate control capability can be modulated by controlling the thickness of the thin barrier layer, the threshold voltage is regulated, the on-resistance is reduced, and the device performance is improved.
Drawings
FIG. 1 (a) is a schematic diagram of a semiconductor structure with a gate electrode window, in which a thick P-type gate layer is provided in the gate electrode window according to an embodiment of the present invention;
FIG. 1 (b) is a schematic diagram of a semiconductor structure with a gate electrode window, in which a thin P-type gate layer is present;
fig. 2 is a schematic diagram of a semiconductor structure with a gate electrode window, a source electrode window and a drain electrode window according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a semiconductor structure with thin barrier layers extending on both sides of a gate electrode window according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a semiconductor structure with a gate electrode window, a source electrode window and a drain electrode window, and thin barrier layers extending on both sides of the gate electrode window according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a semiconductor structure with a dielectric layer according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a semiconductor structure with a gate electrode window, a source electrode window and a drain electrode window and a dielectric layer according to an embodiment of the present invention;
fig. 7 is a flowchart of a semiconductor forming method according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. The dimensions of the various layers and regions are exaggerated or reduced for convenience of illustration and, therefore, the dimensions and proportions shown in the figures do not necessarily represent actual dimensions, nor reflect the proportional relationship of dimensions. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
The semiconductor structure sequentially comprises the following components from bottom to top: a substrate; a buffer layer on the upper surface of the substrate; the channel layer is formed of a silicon nitride layer,the material is GaN crystal or InGaN crystal; thick barrier layer of In m Al n Ga (1-m-n) N crystal, wherein the molar content of Al component is 0.80-0.15, the molar content of in component is 0.45-0, n+m-1, the thickness of thick barrier layer is not less than 10nm, gate electrode window is formed on the thick barrier layer, and channel layer or thick barrier layer with thickness not more than 3nm is arranged at the bottom of the gate electrode window; thin barrier layer of low Al composition In x Al y Ga (1-x-y) N crystal with thickness of 0.5-5 nm, al component molar content of 0.15-0.01, in component molar content of 0.3-0, and being inside the gate electrode window, i.e. on the side wall and bottom of the gate electrode window; the P-type gate layer is made of P-type conductive GaN crystals or AlGaN crystals; and the gate electrode is positioned in the gate electrode window, and the bottoms of the gate electrode and the gate electrode are contacted with the P-type gate layer.
When the thickness of the P-type gate layer is relatively thin, the P-type gate layer is grown on the thin barrier layer, and at this time, the bottom and the side wall of the gate electrode are in contact with the P-type gate layer, the structure is schematically shown in fig. 1 (b), and when the thickness of the P-type gate layer is relatively thick, the P-type gate layer fills the whole gate electrode window, and at this time, the bottom of the gate electrode is in contact with the P-type gate layer, and the structure is schematically shown in fig. 1 (a). In one embodiment of the invention, the substrate can be one or a combination of several of Si, siC and sapphire crystals with the thickness of 300-1500 mu m, can also be alloy semiconductors such as indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide or a combination thereof, and can also be epitaxial wafers of one or more layers of semiconductor films grown on the semiconductor substrate. Preferably, the substrate in the present embodiment may be a Si or SiC substrate.
In one embodiment of the invention, the buffer layer with the thickness of 1-5 mu m is arranged on the substrate, and the buffer layer material is one or a combination of several of an AlN layer, an AlGaN layer with gradually changed Al component, an AlN/AlGaN laminated layer and an AlGaN/GaN laminated layer. In a preferred embodiment of the present invention, the portion of the buffer layer adjacent to the channel layer is a high-resistance layer having a thickness of 0.5 to 3.5 μm, and the high-resistance layer may be one or a combination of several of a GaN layer, an AlN/GaN stack, and an AlGaN/GaN stack having a high resistivity. The high-resistance layer can effectively block or reduce the current flow of the device to the buffer layer, and improve the device performance, especially the off-state leakage.
In one embodiment of the invention, the channel layer is a 200-300 nm thick GaN crystal or InGaN crystal. InGaN has higher mobility than GaN, and the high frequency performance of the device is better, but when InGaN is used as a channel layer, the band gap of the energy band is narrower than GaN, and the withstand voltage performance of the device is reduced. Al of low Al component t Ga 1-t The N crystal (t is less than or equal to 0.1) can also be used as a channel layer, and the difference between the energy band structure and the lattice constant of the N crystal and GaN is small, so that the N crystal can be regarded as a practical GaN channel layer and is also within the protection scope of the invention.
In one embodiment of the invention, the thick barrier layer has a thickness of 10 to 30nm, preferably 15 to 20nm.
In one embodiment of the present invention, the P-type gate layer material is a P-type conductive GaN crystal or an AlGaN crystal, preferably the P-type gate layer material is a P-type conductive GaN crystal; the thickness of the P-type gate layer is 20 to 200nm, preferably, the thickness of the P-type gate layer is 90 to 130nm.
The gate electrode window may be formed on the thick barrier layer using a "photolithography + etch" technique, first defining the gate electrode window region using photolithography, and then performing a gate trench etch using chlorine-based Reactive Ion Etching (RIE) or inductively coupled plasma etching (ICP etching), forming the gate electrode window.
In one embodiment of the present invention, the thin barrier layer and the P-type gate layer may be formed using Metal Organic Chemical Vapor Deposition (MOCVD) or Atomic Layer Deposition (ALD). MOCVD can epitaxially generate a high-quality thin barrier layer, and the thin barrier layer can be deposited by using an ALD technology, so that the crystal quality of the formed thin barrier layer is inferior to that of the MOCVD technology due to the low process temperature of ALD, and the crystal quality of the thin barrier layer can be improved by using a high-temperature annealing technology after the deposition of the thin barrier layer. In order to repair the etching damage caused by the formation of the gate electrode window, the damaged layer may be repaired by a high-temperature annealing treatment at about 1000-1200 ℃ before the formation of the thin barrier layer. Alternatively, the high temperature annealing process is performed under a chlorine-containing atmosphere, for example, containing chlorine gas or hydrogen chloride gas, and chlorine can etch nitride at high temperature to remove the surface damaged layer. Optionally, the high-temperature annealing process is performed under a hydrogen-containing atmosphere, and the hydrogen atmosphere can promote the migration of atoms on the surface of the nitride crystal and accelerate the repair of the damaged layer on the surface. In a preferred embodiment of the invention, the semiconductor structure is subjected to an in-situ high temperature annealing treatment in a MOCVD furnace to repair the damaged layer caused by etching, before the thin barrier layer is formed by MOCVD epitaxy. In order to repair the etching damage caused by the formation of the gate electrode window, the semiconductor structure may be subjected to a wet chemical treatment, for example, by removing the damaged layer by aqua regia etching, before the formation of the thin barrier layer.
The gate electrode may be formed within the gate electrode window using electron beam evaporation techniques or magnetron sputtering techniques, with the optional gate electrode metal being Ni/Au.
In one embodiment of the present invention, the semiconductor structure further includes a source electrode and a drain electrode, the source electrode and the drain electrode are located at two sides of the gate electrode, and the bottom is in contact with the thick barrier layer. In a preferred embodiment of the present invention, a gate electrode window, a source electrode window and a drain electrode window are formed on the thick barrier layer, the source electrode window and the drain electrode window are respectively located at two sides of the gate electrode window, the bottoms of the gate electrode window, the source electrode window and the drain electrode window are channel layers or thick barrier layers with the thickness not greater than 3nm, correspondingly, thin barrier layers are arranged in the source electrode window and the drain electrode window, the thin barrier layers cover the side walls and the bottoms of the source electrode window and the drain electrode window, and the source electrode and the drain electrode are respectively arranged in the source electrode window and the drain electrode window, and the side walls and the bottoms of the source electrode and the drain electrode are all in contact with the thin barrier layers, as shown in fig. 2. The source electrode window and the drain electrode window can be formed at the same time of preparing the gate electrode window, and no additional process steps are required. The thin barrier layers within the source and drain electrode windows may also be formed at the same time as the thin barrier layers in the gate electrode windows, without adding additional process steps. The source electrode and the drain electrode can be obtained by adopting an electron beam evaporation technology or a magnetron sputtering technology to deposit metal and then annealing to form ohmic contact, and the optional source and drain metal is Ti/Al/Ni. The source electrode and the drain electrode need to be in ohmic contact with the semiconductor, and the higher the Al component of the thick barrier layer is, the greater the ohmic contact forming process difficulty is, so compared with the process of directly forming the source/drain electrode on the thick barrier layer, the process of depositing the metal on the low Al component thin barrier layer is beneficial to the manufacture of the ohmic contact process of the source/drain electrode, and the contact resistance and the series resistance of the source/drain of the device are reduced.
In another embodiment of the present invention, the source electrode window and the drain electrode window are not formed, but a gallium nitride thin film is further formed on the upper surface of the thick barrier layer. Because the content of aluminum components in the thick barrier layer is higher, ohmic contact required by a source electrode and a drain electrode is not facilitated, and therefore, a gallium nitride film with the thickness of about 1-10 nm can be epitaxially grown on the upper surface of the thick barrier layer in situ after the thick barrier layer is epitaxially grown, which is beneficial to the formation of ohmic contact of the source electrode and the drain electrode.
In still another embodiment of the present invention, as shown in fig. 3, a thin barrier layer is extended to the upper surface of the thick barrier layer on both sides of the gate electrode window, and when only the gate electrode window is etched on the thick barrier layer (without forming the source electrode window and the drain electrode window), the source electrode and the drain electrode are provided on the extended thin barrier layer. The bottoms of the source electrode and the drain electrode are contacted with the thin barrier layer, and the low content of Al component in the thin barrier layer is beneficial to the manufacture of source-drain ohmic contact technology, so that the contact resistance and the source-drain series resistance of the device are reduced.
In yet another embodiment of the present invention, when the gate electrode window, the source electrode window, and the drain electrode window are etched on the thick barrier layer, respectively, the thin barrier layer extends to the entire upper surface of the semiconductor structure, forming a continuous thin barrier layer, including thin barrier layers on the thick barrier layer between the gate electrode window and the source electrode window and between the gate electrode window and the drain window, as shown in fig. 4. The formation of the continuous thin barrier layer does not require additional photolithography and masking processes, and can simplify the process steps.
In one embodiment of the present invention, a gate dielectric layer is provided between the P-type gate layer and the gate electrode, as shown in fig. 5 and 6. In fig. 5, a gate electrode window is etched only in the gate electrode region, and in fig. 6, in addition to the gate electrode window, there are also a source electrode window and a drain electrode window, in both cases, a gate dielectric layer may be disposed between the P-type gate layer and the gate electrode. The gate dielectric layer is about 1-50 nm thick and is made of SiO 2 Single layer, al 2 O 3 Monolayer, sc 2 O 3 Monolayer, hfO 2 Monolayer, ta 2 O 5 A single layer, a ZnO single layer, a silicon nitride single layer, a silicon oxynitride single layer, or a composite laminate of one or more of the single layers, wherein the silicon nitride and the silicon oxynitride can be a film layer with standard stoichiometric ratio or a film layer with a deviation from the standard stoichiometric ratio. The gate dielectric layer may be typically formed by ALD deposition. By arranging the gate dielectric layer, the gate leakage can be reduced while the control of the gate to the channel layer is ensured, and the method is very beneficial to reducing the power consumption of the device.
In one embodiment of the invention, a passivation layer is provided on the thick or thin barrier layer between the source and gate electrodes, and between the drain and gate electrodes. The passivation layer is an insulating material, such as SiN or AlN material, capable of reducing the movable charge density on the upper surface of the barrier layer, and the thickness of the passivation layer is about 1-10 nm. If the thin barrier layer is extended to the thick barrier layers on both sides of the gate electrode, the passivation layer is disposed on the thin barrier layer, and if the thin barrier layer is not epitaxially grown on the thick barrier layers on both sides of the gate electrode, the passivation layer is disposed on the thick barrier layer. The passivation layer may be formed by Plasma Enhanced Chemical Vapor Deposition (PECVD), metalorganic chemical vapor deposition, or atomic layer deposition.
In one embodiment of the invention, the thin barrier layer is a crystal with N-type conductivity, and may be unintentionally doped or doped to form In of N-type low Al composition x Al y Ga (1-x-y) And N crystals. The thin barrier layer may be either N-type or P-type. When the thin barrier layer is N-type conductive, the bottom of the gate electrode window can be etched to the channel layer, or a thick barrier within 3nm can be reservedThe etching process window is wide; when the thin barrier layer is P-type conductive, the thick barrier layer at the bottom of the gate electrode window needs to be kept at 3-5 nm, the etching depth needs to be accurately controlled, and the process window is narrow. Thus, with a thin barrier layer of N-type conductivity, the process window for etching can be widened.
In one embodiment of the present invention, the P-type gate layer is a GaN crystal or an AlGaN crystal having a P-type conductivity type, which can be formed by doping Be, mg, zn, C, mn, cd, al or the like, preferably Mg, zn as a doping element; the P-type gate layer can improve threshold voltage and realize an enhanced HEMT device.
As shown in fig. 7, a flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention includes the following steps:
and step S0, providing a substrate, wherein the substrate can be one or a combination of several of Si, siC and sapphire crystals, can also be an alloy semiconductor such as indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide or a combination thereof, and can also be an epitaxial wafer of one or more layers of semiconductor films grown on the semiconductor substrate. Preferably, the substrate in the present embodiment may be a Si or SiC substrate.
Step S1, epitaxially growing a buffer layer, a channel layer made of GaN crystal or InGaN crystal and a thick barrier layer made of In on a substrate m Al n Ga (1-m-n) N crystal, wherein the molar content of Al component is 0.80-0.15, the molar content of in component is 0.45-0, m+n is not more than 1, and the thickness of thick barrier layer is not less than 10nm. Wherein the thickness of the buffer layer is 1-5 mu m, and the material is one or the combination of more of an AlN layer, an AlGaN layer with gradual change of Al components, an AlN/AlGaN lamination and an AlGaN/GaN lamination; the thickness of the channel layer is 200-300 nm; the thickness of the thick barrier layer is 10-30 nm. In a preferred embodiment of the present invention, the portion of the buffer layer adjacent to the channel layer is a high-resistance layer having a thickness of 0.5 to 3.5 μm, and the high-resistance layer may be one or a combination of several of a GaN layer, an AlN/GaN stack, and an AlGaN/GaN stack having a high resistivity. The high-resistance layer can effectively block or reduce the current flow of the device to the buffer layerAnd the device performance, especially the off-state leakage, is improved.
And S2, etching the thick barrier layer to the position of the channel layer or the thick barrier layer which is not more than 3nm away from the channel layer to form a gate electrode window. This step may be implemented using a "photolithography + etch" technique: firstly, defining and forming a gate electrode window area on a thick barrier layer by utilizing a photoetching technology, and then, carrying out gate groove etching by utilizing chlorine-based RIE or ICP etching until the gate electrode window is formed at a position of a channel layer or the thick barrier layer which is not more than 3nm away from the channel layer;
s3, forming a thin barrier layer In the gate electrode window, wherein the thin barrier layer is In with N-type low Al component x Al y Ga (1-x-y) N crystal with thickness of 0.5-5 nm, molar content of Al component of 0.15-0.01, molar content of in component of 0.3-0; wherein, the thin barrier layer covers the side wall and the bottom of the gate electrode window, and can be formed by MOCVD or ALD technology. MOCVD can epitaxially generate a high-quality thin barrier layer, and the thin barrier layer can be deposited by using an ALD technology, so that the crystal quality of the formed thin barrier layer is inferior to that of the MOCVD technology due to the low process temperature of ALD, and the crystal quality of the thin barrier layer can be improved by using a high-temperature annealing technology after the deposition of the thin barrier layer. In order to repair the etching damage caused by the formation of the gate electrode window, the damaged layer may be repaired by a high-temperature annealing treatment at about 1000-1200 ℃ before the formation of the thin barrier layer. Alternatively, the high temperature annealing process is performed under a chlorine-containing atmosphere, for example, containing chlorine gas or hydrogen chloride gas, and chlorine can etch nitride at high temperature to remove the surface damaged layer. Optionally, the high-temperature annealing process is performed under a hydrogen-containing atmosphere, and the hydrogen atmosphere can promote the migration of atoms on the surface of the nitride crystal and accelerate the repair of the damaged layer on the surface. In a preferred embodiment of the invention, the semiconductor structure is subjected to an in-situ high temperature annealing treatment in a MOCVD furnace to repair the damaged layer caused by etching, before the thin barrier layer is formed by MOCVD epitaxy. In order to repair the etching damage caused by the formation of the gate electrode window, the semiconductor structure may be subjected to a wet chemical treatment, for example, by removing the damaged layer by aqua regia etching, before the formation of the thin barrier layer.
S4, forming a P-type grid layer on the thin barrier layer, wherein the P-type grid layer is made of a P-type conductive GaN crystal or AlGaN crystal, and the thickness of the P-type grid layer is 20-200 nm; wherein the P-type gate layer may be formed using MOCVD or ALD techniques. MOCVD can epitaxially generate a high-quality P-type gate layer, and the P-type gate layer can be deposited and formed by utilizing an ALD technology, so that the crystal quality of the formed P-type gate layer is inferior to that of the MOCVD technology due to the low process temperature of ALD, and the crystal quality can be improved through a subsequent high-temperature annealing technology.
And S5, forming a gate electrode on the P-type gate layer. Wherein, this step can be realized by electron beam evaporation technology or magnetron sputtering technology, and the optional gate electrode metal is Ni/Au.
In one embodiment of the present invention, a source electrode and a drain electrode are formed on both sides of the gate electrode prior to the formation of the gate electrode, wherein the source electrode and the drain electrode are in contact with the thick barrier layer. The source/drain electrode needs to form ohmic contact with the barrier layer, metal can be deposited by adopting an electron beam evaporation technology or a magnetron sputtering technology, and then ohmic contact is formed by annealing, wherein the optional source/drain metal is Ti/Al/Ni.
In one embodiment of the present invention, in step S2, a gate electrode window is etched on the thick barrier layer, and simultaneously, a source electrode window and a drain electrode window are etched on partial regions on both sides of the gate electrode, wherein the bottoms of the source electrode window and the drain electrode window are channel layers or thick barrier layers not more than 3nm away from the channel layers; in step S3, a thin barrier layer is formed in the gate electrode window and simultaneously in the source electrode window and the drain electrode window; in step S5, before or after forming the gate electrode, a source electrode and a drain electrode are formed on the thin barrier layer in the source electrode window and the drain electrode window, respectively. Wherein the source and drain electrodes are typically of a different metal than the gate electrode, and may be formed either before or after the gate electrode is formed. In a preferred embodiment of the present invention, the source and drain electrodes are formed first, and then the gate electrode is formed in the gate electrode window, so that the influence of the high temperature annealing process required in the formation of the source/drain electrodes on the gate electrode structure and performance can be avoided. The source electrode window and the drain electrode window are formed simultaneously with the gate electrode window, and the thin barrier layers in the source electrode window and the drain electrode window can be formed simultaneously with the preparation of the thin barrier layers in the gate electrode window, so that additional process steps are not required to be added, and the process can be simplified.
In one embodiment of the present invention, after step S4, the method for forming a semiconductor structure further includes, before step S5: step S41, forming a gate dielectric layer on the P-type gate layer, wherein the gate dielectric layer is positioned between the P-type gate layer and the gate electrode, and the gate dielectric layer is SiO 2 Single layer, al 2 O 3 Monolayer, sc 2 O 3 Monolayer, hfO 2 Monolayer, ta 2 O 5 One or more of a single layer, a ZnO single layer, a silicon nitride single layer and a silicon oxynitride single layer are laminated, wherein the silicon nitride and the silicon oxynitride can be film layers with standard stoichiometric ratio or deviated from standard stoichiometric ratio, and if a gate electrode is formed on a gate dielectric layer, the formation of a source electrode and a drain electrode is before or after the formation of the gate electrode.
In one embodiment of the present invention, before the gate electrode window is formed in step S2, the semiconductor structure forming method further includes: s11, forming a passivation layer on the surface of the thick barrier layer, wherein the passivation layer is made of SiN or AlN material; in step S2, etching the passivation layer and the thick barrier layer until the channel layer or the thick barrier layer which is not more than 3nm away from the channel layer is etched, forming a gate electrode window, etching the passivation layer in partial areas at two sides of the gate electrode window until the thick barrier layer is etched, wherein the etching areas at two sides of the gate electrode window are used for forming a source electrode and a drain electrode; or in step S2, etching the passivation layer and the thick barrier layer until the channel layer or the thick barrier layer not greater than 3nm from the channel layer is etched, thereby forming a gate electrode window, a source electrode window and a drain electrode window, wherein the source electrode window and the drain electrode window are respectively positioned at two sides of the gate electrode window.
The GaN HEMT device provided by the embodiment of the invention has the following beneficial effects that the low Al component thin barrier layer is extended on the thick barrier layer:
1. in general, when a groove gate etching is carried out on a GaN HEMT device with a groove gate structure, material damage caused by etching is strictly controlled, and the process control difficulty of non-damage GaN etching is high; the etching damage layer of the side wall of the gate groove and the bottom material can be repaired during epitaxy by utilizing the low Al component thin barrier layer of epitaxial growth, so that the interface state density of a gate interface is reduced, and the reliability of the device is improved.
2. In general, when a device with a groove gate structure is used for groove gate etching, a barrier layer with the thickness of 3-5 nm is reserved, the etching depth is required to be accurately controlled, the strict requirements are put on the consistency and repeatability of epitaxy and etching processes, the difficulty of large-scale production is high, the barrier layer can be completely etched by adopting a mode of epitaxially growing a low Al component thin barrier layer, a small amount of barrier layer can be overetched to a channel layer, and the barrier layer with the thickness of less than 3nm can be reserved, so that the etching process window is greatly widened, the process is easy to control, and the large-scale production is easy to realize;
3. the low Al component thin barrier layer and the P-type gate layer are epitaxially grown, so that the GaN HEMT device is realized, the gate control capability can be modulated by controlling the thickness of the thin barrier layer, and therefore, the threshold voltage is regulated, the on-resistance is reduced, and the device performance is improved.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (14)
1. A semiconductor structure, comprising, in order from bottom to top:
a substrate;
a buffer layer on the substrate surface;
the channel layer is made of GaN crystals or InGaN crystals;
a thick barrier layer made of In m Al n Ga (1-m-n) N crystal, wherein the molar content of Al component is 0.80-0.15, the molar content of in component is 0.45-0, the thickness of the thick barrier layer is not less than 10nm, a gate electrode window is formed on the thick barrier layer, the gate is formed on the thick barrier layerThe bottom of the electrode window is the channel layer or a thick barrier layer with the thickness not more than 3 nm;
a thin barrier layer of In with low Al composition x Al y Ga (1-x-y) N crystal with thickness of 0.5-5 nm, molar content of Al component of 0.15-0.01, molar content of in component of 0.3-0, and covering the side wall and bottom of the gate electrode window;
the P-type grid layer is made of P-type conductive GaN crystals or AlGaN crystals;
the gate electrode is positioned in the gate electrode window, and the bottom of the gate electrode is contacted with the P-type gate layer;
the semiconductor structure further includes:
the source electrode window and the drain electrode window are respectively positioned at two sides of the gate electrode window, and the bottoms of the source electrode window and the drain electrode window are the channel layer or a thick barrier layer with the thickness not more than 3 nm;
a thin barrier layer located within the source electrode window and the drain electrode window;
the source electrode and the drain electrode are respectively positioned in the source electrode window and the drain electrode window, and the side wall and the bottom of the source electrode and the drain electrode are in contact with the thin barrier layer;
the thin barrier layer extends to the upper surface of the thick barrier layer on both sides of the gate electrode window.
2. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises:
and the gate dielectric layer is positioned between the P-type gate layer and the gate electrode.
3. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises:
and the passivation layer is positioned on the thin barrier layer or the thick barrier layer between the source electrode and the gate electrode and between the drain electrode and the gate electrode.
4. The semiconductor structure of claim 1, wherein the thin barrier layer is an N-type conductive crystal.
5. The semiconductor structure of claim 1, wherein the buffer layer is one or a combination of an AlN layer, an AlGaN layer with graded Al composition, an AlN/AlGaN stack, an AlGaN/GaN stack.
6. The semiconductor structure of claim 1, wherein the portion of the buffer layer adjacent to the channel layer is a high-resistance layer, the high-resistance layer being one or a combination of a GaN layer, an AlN/GaN stack, an AlGaN/GaN stack having a high resistivity.
7. The semiconductor structure of claim 2, wherein said gate dielectric layer is SiO 2 Single layer, al 2 O 3 Monolayer, sc 2 O 3 Monolayer, hfO 2 Monolayer, ta 2 O 5 A single layer, a ZnO single layer, a silicon nitride single layer and a silicon oxynitride single layer.
8. The semiconductor structure of claim 3, wherein the passivation layer is SiN or AlN material.
9. The method for forming the semiconductor structure is characterized by comprising the following steps of:
step S0, providing a substrate;
step S1, sequentially epitaxially growing a buffer layer, a channel layer made of GaN crystal or InGaN crystal and a thick barrier layer made of In on the substrate m Al n Ga (1-m-n) N crystal, wherein the molar content of Al component is 0.80-0.15, the molar content of in component is 0.45-0, and the thickness of the thick barrier layer is not less than 10nm;
step S2, etching the thick barrier layer to the position of the channel layer or the thick barrier layer which is not more than 3nm away from the channel layer to form a gate electrode window;
s3, forming a thin barrier layer In the gate electrode window, wherein the thin barrier layer extends to the upper surfaces of the thick barrier layers at two sides of the gate electrode window, and the thin barrier layer is In with low Al component x Al y Ga (1-x-y) N crystal with thickness of 0.5-5 nm, molar content of Al component of 0.15-0.01, molar content of in component of 0.3-0;
s4, forming a P-type grid layer on the thin barrier layer, wherein the P-type grid layer is made of a P-type conductive GaN crystal or AlGaN crystal, and the thickness of the P-type grid layer is 50-200 nm;
s5, forming a gate electrode on the P-type gate layer;
in step S2, etching the thick barrier layer to form a gate electrode window, and etching partial areas on two sides of the gate electrode to form a source electrode window and a drain electrode window, wherein the bottoms of the source electrode window and the drain electrode window are channel layers or thick barrier layers which are not more than 3nm away from the channel layers;
in step S5, a source electrode and a drain electrode are formed on the thin barrier layer in the source electrode window and the drain electrode window, respectively, simultaneously with, before or after forming the gate electrode.
10. The method of forming a semiconductor structure of claim 9, further comprising, after step S4, before step S5:
and S41, forming a gate dielectric layer on the P-type gate layer.
11. The method of claim 9, wherein the buffer layer is one or a combination of several of an AlN layer, an AlGaN layer with graded Al composition, an AlN/AlGaN stack, and an AlGaN/GaN stack.
12. The method of forming a semiconductor structure according to claim 9, wherein a portion of the buffer layer adjacent to the channel layer is a high-resistance layer, and the high-resistance layer is one or a combination of a plurality of GaN layers, alN/GaN stacks, alGaN/GaN stacks having a high resistivity.
13. The method of claim 9, wherein the thin barrier layer and the P-type gate layer are formed by a metal-organic chemical vapor deposition technique or an atomic layer deposition technique.
14. The method of forming a semiconductor structure of claim 10, wherein said gate dielectric layer is SiO 2 Single layer, al 2 O 3 Monolayer, sc 2 O 3 Monolayer, hfO 2 Monolayer, ta 2 O 5 A single layer, a ZnO single layer, a silicon nitride single layer and a silicon oxynitride single layer.
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| JPH06338618A (en) * | 1993-04-02 | 1994-12-06 | Fujitsu Ltd | Semiconductor memory and data storing method thereof |
| KR20130010823A (en) * | 2011-07-19 | 2013-01-29 | 한국전자통신연구원 | Nitride electronic device and method for manufacturing it |
| KR20150091705A (en) * | 2014-02-03 | 2015-08-12 | 엘지전자 주식회사 | Nitride semiconductor and method thereof |
| CN209447803U (en) * | 2018-11-21 | 2019-09-27 | 芜湖启迪半导体有限公司 | A kind of semiconductor structure |
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