KR20130010823A - Nitride electronic device and method for manufacturing it - Google Patents

Abstract

PURPOSE: A nitride electronic device and a manufacturing method thereof are provided to implement an integrated circuit with various properties on a single substrate by using design technology and unit process with a structure of a different channel layer and a barrier layer. CONSTITUTION: A low temperature buffer layer(102) is formed on a sapphire substrate(101). A first semi-insulating GaN layer(103) is formed on the low temperature buffer layer. A first channel layer(104) for an electron transfer is formed on the first semi-insulating GaN layer. A first barrier layer(105) is formed on the first channel layer. A second semi-insulating GaN layer(107) is formed on the sidewall of the first barrier layer and the first channel layer. A second channel layer(108) and a second barrier layer(109) are formed on the second semi-insulating GaN layer.

Description

Nitride electronic device and its manufacturing method {Nitride electronic device and method for manufacturing it}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nitride electronic device and a method for manufacturing the same. Specifically, a group III nitride including a group III element such as gallium (Ga), aluminum (Al), indium (In), and nitrogen. (III-Nitride) Nitride electronic devices capable of implementing various types of nitride integrated structures on the same substrate through epitaxially lateral over-growth (ELOG) of semi-insulating gallium nitride (GaN) layers used in semiconductor electronic devices. The manufacturing method is related.

Gallium nitride (GaN) compound semiconductors are direct transition semiconductors and can control wavelengths from visible light to ultraviolet light. Gallium nitride compound semiconductors have high thermal and chemical stability, and have high electron mobility and saturated electron velocity. Gallium nitride compound semiconductors have superior physical properties compared to conventional gallium arsenide (GaAs) and indium phosphorus (InP) compound semiconductors such as large energy band gaps. Based on these characteristics, gallium nitride compound semiconductors are optical devices such as light emitting diodes (LEDs) and laser diodes (LDs) in the visible region, and next generation wireless and satellite communications requiring high power and high frequency characteristics. Existing compound semiconductors, such as systems, are being expanded to applications with limitations.

The gallium nitride-based electronic device includes a barrier layer composed of aluminum gallium nitride (AlGaN), indium aluminum nitride (InAlN), and aluminum nitride (AlN), a channel layer used as an electron transport path, Epi-structure consisting of semi-insulating layer for device isolation and leakage current reduction, ohmic contact by low-resistance metal material, schottky contact with high barrier potential, etc. The performance is determined by the process technology, the high frequency operation, and the device design to determine the current operating range.

However, in order to simultaneously implement an integrated structure having various characteristics on a single substrate, various constraints are placed on the design of the epi structure, the device process, and the device design, which are obstacles to the GaN-based electronic device implementation.

Therefore, in order to fabricate GaN-based field effect transistors (FETs), it is necessary to develop epistructures, process technologies, and device design technologies that can manufacture various FET devices on a single substrate.

The present invention was devised for the above necessity, and it is possible to achieve various characteristics on a single substrate by using a reprocessing technology using a GaN layer, which is a semi-insulating layer, and a unit process and design technology having different channel layer and barrier layer structures through regrowth. An object of the present invention is to provide an electronic device having an integrated structure and a method of manufacturing the same.

To this end, in the nitride electronic device according to the present invention, a low temperature buffer layer, a first semi-insulating nitride layer, a first channel layer, and a first barrier layer are sequentially stacked on a substrate, and a portion of the first semi-insulating nitride layer is etched. A first nitride integrated structure and a second nitride integrated structure in which a second semi-insulating nitride layer, a second channel layer, and a second barrier layer are sequentially stacked on portions of the first semi-insulating nitride layer. .

In addition, the method for manufacturing a nitride electronic device according to the present invention comprises the steps of forming an epi structure in which the low temperature buffer layer, the first semi-insulating nitride layer, the first channel layer and the first barrier layer are sequentially stacked on the substrate; Stacking a first dielectric layer for pattern formation on the first barrier layer and etching a portion of the first barrier layer, the first channel layer, and the first semi-insulating nitride layer, and etching the etched first semi-insulating nitride layer Regrowing a second semi-insulating nitride layer on the layer, sequentially laminating a second channel layer and a second barrier layer on the second semi-insulating nitride layer, and forming a pattern on the second barrier layer. Stacking a second dielectric layer and etching the second barrier layer, the second channel layer and the second semi-insulating nitride layer, removing the first and second dielectric layers and removing metal from the first and second barrier layers Laminating an electrode layer The.

According to the present invention, various effects can be obtained by integrating various devices using a semi-insulating GaN layer that limits separation and leakage current between devices in an electronic device.

Using a regrowth technology on a single substrate, compound semiconductor integrated circuits that simultaneously fabricate various types of devices can be realized.

Since different types of epi-structures can be grown, integration of high frequency devices having different operating frequencies, integration of depleted mode (normally-on) and incremental mode (normally-off) devices by controlling the thickness of the barrier layer In addition, various types of electronic devices, such as a high frequency device composed of a channel layer and a barrier layer and a high current device composed of a channel layer or a Schottky diode, can be formed as necessary.

In addition, by integrating the electronic device in the vertical direction, it is possible to improve the integration of the device in the same area compared to the existing horizontal device arrangement, and in the semiconductor integration process, the device is moved in the vertical direction while making the surface flat in the horizontal direction. The advantage is that it can be integrated.

1 is a cross-sectional structural view of a GaN electronic device according to the present invention.
2 to 9 is a process flow diagram for a method of manufacturing a GaN electronic device according to the present invention.
FIG. 10 is a cross-sectional structure diagram of a GaN electronic device in which the first channel layer and the second channel layer are omitted in the GaN electronic device structure of FIG.
FIG. 11 is a cross-sectional structural view of a GaN electronic device in which the first integrated structure includes only a channel layer and the second integrated structure includes a channel layer and a barrier layer in the GaN electronic device structure of FIG. 1.
12 is a cross-sectional structural view of a GaN electronic device in which the first integrated structure includes a channel layer and a barrier layer, and the second integrated structure includes only a channel layer in the GaN electronic device structure of FIG.
FIG. 13 is a cross-sectional structural view of a GaN electronic device in which the first barrier layer and the second barrier layer are omitted in the GaN electronic device structure of FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The configuration of the present invention and the operation and effect thereof will be clearly understood through the following detailed description.

Prior to the detailed description of the present invention, the same components are denoted by the same reference numerals as much as possible even if displayed on different drawings, and the known components will be omitted if it is determined that the gist of the present invention may obscure the gist of the present invention. do.

1 is a cross-sectional view of a GaN electronic device according to an embodiment of the present invention.

As shown in FIG. 1, a GaN electronic device according to an embodiment of the present invention may include a sapphire substrate 101, a low temperature buffer layer 102, a first semi-insulating GaN layer 103, A first channel layer 104, a first barrier layer 105, a second semi-insulating GaN layer 107, a second channel layer 108, a second barrier layer 109, An ohmic contact layer-source electrode layer 111, an ohmic contact layer-drain electrode layer 112, and a Schottky contact layer-gate electrode layer 113.

According to an embodiment of the present invention, the second semi-insulating GaN layer 107 is used for device isolation and reducing the leakage current of the GaN electronic device, and the first and the second semi-insulating GaN layer 107 are re-grown. By implementing the electrical insulation and device isolation characteristics between the second GaN integrated structure, it is possible to manufacture an electronic device that can implement a variety of devices of the same or different types on the same substrate.

2 to 9 illustrate a manufacturing process of a GaN electronic device according to an embodiment of the present invention.

Looking at the manufacturing process of the GaN electronic device, first to form a basic epi structure. The epitaxial structure includes a low temperature buffer layer 102, a first semi-insulating GaN layer 103, a first channel layer 104 for electron transfer, and a two-dimensional electron gas layer on the sapphire substrate 101. It is formed by sequentially stacking the first barrier layer 105 forming DEG).

Thereafter, after etching the first SiO ₂ layer or the first SiN _x layer 106 for the etching process for device integration, the first channel layer 104 and the first barrier layer 105 are etched. Next, the second semi-insulating GaN layer 107 is regrown on the exposed first semi-insulating GaN layer 103. After the two-dimensional surface growth is completed, the second channel layer 108 and the second barrier layer 109 are sequentially stacked. At this time, the epitaxial characteristics of the semi-insulating GaN layer, the channel layer, and the barrier layer, which are grown, are determined according to the characteristics of the device to be integrated on a single substrate, and various devices can be integrated.

When regrowth is complete, a second SiO ₂ layer or SiN _x layer 110 is deposited and patterned in opposition to the first mask patterning. The first SiO ₂ layer or SiN _x layer 106 is then etched and the exposed first SiO ₂ layer or SiN _x layer 106 is removed.

Next, an electrode layer for fabricating an electronic device is formed, which forms an ohmic contact between the source electrode and the drain electrode according to the design of the device pattern, and then forms a schottky electrode of the gate electrode. Based on this process, the same or different GaN devices can be integrated on a single substrate.

2 shows an epitaxial layer which is a basic structure of an electronic device using a GaN compound semiconductor. The epitaxial layer has a structure in which a sapphire substrate 101, a low temperature buffer layer 102, a first semi-insulating GaN layer 103, a first channel layer 104, and a first barrier layer 105 are sequentially stacked.

Looking at the manufacturing process step of the epi-structure layer, first, the low temperature buffer layer 102 is grown on the sapphire substrate (101). Next, in order to reduce the electrical insulation and leakage current of the electronic device, the first semi-insulating GaN layer 103 is grown to a thickness of 2 to 3 μm in the low temperature buffer layer 102. The first semi-insulating GaN layer 103 is grown into an epitaxial structure having high resistance through high temperature GaN growth rate change or GaN growth mode control.

Next, the first channel layer 104 is grown on the first semi-insulating GaN layer 103. The first channel layer 104 is a passage through which electrons forming a current flow in the electronic device move between the electrode layers, so that the first channel layer 104 does not have an impurity doping or uses a minimum dopant in order to have high mobility. In addition, the first channel layer 104 may be formed of a ternary compound semiconductor including indium (In) or aluminum (Al) in order to block leakage current and increase current limiting effect.

Next, a first barrier layer 105 is grown on the first channel layer 104. The first barrier layer 105 is mainly ternary (Al _x Ga _{1 - x} N, In _x Ga _{1 - x} N, In _x Al _{1 - x} N) or quaternary (In _x Al _y Ga _1-xy N) It consists of a compound semiconductor. At this time, the composition ratio of each element and the thickness of the barrier layer is determined according to the performance required in the GaN electronic device. Al _x Ga _{1 - x} N barrier layer is mainly used for high frequency electronic devices, Al composition ratio is 20 to 40% range, thickness is 10 to 40nm range.

3 and 4 illustrate the steps of pattern formation and etching for semi-insulating GaN regrowth.

In FIG. 3, the first dielectric layer 106 is used for pattern formation, wherein the thickness of the dielectric layer is in the range of 0.1 to 0.2 μm. SiO ₂ or SiN _x may be used as the first dielectric layer 106.

In FIG. 4, the etching thickness is up to the depth at which the first semi-insulating GaN layer 103 appears, and is typically in the range of 0.1 to 0.5 μm. 4 shows a first integrated structure.

The second semi-insulating GaN layer 107 is regrown on the surface of the first semi-insulating GaN 103 etched in FIG. 5, and the second channel layer 108 and the second barrier layer 109 are sequentially stacked. In this case, the total thickness of the second integrated structure to be grown should not exceed 1 μm in consideration of pattern work. The detailed configuration of the second channel layer 108 and the second barrier layer 109 is similar to the first channel layer 104 and the first barrier layer 105, and should be designed according to the characteristics of the GaN electronic device.

6 to 9 briefly illustrate the manufacturing process steps of the GaN electronic device.

In FIG. 6, a second dielectric layer 110 is formed for an etching process. In this case, the formed pattern is opposite to the first dielectric layer 106. SiO ₂ or SiN _x may be used as the second dielectric layer 110.

In FIG. 7, the etching process is performed up to the first dielectric layer 106. In FIG. 8, the first dielectric layer 106 and the second dielectric layer 110 used for pattern formation are removed, and the ohmic metal electrode layers 111 and 112 are laminated according to the design structure of the GaN electronic device in FIG. The GaN electronic device of FIG. 1 is fabricated by laminating the key metal electrode layer 113.

10 to 13 illustrate various types of electronic device structures based on the structure of the GaN electronic device shown in FIG. 1.

10 illustrates a structure in which the first channel layer 104 and the second channel layer 108 are omitted. In the case of the high frequency electronic device, the channel layer may be omitted depending on the characteristics of the first semi-insulating GaN layer 103 and the second semi-insulating GaN layer 107.

FIG. 11 illustrates a structure in which the first barrier layer 105 is omitted, and FIG. 12 illustrates a structure in which the second barrier layer 109 is omitted.

Most electronic devices including a barrier layer have a high electron mobility transistor (HEMT) structure, and electronic devices without a barrier layer have a high current driving characteristic (MESFET). Transistor) structure.

FIG. 13 illustrates a structure in which both the first barrier layer and the second barrier layer are omitted, and each includes only a channel layer. According to the characteristics of the channel layer, a structure in which the same or different types of metal field effect transistors are integrated is shown.

The foregoing description is merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the spirit of the present invention. Accordingly, the embodiments disclosed in the specification of the present invention are not intended to limit the present invention. The scope of the present invention should be construed according to the following claims, and all the techniques within the scope of equivalents should be construed as being included in the scope of the present invention.

101: sapphire substrate 102: low temperature buffer layer
103: first semi-insulating GaN layer 104: first channel layer
105: first barrier layer 106: first SiO ₂ or SiN _x layer
107: second semi-insulating GaN layer 108: second channel layer
109: second barrier layer 110: second SiO ₂ or SiN _x layer
111: ohmic contact-source 112: ohmic contact-drain
113: Schottky contact gate

Claims (10)

A first nitride integrated structure in which a first semi-insulating nitride layer is laminated on a substrate and a portion of the first semi-insulating nitride layer is etched;
And a second nitride integrated structure in which a second semi-insulating nitride layer is stacked on the partially etched portion of the first semi-insulating nitride layer through a regrowth technology for electrical insulation and device isolation.
The method of claim 1,
And the channel layer / barrier layer of the first nitride integrated structure and the channel layer / barrier layer of the second nitride integrated structure are the same or different.
The method of claim 2,
The first nitride integrated structure operates in a depleted mode (thickly-on) with a thicker barrier layer, and the second nitride integrated structure operates in a normally increased (off) mode with a thinner barrier layer. Electronic devices.
The method of claim 2,
The first nitride integrated structure operates in a normally-off thinner barrier layer, and the second nitride integrated structure operates in a depleted mode (thickly-on) thicker barrier layer. device.
The method of claim 2,
The first and second nitride integrated structure is composed of only a barrier layer, each of the nitride electronic device, characterized in that it operates as a high frequency electronic device or a high power electronic device.
The method of claim 2,
The first nitride integrated structure operates as a field effect transistor (MESFET) or a schottky diode composed of a channel layer, and the second nitride integrated structure operates as a high frequency device or a high power device composed of a channel layer and a barrier layer. A nitride integrated device, characterized in that.
The method of claim 2,
The first nitride integrated structure operates as a high frequency device or a high power device composed of a channel layer and a barrier layer, and the second nitride integrated structure operates as a field effect transistor (MESFET) or a schottky diode composed of a channel layer. A nitride integrated device, characterized in that.
The method of claim 2,
The first and the second nitride integrated structure is composed of only a channel layer, each of the nitride integrated device, characterized in that it operates as a field effect transistor (MESFET) or a schottky diode (schottky diode).
Forming an epi structure on which a low temperature buffer layer, a first semi-insulating nitride layer, a first channel layer, and a first barrier layer are sequentially stacked;
Stacking a first dielectric layer for pattern formation on the first barrier layer and etching portions of the first barrier layer, the first channel layer, and the first semi-insulating nitride layer;
Regrowing a second semi-insulating nitride layer on the etched first semi-insulating nitride layer;
Sequentially stacking a second channel layer and a second barrier layer on the second semi-insulating nitride layer;
Stacking a second dielectric layer for pattern formation on the second barrier layer and etching the second barrier layer, the second channel layer, and the second semi-insulating nitride layer;
Removing the first and second dielectric layers and depositing a metal electrode layer on the first and second barrier layers.
10. The method of claim 9,
And the second dielectric layer is stacked opposite to the pattern of the first dielectric layer.

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