KR20140131167A - Nitride semiconductor and method thereof - Google Patents

Abstract

Provided are a nitride semiconductor device where a GaN layer, AlGaN layer, a p-GaN layer and a gate insulating layer (or oxide layer) formed by oxidizing a part of the p-GaN layer are successively stacked, and a method thereof. For this, a semiconductor device according to one embodiment can include: a GaN layer; AlGaN layer formed on the GaN layer; a p-GaN layer formed on the AlGaN layer; a gate oxide layer formed on the p-GaN layer; a gate electrode formed on the gate oxide layer; and a source electrode and a drain electrode formed on a part of the AlGaN layer.

Description

[0001] NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING [0002]

The present invention relates to a semiconductor device in which a far-off characteristic is realized based on a p-GaN layer, in which a p-GaN layer is partially oxidized by photoelectrochemistry to form a gate insulating film (or an oxide film) To a nitride semiconductor device and a method of manufacturing the same.

Nitride semiconductors have been studied with high critical electric field, low on resistance, high temperature and high frequency operation characteristics compared with silicon and are being studied as materials of next generation semiconductor devices.

Recently, mainstream power MOSFETs and IGBTs have been widely used in high output power devices, and devices such as HEMTs, HFETs, and MOSFETs have been studied in GaN series.

In the case of HEMTs, high-electron mobility is used for communication devices having high-frequency characteristics.

In addition, HEMTs have been used for power semiconductor devices and communication devices with high frequency characteristics. In recent years, hybrid / fuel cell vehicles are being developed, and hybrid cars are being launched by many overseas companies. A voltage booster converter that connects a motor and a generator in a hybrid vehicle and a semiconductor switch in the inverter require reliable operation at high temperatures due to the heat generated by the engine. The wide bandgap of GaN enables reliable high temperature operation and is suitable as a next-generation semiconductor switch in hybrid vehicles.

Among them, Furukawa Electric of Japan has announced the discrete high-electron-mobility transistor (HEMT) of AlGaN / GaN. It has high breakdown voltage of 750 V and low on-resistance of 6.3 mΩ-cm2, , Si superjunction MOSFET and SiC MESFET. In addition, GaN discrete was stable at a high temperature of 225 ℃.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is an exemplary diagram illustrating the general structure of a heterojunction field effect transistor (HFET).

Referring to FIG. 1, a general HFET can switch a 2DEG current flowing from a drain electrode to a source electrode through a schottky gate electrode.

A general HFET 10 includes a substrate (not shown), a first GaN layer 11 formed on the substrate, an AlGaN layer 12 formed on the first GaN layer, a second GaN layer 12 formed on the AlGaN layer, A layer 13, a gate electrode 14, a source electrode 15 and a drain electrode 16 formed on the second GaN layer.

This kind of HFET device is excellent in voltage and current characteristics and many attempts have been made to use it as a high output power device. However, it has a disadvantage that it has a normally-on mode unlike other devices such as MOSFET and IGBT .

In the case of a normally-on device, it is difficult to form a circuit due to its high complexity. Therefore, plasma treatment, p-GaN growth, and gate recession have been studied to increase the threshold voltage.

Each technique has advantages and disadvantages, especially in the case of a technology using a p-type gate, since the normally-off state can be maintained without decreasing the 2DEG.

However, p-type gate HEMT devices require advanced epitaxial layer growth technology, and pn junctions formed inevitably make it difficult to control the leakage current.

The present invention relates to a semiconductor device in which a far-off characteristic is realized based on a p-GaN layer, in which a p-GaN layer is partially oxidized by photoelectrochemistry to form a gate insulating film (or an oxide film) And a method for fabricating the nitride semiconductor device.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a GaN layer; An AlGaN layer formed on the GaN layer; A p-GaN layer formed on the AlGaN layer; A gate oxide layer formed on the p-GaN layer; A gate electrode formed on the gate oxide layer; And a source electrode and a drain electrode formed on a part of the AlGaN layer.

As an example related to the present specification, the gate oxide layer may be formed by oxidizing a part of the p-GaN layer.

As an example related to the present specification, the gate oxide layer may be formed by oxidizing the p-GaN layer based on a photoelectrochemical (PEC) method.

As an example related to the present specification, the gate oxide film layer may be made of GaO _x , and x may be 0.1 to 2.0.

As one example related to the present specification, the gate oxide layer may be made of Ga ₂ O ₃ .

As an example related to the present specification, the thickness of the gate oxide layer may be 0.1 nm to 2 um.

As an example related to the present specification, the gate oxide layer may be formed to surround the upper and both sides of the p-GaN layer.

In one embodiment of the present invention, the p-GaN layer is formed by doping with a p-type dopant, and the p-type dopant may be at least one of Mg and Zn.

As an example related to the present specification, the concentration of the p-type dopant, may be one of ^{1e 12 / cm 3 ~ 1e 21} / cm 3.

As an example related to the present specification, the thickness of the p-GaN layer may be 1 nm to 1 μm.

As an example related to the present specification, the thickness of the GaN layer may be 0.5 um to 7 um.

As an example related to the present specification, the GaN layer may be doped with at least one dopant of Mg, C and Fe, and the at least one dopant concentration may be 1e16 / cm3 to 5e20 / cm3.

As one example related to the present specification, the thickness of the AlGaN layer may be 2 nm to 100 nm.

As an example related to the present specification, the above-mentioned half-tone element may further include a GaN cap layer formed on the AlGaN layer.

As an example related to the present specification, the thickness of the GaN cap layer may be 2 nm to 10 nm.

As one example related to the present specification, the GaN layer may be formed on the buffer layer.

As one example related to the present specification, the buffer layer may be made of at least one of AlN, AlGaN, and superlattice structures.

As an example related to the present specification, the buffer layer may be formed on a substrate.

As one example related to the present specification, the substrate may be made of at least one of Si, SiC, Sapphire, and GaN.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: forming a buffer layer on a substrate; Forming a GaN layer on the buffer layer; Forming an AlGaN layer on the GaN layer; Forming a p-GaN layer on the AlGaN layer; Etching a portion of the p-GaN layer to form source and drain electrodes separated from each other on the open AlGaN layer; Forming a gate oxide layer by oxidizing a part of the p-GaN layer; And forming a gate electrode on the gate oxide layer.

One example of the buffer layer, the GaN layer, the AlGaN layer, and the p-GaN layer may be formed by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), helium vapor deposition (HVPE), plasma-enhanced chemical vapor deposition (PECVD), sputtering, and atomic layer deposition (ALD).

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, comprising: forming a buffer layer on a substrate; Forming a GaN layer on the buffer layer; Forming an AlGaN layer on the GaN layer; Forming a p-GaN layer on the AlGaN layer; Oxidizing the upper region of the p-GaN layer to form a gate oxide layer; Etching a portion of the gate oxide layer and the p-GaN layer to form source and drain electrodes separated from each other on the open AlGaN layer; And forming a gate electrode on the gate oxide layer.

According to an embodiment disclosed in this specification, a nitride semiconductor device including a sequentially stacked GaN layer, an AlGaN layer, a p-GaN layer, and a gate insulating film (or oxide film) formed by partially oxidizing the p-GaN layer, ≪ / RTI >

Particularly, according to the semiconductor device disclosed in this specification, a normally-on state is realized based on a p-GaN layer, and a part of the p-GaN layer is oxidized based on photoelectrochemistry to form a gate insulating film, There is an advantage that a nitride semiconductor device in which current can be drastically reduced and a manufacturing method thereof can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is an exemplary diagram illustrating the general structure of a heterojunction field effect transistor (HFET).
2 is an exemplary view showing a structure of a semiconductor device according to an embodiment disclosed herein.
3 is an exemplary view showing a photoelectric chemical process for forming a gate oxide layer according to an embodiment disclosed herein.
4 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment disclosed herein.
5 is an exemplary view showing a method of manufacturing a semiconductor device according to an embodiment disclosed herein.
6 is a flowchart showing a method of manufacturing a semiconductor device according to another embodiment disclosed herein.
7 is an exemplary view showing a method of manufacturing a semiconductor device according to an embodiment disclosed in this specification.

The techniques disclosed herein can be applied to a heterojunction field effect transistor and a manufacturing method thereof. However, the technique disclosed in this specification is not limited thereto, and can be applied to all nitride-based semiconductor devices to which the technical idea of the above-described technique can be applied and a manufacturing method thereof.

The technique disclosed in this specification relates to a nitride semiconductor device including a sequentially stacked GaN layer, an AlGaN layer, a p-GaN layer, and a gate insulating film (or a gate oxide film) formed by partially oxidizing the p-GaN layer and a method of manufacturing the same will be.

In particular, the technique disclosed in this specification realizes a normally-on state based on a p-GaN layer, and oxidizes a part of the p-GaN layer based on photoelectrochemistry to form a gate insulating film (or an oxide film) To a nitride semiconductor device in which a leakage current can be remarkably reduced and a manufacturing method thereof.

The p-type gate HEMT device can maintain the normally-off characteristic without decreasing the 2DEG density. However, it can be disadvantageous in that it can not control the current flowing in the on-state of the pn junction, that is, Ig (gate current).

The normally-off characteristic is maintained by depletion of the pn junction, but a forward current may occur when a gate voltage is applied across the pn-junction barrier.

Increasing the gate current means that unwanted losses occur, which can reduce the efficiency of the device. To overcome this, the technique disclosed in this specification discloses an insulating film capable of blocking gate current between a p-type gate and a gate metal.

In a typical metal-insulator-semiconductor (MIS) structure, the gate current is very low due to the insulator inserted between the gate electrode and the semiconductor. However, since the process called recess is inserted for the normally-off characteristic, there is a disadvantage of damaging the current flowing in the on-state. In addition, there is a disadvantage in that the reliability is deteriorated due to a reduction in device characteristics due to defects between the insulator and the semiconductor interface.

The technique disclosed in this specification proposes a p-type gate MIS HEMT in order to reduce the gate current inevitably while making the most of the advantage of the p-type gate HEMT.

In particular, according to one embodiment, device characteristics are improved using a photo-electrochemical oxidation method to form a high-quality insulator.

It is noted that the technical terms used herein are used only to describe specific embodiments and are not intended to limit the scope of the technology disclosed herein. Also, the technical terms used herein should be interpreted as being generally understood by those skilled in the art to which the presently disclosed subject matter belongs, unless the context clearly dictates otherwise in this specification, Should not be construed in a broader sense, or interpreted in an oversimplified sense. In addition, when a technical term used in this specification is an erroneous technical term that does not accurately express the concept of the technology disclosed in this specification, it should be understood that technical terms which can be understood by a person skilled in the art are replaced. Also, the general terms used in the present specification should be interpreted in accordance with the predefined or prior context, and should not be construed as being excessively reduced in meaning.

Also, the singular forms "as used herein include plural referents unless the context clearly dictates otherwise. In this specification, the terms "comprising ", or" comprising ", etc. should not be construed as necessarily including the various elements or steps described in the specification, Or may be further comprised of additional components or steps.

Furthermore, terms including ordinals such as first, second, etc. used in this specification can be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein like reference numerals denote like or similar elements, and redundant description thereof will be omitted.

Further, in the description of the technology disclosed in this specification, a detailed description of related arts will be omitted if it is determined that the gist of the technology disclosed in this specification may be obscured. It is to be noted that the attached drawings are only for the purpose of easily understanding the concept of the technology disclosed in the present specification, and should not be construed as limiting the spirit of the technology by the attached drawings.

No far - off  Explanation of methods for forming characteristics

Since nitride semiconductors have a high critical electric field and a high saturation electron mobility, a semiconductor device fabricated using the nitride semiconductor can exhibit high breakdown voltage and large current characteristics.

An example of this is an HFET device fabricated on the basis of a heterojunction structure of AlGaN / GaN.

HFET devices have excellent voltage and current characteristics, and many attempts have been made to use them as high output power devices. However, they may have a disadvantage of having a normally-on mode unlike other devices such as MOSFETs and IGBTs.

According to one embodiment, a method for fabricating a normally-off HEMT device may include a gate recess, fluorine treatment (or plasma treatment), and a p-type gate.

The gate recess method may be a method of cutting a part of a 2DEG through etching and introducing a Schottky gate to maintain the off characteristic. This can be a drawback to 2DEG loss.

The fluorine treatement method may be a method of depleting electrons by plasma treatment of F ions to maintain off characteristics. This may have drawbacks such as unwanted plasma damage.

Finally, in the case of p-type gate, depletion of pn junction can be used to maintain off characteristics.

However, there is a disadvantage that a leakage current flows when a bias over a junction barrier is applied. However, the p-type gate has a special advantage of maintaining off characteristics without affecting the 2DEG.

According to one embodiment, in the p-type gate method, there can be a p-GaN gate method as a technique capable of performing the normally off-switching while maintaining excellent current characteristics of the nitride semiconductor device.

When the p-GaN layer is formed under the gate electrode, the p-GaN layer and the underlying AlGaN / GaN structure form a p-n junction, and a depletion phenomenon may occur.

Therefore, the 2DEG layer disappears at the bottom of the gate, so that when the gate is grounded, the source and the drain can not flow current.

However, when a threshold voltage having a (+) sign is applied to the gate, the lower 2DEG layer of the gate disappears and the current flows and the switching operation can be performed.

 That is, when the p-GaN gate is used, the nitride semiconductor device can be driven to be normally off-driven and high current characteristics can be maintained.

This p-GaN gate technology can be a technique for growing GaN p-doped on an AlGaN / GaN heterojunction structure and forming a gate electrode therefor.

The p-GaN layer may serve to deplete the two-dimensional free electron gas (2DEG) present at the interface between AlGaN and GaN.

The technique disclosed herein relates to a nitride semiconductor power device using GaN and a method of manufacturing the same.

According to one embodiment, a normally-off device is manufactured without decreasing the 2DEG by using the epitaxial structure of p-GaN / AlGaN / GaN structure. In order to reduce the leakage current due to the pn junction, An insulating film (or oxide film) may be formed between the gate electrode and the gate electrode.

The insulating film may be formed using a photo-electrochemical oxidation method to maintain high purity characteristics.

The device fabricated by the above method has advantages of minimizing the leakage current and ensuring high reliability due to the insulating film / protective film of high purity.

This can increase the stability of the device to be operated at a high voltage, in particular, while preventing the number of carrier concentration or electron mobility of the 2DEG from decreasing.

Hereinafter, the structure of a semiconductor device according to one embodiment disclosed herein will be described with reference to FIGS. 2 to 3. FIG.

The work disclosed herein In the embodiment  Description of the semiconductor device according to

The semiconductor device according to one embodiment disclosed herein includes a GaN layer, an AlGaN layer formed on the GaN layer, a p-GaN layer formed on the AlGaN layer, a gate oxide layer formed on the p- A gate electrode formed on the gate oxide film (or insulating film) layer, and a source electrode and a drain electrode formed on a partial region of the AlGaN layer.

According to one embodiment, the gate oxide layer may be formed by oxidizing a part of the p-GaN layer.

In addition, according to one embodiment, the gate oxide layer may be formed by oxidizing the p-GaN layer based on a photoelectrochemical (PEC) method.

Also, according to one embodiment, the gate oxide layer may be made of GaO _x , and x may be 0.1 to 2.0.

According to an embodiment, the gate oxide layer may be made of Ga ₂ O ₃ .

Also, according to one embodiment, the thickness of the gate oxide layer may be 0.1 nm to 2 um.

Also, according to one embodiment, the gate oxide layer may be formed to surround the upper and both sides of the p-GaN layer.

Also, according to one embodiment, the p-GaN layer may be doped with a p-type dopant, and the p-type dopant may be at least one of Mg and Zn.

Also, according to one embodiment, the concentration of the p-type dopant may be ^{1 12} / cm ³ to 1 ²¹ / cm ³ .

Also, according to one embodiment, the thickness of the p-GaN layer may be 1 nm to 1 μm.

Also, according to one embodiment, the thickness of the GaN layer may be 0.5 um to 7 um.

Also, according to one embodiment, the GaN layer may be doped with at least one dopant of Mg, C, and Fe, and the at least one dopant concentration may be 1e16 / cm3 to 5e20 / cm3.

Also, according to one embodiment, the thickness of the AlGaN layer may be 2 nm to 100 nm.

Further, according to an embodiment, the semiconductor device may further include a GaN cap layer formed on the AlGaN layer.

Also, according to one embodiment, the GaN cap layer may have a thickness of 2 nm to 10 nm.

Also, according to one embodiment, the GaN layer may be formed on the buffer layer.

Also, according to one embodiment, the buffer layer may be formed of at least one of AlN, AlGaN, and superlattice structures.

Also, according to one embodiment, the buffer layer may be formed on a substrate.

According to an embodiment, the substrate may be made of at least one of Si, SiC, Sapphire, and GaN.

2 is an exemplary view showing a structure of a semiconductor device according to an embodiment disclosed herein.

Referring to FIG. 2, a semiconductor device 100 according to an embodiment disclosed herein includes a GaN layer 110, an AlGaN layer 120, a p-GaN layer 130, a gate oxide layer 140, A source electrode 150, a drain electrode 170, and a source electrode 160. [

In addition, according to one embodiment, the semiconductor device 100 may further include a buffer layer (not shown) positioned under the GaN layer 110.

Also, according to one embodiment, the semiconductor device 100 may further include a GaN cap layer (not shown).

The semiconductor device 100 according to the embodiment disclosed herein may switch the 2DEG current flowing from the drain electrode 170 to the source electrode 160 through the Schottky gate electrode 700 can do.

The buffer layer may be formed on a substrate (not shown).

According to one embodiment, the substrate may be n-type, p-type, or various types of materials. For example, the substrate may be at least one of an insulating substrate, a sapphire substrate, a GaN substrate, a SiC substrate, and a Si substrate. It will be apparent to those skilled in the art that various types of substrates may be applied to the semiconductor devices disclosed herein.

Further, the substrate can be removed after fabrication of the semiconductor device 100. [ Thus, the final structure of the semiconductor device 100 may be a structure without the substrate.

The buffer layer may be formed of various materials. For example, the buffer layer may be composed of at least one of AlN and AlGaN.

Also, according to one embodiment, the buffer layer may comprise a superlattice buffer structure (or superlattice layer).

According to one embodiment, when the buffer layer is made of AlN, the buffer layer can be grown under various conditions. For example, the buffer layer may include a first AlN layer grown at a low temperature and a second AlN layer grown on the first AlN layer and grown at a high temperature.

According to another embodiment, when the buffer layer is made of AlGaN, the composition ratio of Al can be changed in the stacking direction. For example, the buffer layer may be made of AlGaN whose composition of Al is gradually decreased in the laminating direction.

That is, the Al composition of the AlGaN layer can be represented by Al _x Ga _{1 - x} N (0 _{? X} ? 1). For example, the composition of Al may be continuous and gradually decrease. Further, for example, the composition of Al may be gradually decreased in a stepwise (or stepwise) manner.

It is apparent to those skilled in the art that the buffer layer may be formed based on various materials, composition ratios, and growth conditions.

The buffer layer may be formed in various ways (or methods). For example, the buffer layer may be formed by selectively growing a nitride semiconductor crystal. At least one of MOCVD, molecular beam epitaxy (MBE), and helium vapor deposition (HVPE) It can be formed on the basis of one. However, in consideration of the crystallinity of the buffer layer, MOCVD may be used for device fabrication.

When the buffer layer includes a superlattice layer (not shown), the superlattice layer may be formed by stacking a plurality of superlattice thin film layers in which two different thin film layers are stacked.

In other words, the superlattice layer may be formed by alternately stacking two different thin film layers.

The superlattice thin film layer may be formed of various materials. For example, the superlattice thin film layer may be at least one of AlN / GaN, AlN / AlGaN, and AlGaN / GaN. That is, this may mean that each of the two different thin film layers is composed of a combination of at least one of AlN / GaN, AlN / AlGaN, and AlGaN / GaN. It is apparent to those skilled in the art that the superlattice thin film layer may be formed of various materials.

According to one embodiment, the Al composition of the AlGaN may be represented by Al _x Ga _{1 - x} N (0 _{? X} ? 1), and the composition of Al may change in accordance with the lamination direction. For example, the composition of Al may be continuous and gradually decrease. Further, for example, the composition of Al may be gradually decreased in a stepwise (or stepwise) manner.

According to one embodiment, the thickness of each of the two different thin film layers may be 1 nm to 100 nm. In particular, the thickness of each of the two different thin film layers may be 5 nm to 35 nm.

Also, according to one embodiment, the superlattice layer may include 3 to 500 superlattice thin film layers. In other words, the superlattice layer may have 3 to 500 pairs of the two different thin film layers. In other words, the superlattice layer may be formed by stacking the two different thin film layers alternately 5 to 999 times.

The superlattice layer can be formed in various ways (or methods). For example, the superlattice layer may be formed by selectively growing nitride semiconductor crystals. The superlattice layer may be formed by MOCVD, molecular beam epitaxy (MBE), and helium vapor deposition (HVPE) Or the like. However, considering the crystallinity of the superlattice layer, MOCVD may be used for device fabrication.

According to one embodiment disclosed herein, the superlattice buffer structure (or superlattice layer) may be formed by doping a specific dopant.

According to one embodiment, the specific dopant may be a p-type dopant. For example, the p-type dopant may be at least one of Mg, C, and Fe.

According to an embodiment disclosed herein, the concentration of the p-type dopant may be 1e ¹⁶ / cm ³ to 5e ²⁰ / cm ³ . In particular, the concentration of the p-type dopant may be 3e ¹⁷ / cm ³ to 1e ²⁰ / cm ³ .

Also, according to one embodiment, the concentration of the p-type dopant may be gradually decreased in the stacking direction of the superlattice layer. For example, the concentration of the p-type dopant may be continuous and gradually decrease. Also, for example, the concentration of the p-type dopant may be gradually decreased stepwise.

The thickness of the GaN layer 110 may be 0.1 um to 100 um. In particular, the GaN layer 300 may have a thickness of 0.5 um to 7 um.

The GaN layer 110 may be formed in various manners (or methods). For example, the GaN layer 110 may be formed by selectively growing a nitride semiconductor crystal. The GaN layer 110 may be formed by a metal organic vapor phase epitaxy (MOCVD) method, a molecular beam epitaxial growth method (MBE) HVPE). ≪ / RTI > However, considering the crystallinity of the GaN 110, MOCVD may be used for device fabrication.

According to one embodiment, the semiconductor device 100 may include a high-resistance layer for exhibiting semi-insulating characteristics of a GaN channel formed by implanting at least one dopant of C, Fe, and Mg dopants on the GaN layer 110 A GaN layer (not shown). Here, the concentration of the at least one dopant may be at least one of Mg, C, and Fe. The concentration of the at least one dopant may be 1e ¹⁶ / cm ³ to 5e ²⁰ / cm ³ . In particular, the concentration of the at least one dopant may be 3e ¹⁷ / cm ³ to 1e ²⁰ / cm ³ .

The AlGaN layer 120 may be formed on the GaN layer 110. The AlGaN layer 120 may serve as an active layer.

According to one embodiment, the thickness of the AlGaN layer 120 may range from 0 nm to 100 nm, and the thickness of the AlGaN layer 400 may range from 10 nm to 30 nm.

The AlGaN layer 120 may have a variety of materials and compositions. For example, the AlGaN layer 120 may be composed of Al _x Ga _{1 - x} N. Here, x may be from 0.01 to 1. It is apparent to those skilled in the art that the AlGaN layer 120 may be formed of various materials or composition ratios.

The AlGaN layer 120 may be formed by various methods (or methods). For example, the AlGaN layer 120 may be formed by selectively growing a nitride semiconductor crystal. The AlGaN layer 120 may be formed by a metal organic vapor phase epitaxy (MOCVD) method, a molecular beam epitaxial growth method (MBE) HVPE). ≪ / RTI > However, considering the crystallinity of the AlGaN layer 120, the MOCVD method may be used for device fabrication.

The GaN cap layer may be formed on the AlGaN layer 120 and may be formed by growing GaN thinly.

According to one embodiment, the thickness of the GaN cap layer may be in the range of 0 nm to 100 nm, particularly 2 nm to 10 nm. The GaN cap layer may serve to prevent surface leakage current.

The source electrode 160 and the drain electrode 170 may be formed on a part of the AlGaN layer 120. In addition, when the semiconductor device 100 further includes the GaN cap layer, the semiconductor device 100 may be formed on a part of the GaN cap layer.

The p-GaN layer 130 may be formed on the AlGaN layer 120.

The p-GaN layer 130 may be doped with a p-type dopant, and the p-type dopant may be at least one of Mg and Zn.

According to one embodiment, the concentration of the p-type dopant may be 1e ¹² / cm ³ to 1e ²¹ / cm ³ .

Also, according to one embodiment, the thickness of the p-GaN layer 130 may be 1 nm to 1 μm.

The p-GaN layer 130 may be formed by various methods (or methods). For example, the p-GaN layer 130 may be formed by selectively growing a nitride semiconductor crystal. The p-GaN layer 130 may be formed by metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and helium vapor deposition (HVPE). ≪ / RTI > However, considering the crystallinity of the p-GaN layer 130, MOCVD may be used for device fabrication.

After the p-GaN layer 130 is grown (or epitaxially grown), holes may be formed in p-GaN through activation of p-GaN. Here, the activation temperature may be in the range of 800 to 1100 ° C.

The gate oxide layer 140 may be formed on the p-GaN layer 130.

The gate oxide layer 140 may be formed by oxidizing a part of the p-GaN layer 130.

According to one embodiment, the gate oxide layer 140 may be formed by oxidizing the p-GaN layer 130 based on a photoelectrochemical (PEC) method.

Also, according to one embodiment, the gate oxide layer 140 is made of GaO _x , and x may be 0.1 to 2.0. For example, the gate oxide layer 140 may be made of Ga ₂ O ₃ .

Also, according to one embodiment, the thickness of the gate oxide layer 140 may be 0.1 nm to 2 μm.

2, the gate oxide layer 140 may be formed so as to surround the upper and both sides of the p-GaN layer 130.

The gate electrode 150 may be formed on the gate oxide layer 140.

As described above, a 2DEG current flowing from the drain electrode 170 to the source electrode 160 can be generated through the control of the gate electrode 150. [

Hereinafter, a method of forming the gate oxide layer 140 using a photoelectrochemical method will be described in detail with reference to FIG.

3 is an exemplary view showing a photoelectric chemical process for forming a gate oxide layer according to an embodiment disclosed herein.

Referring to FIG. 3, gate, source, and drain electrodes are formed on the epi layer formed by the above-described method for the enhancement type semiconductor device, and a gate insulating film Oxide layer) can be formed using photoelectrochemistry.

The p-GaN layer may be oxidized by a photoelectrochemical method as shown in FIG. 3 after the portion not to form the gate insulating film is treated so as to cover the light source corresponding to the bandgap of p-GaN or AlGaN.

The processing of the portion where the gate insulating film is not to be formed may be performed by applying a photoresistor (PR) which is a photosensitive resistive material applied to the semiconductor surface to a portion where the gate insulating film is not formed have.

First, a first electrode 32 'is formed in a sample (or a nitride semiconductor) 28 to be oxidized, and immersed in an aqueous solution. For example, the aqueous solution may be water (H ₂ O) or an aqueous solution for PEC.

The second electrode 32 '' for giving the electric potential difference to the sample 28 is separated from the first electrode 32 'and immersed in the aqueous solution.

And a power supply unit 34 capable of supplying power is connected between the wires connecting the two electrodes 32 'and 32' '.

Then, when a positive voltage is applied to the sample 28 and the sample 28 is irradiated with a light source (or a UV light source) 26 containing light having energy corresponding to the bandgap of p-GaN, The p-GaN layer 130 may be oxidized.

A gate metal process is performed on the gate oxide layer 140 or the gate insulating layer formed using the photoelectrochemistry to form the gate electrode 150 and the source 160 and drain 170 electrodes It is possible to finally complete the enhancement type nitride semiconductor heterojunction semiconductor device.

It will be apparent to those skilled in the art that the gate oxide layer 140 may be formed by a variety of photoelectric chemical methods, and the scope of the present invention is not limited by the photoelectric chemical method disclosed in FIG. 3, Modified, modified, or improved photo-electrochemical methods can be applied to various forms within the scope of the present invention and the claims.

The work disclosed herein In the embodiment  Description of a method of manufacturing a semiconductor device according to

A method of manufacturing a semiconductor device according to an embodiment disclosed herein may be implemented as a part or a combination of the constituent elements or steps included in the embodiments described above or a combination of the embodiments, Overlapping portions may be omitted for clarity of the method of manufacturing a semiconductor device according to an embodiment.

A method of fabricating a semiconductor device according to an embodiment disclosed herein includes forming a buffer layer on a substrate, forming a GaN layer on the buffer layer, forming an AlGaN layer on the GaN layer, Forming a p-GaN layer on the p-GaN layer; etching a part of the p-GaN layer to form source and drain electrodes separated from each other on the open AlGaN layer; Oxidizing the gate oxide film to form a gate oxide film layer; and forming a gate electrode on the gate oxide film layer.

A method of fabricating a semiconductor device according to another embodiment disclosed herein includes forming a buffer layer on a substrate, forming a GaN layer on the buffer layer, forming an AlGaN layer on the GaN layer, Forming a p-GaN layer on the AlGaN layer, oxidizing an upper region of the p-GaN layer to form a gate oxide layer, etching a part of the gate oxide layer and the p- Forming a source electrode and a drain electrode separated from each other on the AlGaN layer, and forming a gate electrode on the gate oxide layer.

The difference between the two manufacturing methods described above is that, in the case of the former, a photolithography process capable of forming a pattern of pGaN on the epi layer (GaN / AlGaN / p-GaN) (Source and drain electrodes) are formed, and then a gate insulating film (for example, a Ga ₂ O ₃ gate insulator) is formed.

In the former case, as shown in FIG. 5, the gate oxide film layer may be formed to surround the upper and both sides of the p-GaN layer.

In the latter case, first, an upper region of the p-GaN layer is oxidized to form a gate oxide film layer, and then a photolithography process is performed to perform an etching process on the p-GaN / gate insulating film. Drain electrode) is formed.

In the latter case, as shown in FIG. 7, the gate oxide film layer may be located above the p-GaN layer.

According to one embodiment, the gate oxide layer may be formed by oxidizing the p-GaN layer based on a photoelectrochemical (PEC) method.

In addition, according to one embodiment, the gate oxide layer may be formed by oxidizing the p-GaN layer based on a photoelectrochemical (PEC) method.

Also, according to one embodiment, the gate oxide layer may be made of Ga ₂ O ₃ .

Also, according to one embodiment, the thickness of the gate oxide layer may be 0.1 nm to 2 um.

Also, according to one embodiment, the gate oxide layer may be formed to surround the upper and both sides of the p-GaN layer.

Also, according to one embodiment, the p-GaN layer may be doped with a p-type dopant, and the p-type dopant may be at least one of Mg and Zn.

Also, according to one embodiment, the concentration of the p-type dopant may be ^{1 12} / cm ³ to 1 ²¹ / cm ³ .

Also, according to one embodiment, the thickness of the p-GaN layer may be 1 nm to 1 μm.

According to one embodiment, one of the buffer layer, the GaN layer, the AlGaN layer, and the p-GaN layer may be formed by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or helium vapor deposition (HVPE), plasma-enhanced chemical vapor deposition (PECVD), sputtering, and atomic layer deposition (ALD).

4 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment disclosed herein.

Referring to FIG. 4, a method of manufacturing a semiconductor device according to an embodiment disclosed herein may include the following steps.

First, a buffer layer may be formed on a substrate (S110).

Next, a GaN layer may be formed on the buffer layer (S120).

Next, an AlGaN layer may be formed on the GaN layer (S130).

Next, a p-GaN layer formed on the AlGaN layer may be formed (S140).

Next, a part of the p-GaN layer is etched to form source and drain electrodes separated from each other on the opened AlGaN layer (S150).

Next, the upper region of the p-GaN layer may be oxidized to form a gate oxide layer (S160).

Next, a gate electrode may be formed on the gate oxide layer (S170).

5 is an exemplary view showing a method of manufacturing a semiconductor device according to an embodiment disclosed herein.

5, a buffer layer 102, a GaN layer 110, an AlGaN layer 120, and a p-GaN layer 130 are sequentially formed on a substrate 101 (FIG. 5A) -GaN layer 130 may be selectively etched (or etched).

A portion of the p-GaN layer 130 where the selective etching is performed may be a region where the source electrode 160 and the drain electrode 170 are formed.

That is, a part of the p-GaN layer 130 may be etched to form the source electrode 160 and the drain electrode 170 separated from each other on the opened AlGaN layer (FIG. 5 (b)).

Next, a part of the p-GaN layer 130 may be oxidized to form a gate oxide layer 140 (Fig. 5 (c)). In this case, as shown in FIG. 5C, the gate oxide layer 140 may be formed to surround the upper and both sides of the p-GaN layer 130.

Here, the gate oxide layer 140 may be formed by oxidizing the p-GaN layer 130 based on a photoelectrochemical (PEC) method.

The photoelectrochemical method is similar to that shown in FIG. 3, so a detailed description thereof will be omitted.

Next, a gate electrode 150 may be formed (or deposited) on the gate oxide layer 140 (FIG. 5 (d)).

6 is a flowchart showing a method of manufacturing a semiconductor device according to another embodiment disclosed herein.

Referring to FIG. 6, a method of manufacturing a semiconductor device according to an embodiment disclosed herein may include the following steps.

First, a buffer layer may be formed on a substrate (S110).

Next, a GaN layer may be formed on the buffer layer (S120).

Next, an AlGaN layer may be formed on the GaN layer (S130).

Next, a p-GaN layer formed on the AlGaN layer may be formed (S140).

Next, the upper region of the p-GaN layer may be oxidized to form a gate oxide layer (S210).

Next, a portion of the gate oxide layer and the p-GaN layer may be etched to form a source electrode and a drain electrode separated from each other on the open AlGaN layer (S220).

Next, a gate electrode may be formed on the gate oxide layer (S170).

7 is an exemplary view showing a method of manufacturing a semiconductor device according to an embodiment disclosed in this specification.

7, a buffer layer 102, a GaN layer 110, an AlGaN layer 120, and a p-GaN layer 130 are sequentially formed on a substrate 101 (Fig. 7A) The upper region of the p-GaN layer 130 may be oxidized to form the gate oxide layer 140 (Fig. 7 (b)).

Here, the gate oxide layer 140 may be formed by oxidizing the p-GaN layer 130 based on a photoelectrochemical (PEC) method.

The photoelectrochemical method is similar to that shown in FIG. 3, so a detailed description thereof will be omitted.

Next, selective etching (or etching) may be performed on the gate oxide layer 140 and a part of the p-GaN layer 130.

Next, the gate oxide layer 140 and a part of the p-GaN layer 130 are etched to form a source electrode 160 and a drain electrode 170 separated from each other on the opened AlGaN layer 120 (Fig. 7 (c)).

Next, a gate electrode 150 may be formed (or deposited) on the gate oxide layer 140 (Fig. 7 (d)).

As described above, according to one embodiment disclosed in the present specification, a nitride layer including a sequentially stacked GaN layer, an AlGaN layer, a p-GaN layer, and a gate insulating film (or oxide film) formed by partially oxidizing the p- A semiconductor device and a method of manufacturing the same are provided.

Particularly, according to the semiconductor device disclosed in this specification, a normally-on state is realized based on a p-GaN layer, and a part of the p-GaN layer is oxidized based on photoelectrochemistry to form a gate insulating film, There is an advantage that a nitride semiconductor device and a manufacturing method thereof capable of drastically reducing the current can be provided.

Specifically, the technology disclosed herein relates to a method for manufacturing the AlGaN / GaN HEMT device having a gate of the p-type, photoelectric chemical oxidation method (photo-electrochemical oxidation method) to the high through the Ga ₂ O ₃ is formed with reliability Lt; / RTI >

AlGaN / GaN HEMT devices with p-type gates compared to conventional AlGaN / GaN devices can easily control the operating voltage and can achieve a normally-off characteristic without reducing the 2DEG density.

However, the p-type gate structure may cause a pn junction (a p-type gate and an n-type AlGaN or GaN junction) and thus can not control the forward bias current due to the pn junction .

The technique disclosed in this specification is a method for reducing the gate current Ig while maintaining the basic characteristics of the device by forming an insulating film by oxidizing p-GaN by a method for further reducing the leakage current due to the pn junction in on-state .

In particular, the technique disclosed herein may be advantageous in that a highly reliable Ga ₂ O ₃ insulating film is formed by oxidizing p-GaN using a photo-electrochemical oxidation method.

When the thus formed element is used, there is an advantage that the leakage current flowing to the gate can be greatly reduced and the reliability of the element can be improved.

The scope of the present invention is not limited to the embodiments disclosed herein, and the present invention can be modified, changed, or improved in various forms within the scope of the present invention and the claims.

100: Semiconductor device 110: GaN layer
120: AlGaN layer 130: p-GaN
140: gate oxide layer 150: gate electrode
160: source electrode 170: drain electrode

Claims (29)

GaN layer;
An AlGaN layer formed on the GaN layer;
A p-GaN layer formed on the AlGaN layer;
A gate oxide layer formed on the p-GaN layer;
A gate electrode formed on the gate oxide layer; And
And a source electrode and a drain electrode formed on a part of the AlGaN layer. The semiconductor device according to claim 1, wherein the gate oxide film layer
And a part of the p-GaN layer is oxidized. The semiconductor device according to claim 2, wherein the gate oxide film layer
Wherein the p-GaN layer is formed by oxidizing based on a photoelectrochemical (PEC) method. The semiconductor device according to claim 1, wherein the gate oxide film layer
GaO _x ,
Wherein x is 0.1 to 2.0. The semiconductor device according to claim 4, wherein the gate oxide film layer
Ga ₂ O ₃ . The semiconductor device according to claim 1, wherein the thickness of the gate oxide film layer
0.1 nm to 2 [mu] m. The semiconductor device according to claim 1, wherein the gate oxide film layer
And the p-GaN layer is formed to surround the upper and both sides of the p-GaN layer. The p-GaN substrate according to claim 1,
doped with a p-type dopant,
The p-
Mg and < RTI ID = 0.0 > Zn. ≪ / RTI > 9. The method of claim 8, wherein the concentration of the p-
1e ¹² / cm ³ to 1e ²¹ / cm ³ . The p-GaN substrate according to claim 1, wherein the thickness of the p-
1 nm to 1 um. The GaN substrate according to claim 1,
0.5um to 7um. The GaN substrate according to claim 1,
Doped with at least one of Mg, C and Fe,
Wherein the at least one dopant concentration is selected from the group consisting of:
Cm < 3 > to 5e20 / cm < 3 >. The method according to claim 1, wherein the thickness of the AlGaN layer
Wherein the thickness of the semiconductor element is 2 nm to 100 nm. The method according to claim 1,
And a GaN cap layer formed on the AlGaN layer. 15. The GaN cap layer according to claim 14,
And is 2 nm to 10 nm. The GaN substrate according to claim 1,
And is formed on the buffer layer. 17. The method of claim 16,
AlN, AlGaN, and a superlattice structure. 17. The method of claim 16,
And is formed on a substrate. 19. The method of claim 18,
Si, SiC, Sapphire, and GaN. Forming a buffer layer on the substrate;
Forming a GaN layer on the buffer layer;
Forming an AlGaN layer on the GaN layer;
Forming a p-GaN layer on the AlGaN layer;
Etching a portion of the p-GaN layer to form source and drain electrodes separated from each other on the open AlGaN layer;
Forming a gate oxide layer by oxidizing a part of the p-GaN layer; And
And forming a gate electrode on the gate oxide film layer. The semiconductor device according to claim 20, wherein the gate oxide film layer
Wherein the p-GaN layer is formed by oxidizing based on a photoelectrochemical (PEC) method. The semiconductor device according to claim 20, wherein the gate oxide film layer
Ga ₂ O ₃ . 21. The method according to claim 20, wherein the thickness of the gate oxide film layer
0.1 nm to 2 [mu] m. The semiconductor device according to claim 20, wherein the gate oxide film layer
And the p-GaN layer is formed to surround the upper and both sides of the p-GaN layer. 21. The method of claim 20, wherein the p-
doped with a p-type dopant,
The p-
Mg and < RTI ID = 0.0 > Zn. ≪ / RTI > 26. The method of claim 25, wherein the concentration of the p-
1e ¹² / cm ³ to 1e ²¹ / cm ³ . 21. The method according to claim 20, wherein the thickness of the p-
1 nm to 1 [mu] m. 21. The method of claim 20, wherein one of the buffer layer, the GaN layer, the AlGaN layer, and the p-
At least one of metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), helium vapor deposition (HVPE), plasma enhanced chemical vapor deposition (PECVD), sputtering, and atomic layer deposition Wherein the semiconductor device is formed on the basis of a predetermined pattern. Forming a buffer layer on the substrate;
Forming a GaN layer on the buffer layer;
Forming an AlGaN layer on the GaN layer;
Forming a p-GaN layer on the AlGaN layer;
Oxidizing the upper region of the p-GaN layer to form a gate oxide layer;
Etching a portion of the gate oxide layer and the p-GaN layer to form source and drain electrodes separated from each other on the open AlGaN layer; And
And forming a gate electrode on the gate oxide film layer.

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