KR20150091704A - Nitride semiconductor and method thereof - Google Patents

Abstract

The present invention relates to a nitride semiconductor device and a manufacturing method thereof and, more particularly, to a nitride semiconductor device and a manufacturing method thereof, capable of reducing etching damage and reducing a gate current and maintaining the basic properties of the semiconductor device by forming an insulation film (or insulation layer) on the upper side and the lower side of the p-type gate layer made of AlGaN or GaN doped with a p-type dopant. For this, the semiconductor device according to one embodiment of the present invention includes a GaN channel layer, an AlGaN barrier layer which is formed on the GaN channel layer, a first gate insulation layer which is formed on a gate region defined on a part of the region of the AlGaN barrier layer, a p-type gate layer which is formed on the first gate insulation layer, is doped with the p-type dopant and is made of AlxG1-xN (0<=x<=1), and a second gate insulation layer which is formed on the p-type gate layer.

Description

[0001] NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING [0002]

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device and a manufacturing method thereof.

With the emphasis on green energy, the importance of power semiconductors is growing. Power semiconductors used in inverters such as electric vehicles, air conditioners and refrigerators are currently being manufactured by Silicon. However, nitride semiconductors of new materials are attracting attention as high critical electric field, low on resistance, high temperature and high frequency operation characteristics as compared with silicon and are being studied as materials of next generation power semiconductor devices.

Recently, mainstream power MOSFETs and IGBTs have been widely used in high output power devices, and devices such as HEMTs, HFETs, and MOSFETs have been studied in GaN series.

In the case of HEMTs, high-electron mobility is used for communication devices having high-frequency characteristics.

In addition, HEMTs have been used for power semiconductor devices and communication devices with high frequency characteristics. In recent years, hybrid / fuel cell vehicles are being developed, and hybrid cars are being launched by many overseas companies. A voltage booster converter that connects a motor and a generator in a hybrid vehicle and a semiconductor switch in the inverter require reliable operation at high temperatures due to the heat generated by the engine. The wide bandgap of GaN enables reliable high temperature operation and is suitable as a next-generation semiconductor switch in hybrid vehicles.

Among them, Furukawa Electric of Japan has announced the discrete high-electron-mobility transistor (HEMT) of AlGaN / GaN. It has high breakdown voltage of 750 V and low on-resistance of 6.3 mΩ-cm2, , Si superjunction MOSFET and SiC MESFET. In addition, GaN discrete was stable at a high temperature of 225 ℃.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is an exemplary diagram illustrating the general structure of a heterojunction field effect transistor (HFET).

Referring to FIG. 1, a general HFET can switch a 2DEG current flowing from a drain electrode to a source electrode through a schottky gate electrode.

A general HFET 10 includes a substrate (not shown), a first GaN layer 11 formed on the substrate, an AlGaN layer 12 formed on the first GaN layer, a second GaN layer 12 formed on the AlGaN layer, A layer 13, a gate electrode 14, a source electrode 15 and a drain electrode 16 formed on the second GaN layer.

On the other hand, this kind of HFET device is excellent in voltage and current characteristics and many attempts have been made to use it as a high output power device. However, unlike other devices such as MOSFET and IGBT, a disadvantage .

The technique disclosed in this specification relates to a nitride semiconductor device and a manufacturing method thereof, in which an insulating film (or an insulating layer) is formed on upper and lower portions of a p-type gate layer made of GaN or AlGaN doped with a p- And a nitride semiconductor device capable of reducing a gate current and reducing etching damage while maintaining characteristics of the nitride semiconductor device.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a GaN channel layer; An AlGaN barrier layer formed on the GaN channel layer; A first gate insulating layer formed in a gate region defined in a partial region on the AlGaN barrier layer; A p-type gate layer doped with a p-type dopant formed on the first gate insulating layer and made of Al _x Ga _{1 - x} N (0 _{? X} ? 1); And a second gate insulating layer formed on the p-type gate layer.

As an example related to the present specification, the semiconductor device may further include a gate electrode formed on the second gate insulating layer.

As one example related to the present specification, the p-type dopant may be at least one of Mg, C, Zn, and Fe.

As an example related to the present specification, the concentration of the p-type dopant, may be one of ^{1e 12 / cm 3 ~ 1e 21} / cm 3.

As an example related to the present specification, the thickness of the p-type gate layer may be 1 nm to 1 μm.

As an example related to the present specification, the first gate insulating layer may be made of at least one of AlN and Si _x N _y .

As one example related to the present specification, the thickness of the first gate insulating layer may be 0.1 nm to 5 nm.

According to one embodiment of the present invention, the second gate insulating layer may be made of at least one of SiO ₂ , Si _x N _y , HfO ₂ , Al ₂ O ₃ , ZnO, AlN, and Ga ₂ O ₃ .

As an example related to the present specification, the thickness of the second gate insulating layer may be 1 nm to 100 nm.

As an example related to the present specification, the semiconductor device may further include a source electrode and a drain electrode formed on a part of the AlGaN barrier layer.

As an example related to the present specification, the thickness of the GaN channel layer may be 0.5 um to 10 um.

As an example related to the present specification, the GaN channel layer may be doped with at least one dopant of Mg, C and Fe.

As an example related to the present specification, the at least one dopant concentration may be 3e ¹⁷ / cm ³ to 1e ²⁰ / cm ³ .

As an example related to the present specification, the thickness of the AlGaN barrier layer may be 0.1 nm to 100 nm.

As one example related to the present specification, the AlGaN barrier layer may include a plurality of layers made of AlGaN having different compositions of Al.

As an example related to the present specification, the number of the plurality of layers made of AlGaN having different Al compositions may be 2 to 5.

As an example related to the present specification, the Al composition of the AlGaN barrier layer may be continuously decreased with a specific slope in the stacking direction.

As one example related to the present specification, the Al composition of the AlGaN barrier layer may be discontinuously decreased in the stacking direction.

As one example related to the present specification, the GaN channel layer may be formed on the buffer layer.

As an example related to the present specification, the thickness of the buffer layer may be 1 nm to 7 um.

As an example related to the present specification, the buffer layer may include at least one of an AlN buffer layer made of AlN and an AlGaN buffer layer made of AlGaN.

As an example related to the present specification, the GaN channel layer may be formed on a substrate.

As one example related to the present specification, the substrate may be made of at least one of Si, SiC, Sapphire, and GaN.

According to one embodiment of the present invention, the first gate insulating layer and the second gate insulating layer may be formed based on at least one of metal organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD).

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, comprising: forming an AlGaN barrier layer on a GaN channel layer; Forming a first gate insulating layer in a gate region defined in a portion of the AlGaN barrier layer; Forming a p-type gate layer doped with a p-type dopant on the first gate insulating layer and made of Al _x Ga _{1 - x} N (0 _{? X} ? 1); And forming a second gate insulating layer on the p-type gate layer.

As an example related to the present specification, the method of manufacturing a semiconductor device may further include forming a gate electrode on the second gate insulating layer.

As one example related to the present specification, the p-type dopant may be at least one of Mg, C, Zn, and Fe.

As an example related to the present specification, the concentration of the p-type dopant, may be one of ^{1e 12 / cm 3 ~ 1e 21} / cm 3.

As an example related to the present specification, the thickness of the p-type gate layer may be 1 nm to 1 μm.

As an example related to the present specification, the first gate insulating layer may be made of at least one of AlN and Si _x N _y .

As one example related to the present specification, the thickness of the first gate insulating layer may be 0.1 nm to 5 nm.

According to one embodiment of the present invention, the second gate insulating layer may be made of at least one of SiO ₂ , Si _x N _y , HfO ₂ , Al ₂ O ₃ , ZnO, AlN, and Ga ₂ O ₃ .

As an example related to the present specification, the thickness of the second gate insulating layer may be 1 nm to 100 nm.

As an example related to the present specification, the method of manufacturing a semiconductor device may further include forming a source electrode and a drain electrode on a part of the AlGaN barrier layer.

According to one embodiment of the present invention, the first gate insulating layer and the second gate insulating layer may be formed based on at least one of metal organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD).

At least one of the GaN channel layer, the AlGaN barrier layer, and the p-type gate layer may be formed by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), helium vapor deposition (HVPE), Plasma-enhanced chemical vapor deposition (PECVD), sputtering, and atomic layer deposition (ALD).

According to one embodiment disclosed herein, a nitride semiconductor device and a method for fabricating the same are disclosed. In the nitride semiconductor device and method of manufacturing the same, an insulating film (or an insulating layer) is formed on upper and lower portions of a p-type gate layer made of GaN or AlGaN doped with a p- A nitride semiconductor device capable of reducing gate current and etching damage while maintaining basic characteristics of a device, and a method for manufacturing the same.

In particular, according to the semiconductor device disclosed in this specification, by providing a nitride-based semiconductor device having a structure in which an insulating film (or an insulating layer) is included in the upper and lower layers of a p-type gate layer, There is an advantage that it is possible to prevent the decrease of the gate current and to reduce the etching damage which occurs when the etching process for the p-type gate layer proceeds while making the most of advantages of the junction semiconductor device (for example, HFET).

Further, by forming the insulating film (or insulating layer) using MOCVD or ALD, there is an advantage that high-quality insulator and device characteristics are improved.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is an exemplary diagram illustrating the general structure of a heterojunction field effect transistor (HFET).
2 is an exemplary view showing a structure of a semiconductor device according to an embodiment disclosed herein.
3 is an exemplary view showing a configuration of a semiconductor device according to another embodiment disclosed herein.
4 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment disclosed herein.
5A to 5G are views illustrating an example of a method of manufacturing a semiconductor device according to an embodiment disclosed herein.

The techniques disclosed herein can be applied to a heterojunction field effect transistor and a manufacturing method thereof. However, the technique disclosed in this specification is not limited thereto, and can be applied to all nitride-based semiconductor devices to which the technical idea of the above-described technique can be applied and a manufacturing method thereof.

It is noted that the technical terms used herein are used only to describe specific embodiments and are not intended to limit the scope of the technology disclosed herein. Also, the technical terms used herein should be interpreted as being generally understood by those skilled in the art to which the presently disclosed subject matter belongs, unless the context clearly dictates otherwise in this specification, Should not be construed in a broader sense, or interpreted in an oversimplified sense. In addition, when a technical term used in this specification is an erroneous technical term that does not accurately express the concept of the technology disclosed in this specification, it should be understood that technical terms which can be understood by a person skilled in the art are replaced. Also, the general terms used in the present specification should be interpreted in accordance with the predefined or prior context, and should not be construed as being excessively reduced in meaning.

Also, the singular forms "as used herein include plural referents unless the context clearly dictates otherwise. In this specification, the terms "comprising ", or" comprising &quot;, etc. should not be construed as necessarily including the various elements or steps described in the specification, Or may be further comprised of additional components or steps.

Furthermore, terms including ordinals such as first, second, etc. used in this specification can be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein like reference numerals denote like or similar elements, and redundant description thereof will be omitted.

Further, in the description of the technology disclosed in this specification, a detailed description of related arts will be omitted if it is determined that the gist of the technology disclosed in this specification may be obscured. It is to be noted that the attached drawings are only for the purpose of easily understanding the concept of the technology disclosed in the present specification, and should not be construed as limiting the spirit of the technology by the attached drawings.

In recent years, according to the growth technology of a nitride semiconductor, the development of a light emitting diode and a blue-violet laser diode covering a red wavelength band in ultraviolet rays has been completed and has already been widely used in traffic lights, electric sign boards, mobile phones and the like.

Compared with Si-based devices, power-supply devices using nitride semiconductors have superior switching speed and withstand voltage characteristics, and have high current saturation rates, which is advantageous over Si-based devices for high-power, high-voltage applications.

That is, since GaN, which is a typical nitride semiconductor, has a large band gap energy and can form a two-dimensional 2DEG channel through heterojunction, the threshold voltage is large and high-speed operation can be performed.

These high power, high speed characteristics are attracting attention as a next generation power semiconductor material because they are well suited for power semiconductors that require high operating voltage and low energy loss on switching.

Since nitride semiconductors have a high critical electric field and a high saturation electron mobility, a semiconductor device fabricated using the nitride semiconductor is expected to exhibit a high breakdown voltage and a large current characteristic. An example of this is an HFET device fabricated on the basis of a heterojunction structure of AlGaN / GaN.

This type of HFET device is excellent in voltage and current characteristics, and many attempts have been made to use it as a high output power device, but it has a disadvantage that it has a normally-on mode unlike other devices such as MOSFET and IGBT .

In order to increase the threshold voltage, the plasma treatment, the gate recess and the p-type doping (p-type gate layer to p Type gate structure method).

In particular, the techniques disclosed herein provide a normally-on device to which a p-type doping scheme is applied.

According to one embodiment, a p-type gate structure method (or a P-type doping method) is a method of forming a GaN layer on a AlGaN barrier layer (AlGaN barrier layer) using a p-type dopant (e.g., Mg, Fe or the like) Or a method of increasing the threshold voltage by depletion of 2DEG (2 Dimensional Electron Gas) flowing between the AlGaN barrier layer and the GaN buffer layer as the AlGaN layer.

Generally, since depletion is performed only under the gate, the remaining p-type doped regions except the gate forming portion are removed through etching, and then the gate metal is deposited to form a normally off state.

The technique disclosed in this specification relates to a method of manufacturing a GaN (GaN) -type heterojunction element having a p-type gate structure.

Compared to conventional AlGaN / GaN devices, AlGaN / GaN HFET devices with p-type gate structures (or p-type gate layers) can easily control the operating voltage and can achieve a normally-off characteristic without reducing the 2DEG density .

However, a pn junction occurs (junction of the p-type gate layer with n-type AlGaN or GaN), and therefore it may be difficult to control the forward bias current due to the pn junction.

The technique disclosed in the present specification is characterized in that an insulating film (a first gate insulating layer and a second gate insulating layer to be described later) is formed on the upper and lower portions of the p-type gate layer to reduce the gate current and maintain the basic characteristics of the nitride- The present invention provides a semiconductor device and a manufacturing method capable of reducing etch damage.

In the nitride-based semiconductor device, In the buffer layer  Explanation for

In power semiconductors, nitride semiconductors (GaN) are attracting attention as devices with high breakdown voltage and low on-resistance.

However, it is difficult to grow the device because the cost of the substrate is high and it is difficult to grow the device to maintain the lattice mismatch without defective GaN.

In addition, sapphire and SiC can not be processed by conventional semiconductor processes in post-growth process, so new process processes may need to be developed.

For this reason, we will use Silicon, which is a low-cost, low-cost substrate for semiconductor processing. In the case of Silicon, lattice mismatch with GaN, which is a nitride semiconductor, If the device is fabricated, the leakage current of the device can be increased by acting as a leakage path.

Therefore, when a buffer layer such as AlGaN is inserted between the GaN and the silicon substrate, the defect density can be reduced by reducing the lattice mismatch, and the Epi stress due to the difference in the lattice constant between the GaN and the silicon is reduced , even if the thicker GaN is grown, the generation of cracks can be prevented.

In the case of the device using Grade AlGaN buffer, the AlGaN layer having 1 to 5 Al compositions is grown on the AlN nucleation layer, thereby reducing the latitude mismatch between the silicon and the GaN buffer layer and growing the thick GaN buffer layer There may be advantages to grow.

Hereinafter, the buffer layer in the nitride semiconductor device according to the embodiment disclosed in this specification will be described in more detail.

II-V compound semiconductors are advantageous for high-speed and high-power devices because they can produce devices with high mobility and high current density by using 2-dimentional electron gas (2DEG) due to heterojunction have.

However, due to the 2DEG generated by the structural characteristics, the device has a normally-on characteristic, and since the additional voltage is applied for the off state, the standby state of the device also consumes power.

Compound semiconductors such as GaN have a weak n-type doping effect without intentional doping due to N-vacancy occurring in the bonding process such as Gallium and Nitride, and donors derived from impurities existing in the reaction chamber .

This defects and impurities act to lower the resistivity of GaN, which may cause leakage current problems to the outside region of the active layer.

The MOCVD process is known to typically form GaN with an electron concentration of 1 x 10 ¹⁶ cm ^-3 .

In addition, since they are grown on different substrates such as sapphire, SiC, and Si, defects due to the difference in lattice constant with the substrate are generated. Therefore, when a conductive substrate such as Si is used, it is vulnerable to leakage current. Therefore, there is a need for a method for suppressing the leakage current and the leakage current through the buffer layer (or the buffer layer) and the normally off-off characteristic of the device.

There are several ways to reduce the leakage current from the epilayers in a nitride semiconductor power device with a heterojunction structure.

In particular, there may be a method of growing at least one buffer layer between the substrate and the GaN layer (or GaN channel layer) to reduce the leakage current.

In addition, in order to efficiently reduce the leakage current through the buffer layer, not only the semi-insulating function of the GaN channel needs to be strengthened, but also the crystal defects of the buffer layer for growing the buffer layer are minimized and the semi-insulating property is also increased, It may be necessary to minimize the vertical and lateral leakage currents.

This is a particularly necessary part of the operation of a high power device.

The technique disclosed in this specification proposes an effective epitaxial structure that reduces the leakage current of the buffer layer for GaN growth.

According to one embodiment disclosed herein, there may be various kinds of buffer layers for growing GaN on a substrate (for example, a Si substrate). For example, the buffer layer may have a structure including at least one of an AlN layer (an AlN buffer layer or an AlN nucleation layer) and an AlGaN layer (or an AlGaN buffer layer).

The above-mentioned buffer layer may mean a layer including at least one of an AlN buffer layer made of AlN and an AlGaN buffer layer made of AlGaN.

According to one embodiment, the AlN layer (AlN buffer layer or AlN nucleation layer) may comprise a plurality of layers of AlN grown at different temperatures.

For example, the number of the plurality of layers made of AlN grown at the different temperatures may be 2 to 5.

Also, for example, an AlN buffer can be used in combination of low temperature and high temperature. That is, the lower portion of the AlN buffer may be formed by low temperature growth, and the upper portion of the AlN buffer may be formed by high temperature growth. In this case, the AlN layer may include a first AlN layer grown at a low temperature and a second AlN layer grown on the first AlN layer and grown at a high temperature.

Also, according to one embodiment, the AlGaN buffer layer may include a plurality of layers made of AlGaN having different Al compositions.

For example, the number of the plurality of layers made of AlGaN having different Al compositions may be 2 to 5.

Also, for example, a continuous graded or graded buffer having a high Al content in the lower layer of the AlGaN buffer and a low Al composition in the upper layer may be used.

That is, according to one embodiment, the Al composition of at least one of the AlN buffer layer and the AlGaN buffer layer may be continuously decreased with a specific slope in the stacking direction.

According to another embodiment, the Al composition of at least one of the AlN buffer layer and the AlGaN buffer layer may be discontinuously decreased in the stacking direction.

According to the embodiment disclosed herein, the various types of buffer layers may be used as a single buffer layer, but may be combined with each other to be provided in one semiconductor element.

For example, in the semiconductor device according to an embodiment, the AlN buffer (or AlN buffer layer) may be formed on a substrate, and another kind of buffer layer may be formed thereon.

In this case, the AlN buffer layer is a seed layer for growing GaN on the substrate, and may be referred to as a nucleation layer.

In general, the type of the substrate may be Si, SiC, an insulating substrate (e.g., sapphire substrate), a GaN substrate, or the like.

For example, when the substrate is a Si substrate, when the GaN layer is grown (or deposited or laminated) directly on the Si substrate, the crystallinity of the GaN layer is lowered due to the difference in lattice constant between Si and GaN, There may be a problem that the leakage current increases and the breakdown voltage characteristic deteriorates.

Therefore, as described above, by growing at least one buffer layer in the middle instead of growing the GaN layer directly on the Si substrate, it is possible to improve the crystallinity of the GaN layer and improve the leakage current characteristic and the breakdown voltage characteristic have.

Hereinafter, a structure of a semiconductor device and a manufacturing method thereof according to an embodiment disclosed herein will be described with reference to FIGS. 2 to 4. FIG.

The work disclosed herein In the embodiment  Description of the semiconductor device according to

A semiconductor device according to an embodiment disclosed herein includes a GaN channel layer, an AlGaN barrier layer formed on the GaN channel layer, a first gate insulating layer formed in a gate region defined in a partial region on the AlGaN barrier layer, A p-type gate layer doped with a p-type dopant formed on the first gate insulating layer and made of Al _x Ga ₁ -xN (0 _{? X} ? 1), and a second gate insulating layer . &Lt; / RTI &gt;

The semiconductor device according to an embodiment may further include a gate electrode formed on the second gate insulating layer.

According to one embodiment, the p-type dopant may be at least one of Mg, C, Zn, and Fe.

Also, according to one embodiment, the concentration of the p-type dopant may be ^{1 12} / cm ³ to 1 ²¹ / cm ³ .

Also, according to one embodiment, the thickness of the p-type gate layer may be 1 nm to 1 μm.

According to an embodiment, the first gate insulating film (or the insulating layer) may be made of at least one of AlN and Si _x N _y .

Also, according to an embodiment, the thickness of the first gate insulating film (or insulating layer) may be 0.1 nm to 5 nm.

According to an embodiment, the second gate insulating film (or insulating layer) may be formed of at least one material selected from SiO ₂ , Si _x N _y , HfO ₂ , Al ₂ O ₃ , ZnO, AlN, and Ga ₂ O ₃ .

Also, according to one embodiment, the thickness of the second gate insulating film (or insulating layer) may be 1 nm to 100 nm.

In addition, the semiconductor device according to an embodiment may further include a source electrode and a drain electrode formed on a part of the AlGaN barrier layer.

Also, according to one embodiment, the thickness of the GaN channel layer may be 0.5 um to 10 um.

Also, according to one embodiment, the GaN channel layer may be doped with at least one dopant of Mg, C, and Fe.

Also, according to one embodiment, the at least one dopant concentration may be from 3e ¹⁷ / cm ³ to 1e ²⁰ / cm ³ .

Also, according to one embodiment, the thickness of the AlGaN barrier layer may be 0.1 nm to 100 nm.

In addition, according to one embodiment, the AlGaN barrier layer may include a plurality of layers made of AlGaN having different Al compositions.

According to an embodiment, the number of the plurality of AlGaN layers having different compositions of Al may be 2 to 5.

Also, according to one embodiment, the Al composition of the AlGaN barrier layer may be continuously decreased with a specific slope in the stacking direction.

Further, according to an embodiment, the Al composition of the AlGaN barrier layer is discontinuously reduced in the stacking direction.

Also, according to one embodiment, the GaN channel layer may be formed on the buffer layer.

Also, according to one embodiment, the thickness of the buffer layer may be 1 nm to 7 μm.

According to an embodiment, the buffer layer may include at least one of an AlN buffer layer made of AlN and an AlGaN buffer layer made of AlGaN.

Also, according to one embodiment, the GaN channel layer may be formed on a substrate.

According to an embodiment, the substrate may be made of at least one of Si, SiC, Sapphire, and GaN.

According to an embodiment, the first gate insulating film (or the insulating layer) and the second gate insulating film (or the insulating layer) may include at least one of metal organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD) It can be formed on grounds.

2 is an exemplary view showing a structure of a semiconductor device according to an embodiment disclosed herein.

2, a semiconductor device 100 according to one embodiment disclosed herein includes a GaN channel layer 110, an AlGaN barrier layer 120, a p-type gate layer 130, a first gate insulating layer 140 And a second gate insulating layer 150.

In addition, the semiconductor device 100 may further include an oxide layer (not shown) for preventing surface leakage current.

The semiconductor device 100 may further include a gate electrode 160 formed on the second gate insulating layer 150.

The semiconductor device 100 may further include a source electrode 170 and a drain electrode 180 formed on a part of the AlGaN barrier layer 120.

The semiconductor device 100 according to an embodiment disclosed herein may switch a 2DEG (CDEG) current flowing from the drain electrode 180 to the source electrode 170 through a schottky gate electrode 160 ) Operation can be performed.

The GaN channel layer 110 may have a thickness of 0.5 to 100 um. Particularly (or preferably), the GaN channel layer 110 may have a thickness of 0.6 um to 10 um.

The GaN channel layer 110 may be formed by various methods (or methods).

For example, the GaN channel layer 110 may be formed by selectively growing a nitride semiconductor crystal, and may be formed by an organic metal vapor deposition (MOCVD) method, a molecular beam epitaxial growth (MBE) method, (HVPE). &Lt; / RTI &gt; However, considering the crystallinity of the GaN channel layer 110, MOCVD may be used for device fabrication.

For example, when the GaN channel layer 110 is formed by the MOCVD method, the GaN channel layer 110 is formed through epitaxial growth by synthesizing NH 3, which is a raw material of TMGa, N, .

According to one embodiment, the GaN channel layer 110 may be doped with at least one dopant of C, Fe, Mg, and Mn dopants.

In other words, the semiconductor device 100 includes a GaN channel layer 110 for forming a semi-insulating characteristic of a GaN channel formed by implanting at least one dopant of C, Fe, Mg, and Mn dopants on the GaN channel layer 110 - a resistive GaN layer (not shown).

Here, the concentration of the at least one dopant may be 1e ¹⁶ / cm ³ to 5e ²⁰ / cm ³ . In particular, the concentration of the at least one dopant may be 3e ¹⁷ / cm ³ to 1e ²⁰ / cm ³ .

Particularly, when the at least one dopant is C, doping of 1e ¹⁸ / cm ³ or more may be common.

In addition, as shown, the current end of the GaN channel layer 110 to form a flow channel layer can be minimized in the doping of impurities, in particular C concentration must be doped to less than 1e ¹⁷ / cm ³ described above can do.

According to one embodiment, the GaN layer 110 may include a plurality of layers of GaN grown at different temperatures.

Also, according to one embodiment, the number of the plurality of layers made of GaN grown at different temperatures may be 2 to 5.

The AlGaN barrier layer 120 may be formed on the GaN channel layer 110 to form a 2DEG on the channel layer.

That is, the AlGaN barrier layer 120 may be formed on the GaN channel layer 110, and the AlGaN barrier layer 120 may serve as an active layer.

In addition, the thickness of the AlGaN barrier layer 120 may be in the range of 0.1 nm to 100 nm. In particular (or preferably), the thickness of the AlGaN barrier layer 140 may range from 1 nm to 20 nm.

The AlGaN barrier layer 120 may have a variety of compositions. For example, the composition of Al in the AlGaN barrier layer 120 may be 1% to 100%. It is apparent to those skilled in the art that the AlGaN barrier layer 120 may be formed at various composition ratios.

The AlGaN barrier layer 120 may include a plurality of layers made of AlGaN having different Al compositions.

Here, the number of the plurality of layers made of AlGaN having different compositions of Al may be 2 to 5.

In addition, the Al composition of the AlGaN barrier layer 120 may be continuously decreased with a specific slope in the stacking direction.

In addition, the Al composition of the AlGaN barrier layer 120 may be discontinuously decreased in the stacking direction.

The AlGaN barrier layer 120 may be formed in a variety of ways (or methods).

For example, the AlGaN barrier layer 120 may be formed by selectively growing a nitride semiconductor crystal. The AlGaN barrier layer 120 may be formed by a metal organic vapor phase epitaxy (MOCVD), a molecular beam epitaxial growth (MBE) (HVPE). &Lt; / RTI &gt; However, considering the crystallinity of the AlGaN barrier layer 120, MOCVD may be used for device fabrication.

The semiconductor device 100 may include a first gate insulating layer 140 (or an insulating layer) which is a first buffer layer for reducing etch damage.

The first gate insulating layer 140 may be formed in a gate region defined in a portion of the AlGaN barrier layer 120.

The partial region may be a region defined as a gate region where the p-type gate layer 130 is formed.

The first gate insulating layer 140 may be grown by MOCVD and may be a thin insulating layer (or insulating layer) having a thickness of 0.1 nm to 5 nm.

The first gate insulating layer 140 may be made of at least one of AlN and Si _x N _y .

After the first gate insulating layer 140 is formed, a p-type gate layer 130 may be grown on the first gate insulating layer 140 for a normally-off operation.

As described above for the p-type gate layer 130, a gate recess, a fluorine treatment (or plasma treatment), a p-type gate method (or a gate recess method) is used for a method of manufacturing a normally- p-type gate method).

The gate recess method may be a method of cutting a part of the 2DEG through etching and introducing a Schottky gate to maintain the off characteristic. This can be a drawback to 2DEG loss.

The fluorine treatement method may be a method of depleting electrons by plasma treatment of F ions to maintain off characteristics. This may have drawbacks such as unwanted plasma damage.

Finally, the method of adopting the p-type gate layer may be a method of maintaining the off-off characteristic by using a depletion of the pn junction.

The p-type gate method is a technique capable of performing normally off-switching while maintaining excellent current characteristics of a nitride semiconductor device.

When the p-GaN layer is formed under the gate electrode, the p-GaN layer and the underlying AlGaN / GaN structure form a p-n junction, and a depletion phenomenon may occur.

Therefore, the 2DEG layer disappears at the bottom of the gate, so that when the gate is grounded, the source and the drain can not flow current.

However, when a threshold voltage having a (+) sign is applied to the gate, the lower 2DEG layer of the gate disappears and the current flows and the switching operation can be performed.

 That is, when the p-GaN gate is used, the nitride semiconductor device can be driven to be normally off-driven and high current characteristics can be maintained.

Such a p-GaN gate technique (the technique using the p-GaN gate layer or the p-type gate layer) can be a technique for growing p-type doped GaN on the AlGaN / GaN heterojunction structure and forming a gate electrode therefor. have.

The p-GaN layer may serve to deplete the two-dimensional free electron gas (2DEG) present at the interface between AlGaN and GaN.

The p-type gate layer 130 may be a GaN-based (or nitride-based) material doped with a p-type dopant and may be used as a gate layer. Therefore, it may be referred to as a p-GaN gate layer.

That is, the p-type gate layer 130 may be a GaN or AlGaN layer doped with a p-type dopant. Therefore, it may be a layer doped with a p-type dopant and composed of Al _x Ga _{1 - x} N (0 _{? X} ? 1). In particular, the composition x of the p-type gate layer 130 may be 0 to 0.5.

A semiconductor device (e.g., a HEMT or an HFET device) having the p-type gate layer may have the advantage that the normally-off characteristic can be maintained without reducing the 2DEG density.

The thickness of the p-GaN gate layer (or the p-type gate layer 130) may be 1 nm to 1 um. In particular, the p-type gate layer 130 may have a thickness of 1 nm to 200 nm.

The p-type dopant doped in the p-type gate layer 130 may be at least one of Mg, C, Zn, and Fe.

For example, the impurity concentration of the p-type dopant doped in the p-type gate layer 130 may be 1e ¹² / cm ³ to 1e ²¹ / cm ³ . In particular, the concentration of the impurity may be 3e ¹⁷ / cm ³ to 1e ²⁰ / cm ³ .

The second gate insulating layer 150 may be formed on (or on) the p-type gate layer 130.

The second gate insulating layer may be made of at least one of (150), SiO ₂ , Si _x N _y , HfO ₂ , Al ₂ O ₃ , ZnO, AlN, and Ga ₂ O ₃ .

In addition, the thickness of the second gate insulating layer 150 may be 1 nm to 100 nm.

The semiconductor device 100 may further include a gate electrode 160 (or a p-GaN electrode) formed on the second gate insulating layer 150.

The semiconductor device 100 may further include a drain electrode 180 and a source electrode 170 formed on the AlGaN barrier layer 120.

The source electrode 170 and the drain electrode 180 may be formed on a part of the AlGaN barrier layer 120.

3 is an exemplary view showing a configuration of a semiconductor device according to another embodiment disclosed herein.

3, a semiconductor device 100 according to another embodiment disclosed herein further includes a cap layer 190 of GaN (or nitride, nitride based) formed on the AlGaN barrier layer 120 can do.

The GaN cap layer 190 is formed on the AlGaN barrier layer 120 and may be formed by thinly growing a nitride based material such as GaN or AlGaN.

According to one embodiment, the thickness of the GaN cap layer 190 may be in the range of 0.1 nm to 100 nm, particularly 2 nm to 10 nm. The GaN cap layer 190 may prevent surface leakage current.

In this case, the first gate insulating layer 140 may be formed on the GaN cap layer 190.

The source electrode 170 and the drain electrode 180 may be formed on the GaN cap layer 190.

A 2DEG (CDEG) current flowing from the drain electrode 180 to the source electrode 170 may be generated through control of the schottky gate electrode 160, as described above.

According to one embodiment, the semiconductor device 100 is formed on a part of the AlGaN barrier layer 120, the source electrode 170, the drain electrode 180, and the gate electrode 160 And an oxide layer (not shown).

According to one embodiment, the GaN channel layer 110 may be formed on a buffer layer (not shown).

In addition, the buffer layer may be formed on a substrate (not shown).

In addition, according to one embodiment, the GaN channel layer 110 may be formed on the substrate in the absence of the buffer layer.

Also, according to one embodiment, the substrate may be n-type, p-type, or various types of materials. For example, the substrate may be at least one of an insulating substrate, a sapphire substrate, a GaN substrate, a SiC substrate, an AlN substrate, and a Si substrate. It will be apparent to those skilled in the art that various types of substrates may be applied to the semiconductor devices disclosed herein.

Further, the substrate can be removed after fabrication of the semiconductor device 100. [ Thus, the final structure of the semiconductor device may be a structure without the substrate.

The buffer layer is a seed layer for growing GaN on the substrate and may be referred to as a nucleation layer.

Here, the thickness of the buffer layer may be 1 nm to 7 μm.

According to one embodiment, the buffer layer may include at least one of an AlN buffer layer made of AlN and an AlGaN buffer layer made of AlGaN.

The AlN buffer layer may include a plurality of layers made of AlN grown at different temperatures.

In this case, the number of the plurality of layers made of AlN grown at different temperatures may be 2 to 5.

That is, the AlN buffer layer can be grown under various conditions. For example, the AlN buffer layer may include a first AlN layer grown at a low temperature and a second AlN layer grown at a high temperature formed on the first AlN layer.

The AlGaN buffer layer may include a plurality of layers made of AlGaN having different Al compositions.

Here, the number of the plurality of layers made of AlGaN having different compositions of Al may be 2 to 5.

The Al composition of at least one of the AlN buffer layer and the AlGaN buffer layer may vary in various directions depending on the stacking direction.

For example, the Al composition of at least one of the AlN buffer layer and the AlGaN buffer layer may be continuously decreased with a specific slope in the stacking direction.

Also, for example, the Al composition of at least one of the AlN buffer layer and the AlGaN buffer layer may be discontinuously reduced (for example, a discontinuous decrease in the stacking direction) in the stacking direction.

The oxide layer may serve to reduce surface leakage current.

The oxide layer may be formed between the source electrode 170 or the drain electrode 180 and the gate electrode 160.

The oxide layer may have a variety of materials or composition ratios. For example, the oxide layer may be formed of at least one of SiO ₂ , Si _x N _y (for example, Si ₃ N ₄ ), HfO ₂ , Al ₂ O ₃ , ZnO, and Ga ₂ O ₃ .

According to one embodiment, the thickness of the oxide layer is in the range of 2 nm to 200 nm, and in particular (or preferably) the thickness of the oxide layer is in the range of 2 nm to 100 nm.

For example, the oxide layer may be formed by various methods such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), helium vapor deposition (HVPE), and PECVD Plasma-enhanced chemical vapor deposition (CVD), sputtering, and atomic layer deposition (ALD).

The first gate insulating layer 140 and the second gate insulating layer 150 may be formed based on at least one of metal organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD).

The work disclosed herein In the embodiment  Description of a method of manufacturing a semiconductor device according to

A method of manufacturing a semiconductor device according to an embodiment disclosed herein includes forming an AlGaN barrier layer on a GaN channel layer, forming a first gate insulating layer in a gate region defined in a portion of the AlGaN barrier layer Forming a p-type gate layer doped with a p-type dopant on the first gate insulating layer and made of Al _x Ga ₁ -xN (0 _{? X} ? 1), and forming a p- 2 gate insulating layer.

The method of manufacturing a semiconductor device according to an embodiment may further include forming a gate electrode on the second gate insulating layer.

According to an embodiment, the p-type dopant may be at least one of Mg, C, Zn, and Fe.

Also, according to one embodiment, the concentration of the p-type dopant may be ^{1 12} / cm ³ to 1 ²¹ / cm ³ .

Also, according to one embodiment, the thickness of the p-type gate layer may be 1 nm to 1 μm.

According to an embodiment, the first gate insulating layer may be made of at least one of AlN and Si _x N _y .

Also, according to one embodiment, the thickness of the first gate insulating layer may be 0.1 nm to 5 nm.

According to an embodiment, the second gate insulating layer may be made of at least one of SiO ₂ , Si _x N _y , HfO ₂ , Al ₂ O ₃ , ZnO, AlN, and Ga ₂ O ₃ .

According to an embodiment, the thickness of the second gate insulating layer may be 1 nm to 100 nm.

In addition, the method of fabricating a semiconductor device according to an embodiment may further include forming a source electrode and a drain electrode on a part of the AlGaN barrier layer.

According to an embodiment, the first gate insulating layer and the second gate insulating layer may be formed based on at least one of metal organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD).

According to one embodiment, at least one of the GaN channel layer, the AlGaN barrier layer, and the p-type gate layer may be formed by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), helium vapor deposition (HVPE), Plasma-enhanced chemical vapor deposition (PECVD), sputtering, and atomic layer deposition (ALD).

4 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment disclosed herein.

Referring to FIG. 4, a method of manufacturing a semiconductor device according to an embodiment disclosed herein may include the following steps.

First, an AlGaN barrier layer may be formed on the GaN channel layer (S110).

Next, a first gate insulating layer may be formed in a gate region defined in a part of the AlGaN barrier layer (S120).

Next, a p-type gate layer doped with a p-type dopant and made of Al _x Ga _{1 -x} N (0? X? 1) may be formed on the first gate insulating layer (S130).

Next, a second gate insulating layer may be formed on the p-type gate layer (S140).

According to an embodiment, the method may further include forming a gate electrode on the second gate insulating layer.

According to an embodiment, the method may further include forming a GaN cap layer between the AlGaN barrier layer and the first gate insulating layer.

Also, according to an embodiment, it is possible to further include forming a source electrode and a drain electrode on a part of the AlGaN barrier layer.

5A to 5G are views illustrating an example of a method of manufacturing a semiconductor device according to an embodiment disclosed herein.

5A through 5G, a method of manufacturing a semiconductor device according to an embodiment disclosed herein includes sequentially forming on a substrate (not shown) a GaN channel layer 110, an AlGaN barrier layer 120, Layer 140, the p-type gate layer 130 and the second gate insulating layer 150. [0064]

As described above, the substrate can be removed after fabrication of the semiconductor device 100. Thus, the final structure of the semiconductor device may be a structure without the substrate.

The method of manufacturing a semiconductor device according to an embodiment disclosed herein may further include forming a gate electrode 160 on the second gate insulating layer 150. [

The method of manufacturing a semiconductor device according to an embodiment disclosed herein may further include forming a source electrode 170 and a drain electrode 180 on a part of the AlGaN barrier layer 120 .

A method of manufacturing a semiconductor device according to an embodiment disclosed herein may include forming a source electrode 170 and a drain electrode 170 on a part of the GaN cap layer 190, 180 may be formed.

In addition, the method of manufacturing a semiconductor device according to an embodiment disclosed herein may further include forming the AlGaN barrier layer 120 (or the GaN cap layer 190), the source electrode 170, the drain electrode 180, (Not shown) may be formed on a part of the oxide semiconductor layer 160.

5A to 5G, a GaN channel layer 110 can be formed (or grown) with an MOCVD thin film growth apparatus on a substrate (not shown) (FIG. 5A ).

As described above, the substrate may be n-type or p-type, and the substrate may be Si, SiC, sapphire, GaN (e.g., Freestanding GaN) substrate, AlN substrate, or the like .

GaN constituting the GaN channel layer 110 may be formed by an organic metal vapor phase growth method called MOCVD.

In this case, the GaN channel layer 110 can be formed by epitaxial growth by synthesizing NH ₃ , which is a raw material of Ga, as a raw material of Ga, NH ₃ in a reactor at a high temperature.

The GaN channel layer 110 may have a thickness of 0.5 to 10 um. Particularly (or preferably), the GaN channel layer 110 may have a thickness of 0.6 um to 3 um.

Here, the GaN channel layer 110 may be doped with Fe, Mg or Carbon to form semi-insulating characteristics. The GaN channel layer 110 may also be grown to one temperature or to two to five continuous or discontinuous temperatures.

Next, after the GaN channel layer 110 is grown, an AlGaN barrier layer 120, which is an active layer for forming a hetero-junction 2DEG layer, can be grown (FIG. 5B).

The thickness of the AlGaN barrier layer 120 may range from 0.1 nm to 100 nm. In particular (or preferably), the thickness of the AlGaN barrier layer 140 may range from 1 nm to 20 nm.

The AlGaN barrier layer 120 may have a variety of compositions. For example, the composition of Al in the AlGaN barrier layer 120 may be 1% to 100%. It is apparent to those skilled in the art that the AlGaN barrier layer 120 may be formed at various composition ratios.

The AlGaN barrier layer 120 may include a plurality of layers made of AlGaN having different Al compositions.

Here, the number of the plurality of layers made of AlGaN having different compositions of Al may be 2 to 5.

In addition, the Al composition of the AlGaN barrier layer 120 may be continuously decreased with a specific slope in the stacking direction.

In addition, the Al composition of the AlGaN barrier layer 120 may be discontinuously decreased in the stacking direction.

The AlGaN barrier layer 120 may be formed in a variety of ways (or methods).

For example, the AlGaN barrier layer 120 may be formed by selectively growing a nitride semiconductor crystal. The AlGaN barrier layer 120 may be formed by a metal organic vapor phase epitaxy (MOCVD), a molecular beam epitaxial growth (MBE) (HVPE). &Lt; / RTI &gt; However, considering the crystallinity of the AlGaN barrier layer 120, MOCVD may be used for device fabrication.

The AlGaN barrier layer 120 forms a 2DEG due to a piezo-polarization due to a difference in lattice constant with respect to the GaN channel layer 110. The 2DEG density can be determined according to the Al composition and thickness.

Next, a nitride based material such as GaN or AlGaN may be grown on the AlGaN barrier layer 120 to form a GaN cap layer 190 (FIG. 5C).

According to one embodiment, the thickness of the GaN cap layer 190 may be in the range of 0.1 nm to 100 nm, particularly 2 nm to 10 nm. The GaN cap layer 190 may prevent surface leakage current.

Next, after the GaN cap layer 190 is grown, a first gate insulating layer 140 may be formed (FIG. 6D).

The first gate insulating layer 140 may serve as a first buffer layer buffer layer for reducing etch damage.

The first gate insulating layer 140 may be formed in the gate region defined in the AlGaN barrier layer 120 or a portion of the GaN cap layer 190.

The partial region may be a region defined as a gate region where the p-type gate layer 130 is formed.

The first gate insulating layer 140 may be grown by MOCVD and may be a thin insulating layer (or insulating layer) having a thickness of 0.1 nm to 5 nm.

The first gate insulating layer 140 may be made of at least one of AlN and Si _x N _y .

After the first gate insulating layer 140 is formed, a p-type gate layer 130 for a normally-off operation may be grown on the first gate insulating layer 140 ).

The p-type gate layer 130 may be a GaN-based (or nitride-based) material doped with a p-type dopant and may be used as a gate layer. Therefore, it may be referred to as a p-GaN gate layer.

The p-type gate layer 130 may be a GaN or AlGaN layer doped with a p-type dopant. Therefore, it may be a layer doped with a p-type dopant and composed of Al _x Ga _{1 - x} N (0 _{? X} ? 1). In particular, the composition x of the p-type gate layer 130 may be 0 to 0.5.

A semiconductor device (e.g., a HEMT or an HFET device) having the p-type gate layer may have the advantage that the normally-off characteristic can be maintained without reducing the 2DEG density.

The thickness of the p-GaN gate layer (or the p-type gate layer 130) may be 1 nm to 1 um. In particular, the p-type gate layer 130 may have a thickness of 1 nm to 200 nm.

The p-type dopant doped in the p-type gate layer 130 may be at least one of Mg, C, Zn, and Fe.

For example, the impurity concentration of the p-type dopant doped in the p-type gate layer 130 may be 1e ¹² / cm ³ to 1e ²¹ / cm ³ . In particular, the concentration of the impurity may be 3e ¹⁷ / cm ³ to 1e ²⁰ / cm ³ .

Next, a second gate insulating layer 150 may be formed on the p-type gate layer 130 by MOCVD or ALD (FIG. 5F).

The second gate insulating layer 150 may be formed on (or on) the p-type gate layer 130.

The second gate insulating layer may be made of at least one of (150), SiO ₂ , Si _x N _y , HfO ₂ , Al ₂ O ₃ , ZnO, AlN, and Ga ₂ O ₃ .

In addition, the thickness of the second gate insulating layer 150 may be 1 nm to 100 nm.

Next, an etching or etching process may be performed to deposit the gate electrode 160, the source electrode 170, and the drain electrode 180.

According to one embodiment, a gate region may be defined in a portion of the AlGaN barrier layer 120 or the GaN cap layer 190 and the remaining portion may be formed in the first gate insulation layer 130 using a gas based on Cl ₂ and BCl _3. Etching can proceed to the layer 140 (see FIG. 6G).

Next, a source electrode 170 and a drain electrode 180 are formed on the AlGaN barrier layer 120, or a source electrode 170 and a drain electrode 180 are formed on the GaN cap layer 150 (Fig. 6G).

The source electrode 170 and the drain electrode 180 may form an ohmic contact. For example, a Ti / Al-based structure may be used. Further, heat treatment can be performed thereafter.

In addition, the gate electrode 160 may be formed on the second gate insulating layer 150 (FIG. 6G). That is, a gate electrode is formed on the remaining gate region after the formation of the ohmic region, and the gate electrode may be formed of a metal having a high work function such as W, TiN, or a metal such as Ni.

The source electrode 170, the drain electrode 180, and the gate electrode 160 may be deposited using an E-beam as an ohmic electrode.

In addition, in addition, the AlGaN barrier layer 120 (when the GaN cap layer 150 is deposited, the GaN cap layer 150), the source electrode 170, the drain electrode 180, An oxide film layer (not shown) may be formed on a part of the gate electrode 160.

At least one of the GaN channel layer 110, the AlGaN barrier layer 120, the p-type gate layer 130, and the GaN cap layer 190 may be formed by metal organic chemical vapor deposition (MOCVD) , Molecular beam epitaxy (MBE), helix vapor deposition (HVPE), plasma enhanced chemical vapor deposition (PECVD), sputtering, and atomic layer deposition (ALD) .

According to one embodiment, the first gate insulating layer 140 and the second gate insulating layer 150 are formed on at least one of metal organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD) May be formed.

In summary, the nitride semiconductor has a high critical electric field and a high saturation electron mobility, so that a semiconductor device fabricated using the nitride semiconductor is expected to exhibit a high breakdown voltage and a large current characteristic. A representative example is an HFET device fabricated on the basis of a heterojunction structure of AlGaN / GaN.

  HFET devices have excellent voltage and current characteristics, and many attempts have been made to use them as high-output power devices. However, HFET devices have a drawback in that they have a normally-on mode, unlike conventional devices such as MOSFETs and IGBTs. In order to increase the threshold voltage, a plasma treatment, a gate recess and a p-type GaN epitaxial layer (or a p-type GaN-based epitaxial layer as described above) Layer) growth and so on.

The p-type GaN epitaxial layer growth method (or the p-type gate structure method), which is a method applicable in the wafer growing step, is a method in which a p-type GaN-based layer (or a p-type gate layer structure) is formed on AlGaN (or AlGaN barrier layer) Layer is deposited on the wafer.

A similar p-n junction can be formed by etching the rest of the p-type GaN layer except for the gate region. The threshold voltage can be increased by lowering the concentration of 2DEG (2-Dimensional Electron Gas) through the p-n junction.

However, in the case of the p-type gate structure, it is advantageous in that the normally-off state can be maintained without decreasing the 2DEG. However, the epitaxial layer growth technique needs to be advanced and the pn junction is controlled by the leakage current control and the p- Control of etch damage during etch may be difficult.

That is, the p-type gate HFET device can maintain the normally-off characteristic without decreasing the 2DEG density. However, since the depletion of the pn junction maintains the normally-off characteristic, the pn-junction barrier A forward current may be generated.

Increasing the gate current means that unwanted losses occur, which can reduce the efficiency of the device.

The technique disclosed in this specification relates to a nitride semiconductor power device using GaN and a method of manufacturing the same.

Specifically, the techniques disclosed herein utilize an epitaxial structure of p-GaN (or p-type gate layer) / AlGaN (or AlGaN barrier layer) / GaN (or GaN channel layer) (Or an insulating layer) between a metal gate and a p-GaN gate (or a p-type gate layer) to fabricate a device with a pn junction and reduce a leakage current caused by a pn junction, .

The insulating layer (or insulating layer) may be formed using MOCVD or ALD to maintain high purity characteristics.

That is, the semiconductor device according to one embodiment disclosed herein has a structure in which an insulating film (or an insulating layer) for reducing etch damage is formed between a p-type gate layer and an AlGaN barrier layer by MOCVD.

In the case of the device fabricated by the above method, leakage current can be minimized and high reliability can be secured due to a high purity insulating film (or insulating layer) / protective film (or protective layer).

This is especially advantageous over conventional methods in that the stability of the device to be operated at high voltage is enhanced while preventing the number of carrier concentration or electron mobility of the 2DEG from decreasing.

According to one embodiment disclosed herein, a nitride semiconductor device and a method for fabricating the same are disclosed. In the nitride semiconductor device and method of manufacturing the same, an insulating film (or an insulating layer) is formed on upper and lower portions of a p-type gate layer made of GaN or AlGaN doped with a p- A nitride semiconductor device capable of reducing gate current and etching damage while maintaining basic characteristics of a device, and a method for manufacturing the same.

In particular, according to the semiconductor device disclosed in this specification, by providing a nitride-based semiconductor device having a structure in which an insulating film (or an insulating layer) is included in the upper and lower layers of a p-type gate layer, There is an advantage that it is possible to prevent the decrease of the gate current and to reduce the etching damage which occurs when the etching process for the p-type gate layer proceeds while making the most of advantages of the junction semiconductor device (for example, HFET).

Further, by forming the insulating film (or insulating layer) using MOCVD or ALD, there is an advantage that high-quality insulator and device characteristics are improved.

The scope of the present invention is not limited to the embodiments disclosed herein, and the present invention can be modified, changed, or improved in various forms within the scope of the present invention and the claims.

100: Semiconductor device 110: GaN channel layer
120: AlGaN barrier layer 130: p-type gate layer
140: first gate insulating layer 150: second gate insulating layer

Claims (36)

A GaN channel layer;
An AlGaN barrier layer formed on the GaN channel layer;
A first gate insulating layer formed in a gate region defined in a partial region on the AlGaN barrier layer;
A p-type gate layer doped with a p-type dopant formed on the first gate insulating layer and made of Al _x Ga _{1 - x} N (0 _{? X} ? 1); And
And a second gate insulating layer formed on the p-type gate layer. The method according to claim 1,
And a gate electrode formed on the second gate insulating layer. The method of claim 1, wherein the p-
Mg, C, Zn, and Fe. The method of claim 1, wherein the concentration of the p-
1e ¹² / cm ³ to 1e ²¹ / cm ³ . The semiconductor device according to claim 1, wherein the thickness of the p-
1 nm to 1 um. The semiconductor device according to claim 1, wherein the first gate insulating layer
AlN, and Si _x N _y . The semiconductor device according to claim 1, wherein the thickness of the first gate insulating layer
0.1 nm to 5 nm. The semiconductor device according to claim 1, wherein the second gate insulating layer
And at least one of SiO ₂ , Si _x N _y , HfO ₂ , Al ₂ O ₃ , ZnO, AlN, and Ga ₂ O ₃ . The semiconductor device according to claim 1, wherein the thickness of the second gate insulating layer
1 nm to 100 nm. The method according to claim 1,
And a source electrode and a drain electrode formed on a part of the AlGaN barrier layer. The GaN substrate according to claim 1,
0.5um to 10um. 2. The GaN substrate according to claim 1,
Mg, &lt; / RTI &gt; C and Fe. 13. The method of claim 12, wherein the at least one dopant concentration is selected from the group consisting of:
3e ¹⁷ / cm ³ to 1e ²⁰ / cm ³ . 2. The method of claim 1, wherein the thickness of the AlGaN barrier layer
0.1 to 100 nm. 2. The method of claim 1, wherein the AlGaN barrier layer comprises:
And a plurality of layers made of AlGaN having different compositions of Al. 16. The method according to claim 15, wherein the number of the plurality of layers made of AlGaN,
2 &lt; / RTI &gt; 2. The AlGaN barrier layer according to claim 1,
And is continuously reduced with a specific inclination in the stacking direction. 2. The AlGaN barrier layer according to claim 1,
And is discontinuously reduced in the stacking direction. 2. The GaN substrate according to claim 1,
Wherein the semiconductor layer is formed on the buffer layer. The method as claimed in claim 17,
1 nm to 7 [mu] m. The method as claimed in claim 17,
An AlN buffer layer made of AlN and an AlGaN buffer layer made of AlGaN. 2. The GaN substrate according to claim 1,
And is formed on a substrate. 23. The method of claim 22,
Si, SiC, Sapphire, and GaN. The semiconductor memory device according to claim 1, wherein the first gate insulating layer and the second gate insulating layer
And at least one of metal organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD). Forming an AlGaN barrier layer on the GaN channel layer;
Forming a first gate insulating layer in a gate region defined in a portion of the AlGaN barrier layer;
Forming a p-type gate layer doped with a p-type dopant on the first gate insulating layer and made of Al _x Ga _{1 - x} N (0 _{? X} ? 1); And
And forming a second gate insulating layer on the p-type gate layer. 26. The method of claim 25,
And forming a gate electrode on the second gate insulating layer. 26. The method of claim 25, wherein the p-
Mg, C, Zn, and Fe. 26. The method of claim 25, wherein the concentration of the p-
1e ¹² / cm ³ to 1e ²¹ / cm ³ . 26. The method of claim 25, wherein the thickness of the p-
1 nm to 1 [mu] m. The semiconductor device according to claim 25, wherein the first gate insulating layer
AlN, and Si _x N _y . 26. The method according to claim 25, wherein the thickness of the first gate insulating layer
0.1 nm to 5 nm. The semiconductor device according to claim 25, wherein the second gate insulating layer
Wherein the _first electrode is made of at least one of SiO ₂ , Si _x N _y , HfO ₂ , Al ₂ O ₃ , ZnO, AlN and Ga ₂ O ₃ . 26. The method according to claim 25, wherein the thickness of the second gate insulating layer
1 nm to 100 nm. 26. The method of claim 25,
And forming a source electrode and a drain electrode on a partial region of the AlGaN barrier layer. The semiconductor device according to claim 25, wherein the first gate insulating layer and the second gate insulating layer
(MOCVD), and atomic layer deposition (ALD). 26. The method of claim 25, wherein at least one of the GaN channel layer, the AlGaN barrier layer, and the p-
At least one of metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), helium vapor deposition (HVPE), plasma enhanced chemical vapor deposition (PECVD), sputtering, and atomic layer deposition Wherein the semiconductor device is formed on the basis of a predetermined pattern.

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