JP5415668B2 - Semiconductor element - Google Patents

Description

  The present invention relates to a junction gate field effect transistor element formed using a group III nitride.

  Switching elements (transistors, thyristors, etc.) and rectifier elements (diodes) using semiconductors are widely used as elements for power inverters or converter circuits. At present, there is a demand for semiconductor devices for such power applications (so-called power devices) that are smaller and have lower loss in order to meet future high power demand. Conventionally, silicon has been widely used as a semiconductor material. However, in view of such a situation, development of a wide band gap semiconductor material having a high breakdown electric field is progressing as a next-generation semiconductor material. Since so-called wide band gap semiconductor materials such as SiC, diamond, and group III nitride semiconductors are expected to have low on-resistance and high breakdown voltage due to their physical properties, they should be used to form semiconductor elements for power applications. It is expected that the power control device will greatly reduce the size and loss.

  As one type of such a semiconductor device, a field effect transistor device (FET) using a group III nitride such as GaN as a semiconductor layer and a high electron mobility transistor device (HEMT) which is one type thereof are already known (for example, Patent Document 1 to Non-Patent Document 3). Non-Patent Document 1 to Non-Patent Document 3 disclose Schottky FETs and HEMTs formed using Group III nitrides. Among these, Non-Patent Document 3 also discloses a normally-off HEMT.

"Characteristics of a GaN Metal Semiconductor Field-Effect Transistor Grown on a Sappire Substrate by Metalorganic Chemical Vapor Deposition" T. Egawa, K. Nakamura, H. Ishikawa, T. Jimbo, and M. Umeno, Jpn. J. Appl. Phys Vol.38 (1999) pp.2630-2633. "Gallium Nitride Based High Power Heterojunction Field Effect Transistors: Process Development and Present Status at UCSB" S.Keller, YFWu, G.Parish, N.Ziang, JJXu, BPKeller, S.DenBaars, and UKMishra, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.48, NO.3, MARCH 2001. "Non-Recessed-Gate Enhancement-Mode AlGaN / GaN High Electron Mobility Transistors with High RF Performance" A. Endoh, Y. Yamashita, J. Ikeda, M. Higashiwaki, K. Hikosaka, T. Matsui, S. Hiyamizu, and T. Mimura, Jpn. J. Appl. Phys. Vol. 43, NO4B, 2004, pp.2255-2258.

  In a conventional Schottky FET formed using a group III nitride, a so-called leak current flows when a reverse gate voltage is applied. The gate leakage current is about 1 μA / mm in terms of current density (leakage current per unit gate width), but when the gate width is increased as in the case where the electrode structure is comb-like, The loss is not negligible. From the viewpoint of power saving, there is a demand for a low-loss FET in which gate leakage current is further suppressed.

  In addition, when used as a power device, in view of safety and downsizing of the entire device, the FET does not flow main current unless a gate voltage is applied, that is, it is a normally-off type in a pinch-off state. desirable. In order to obtain a normally-off type conventional Schottky contact FET, the pinch-off state can be realized by reducing the thickness of the n-type conductive layer, or the carrier concentration in the n-type conductive layer It was a common aspect to reduce the size. However, since these modes narrow the conduction path or directly reduce the number of carriers, the viewpoint of obtaining a good on-characteristic when applying a forward gate voltage, more specifically, a large output current is obtained. Is not preferred.

  This invention is made | formed in view of the said subject, and it aims at providing the field effect transistor element excellent in the characteristic comprised using group III nitride.

In order to solve the above-mentioned problems, the inventions of claim 1 are each expressed by a composition formula of Al _1-xy Ga _x In _y N (x ≧ 0, y ≧ 0, 0 ≦ x + y ≦ 1) III First semiconductor layer formed by laminating a non-conductive first nitride layer composed of a group nitride and a second nitride layer which is an n-type conductive region in this order And a gate portion formed by bonding to the first semiconductor layer, and the second nitride layer is formed with a dopant concentration of 2 × 10 ¹⁷ / cm ³ and a thickness of 65 nm or less, A second semiconductor layer formed on the first semiconductor layer by using a group IV semiconductor material so as to have a p-type conductivity; and an ohmic contact with the second semiconductor layer. a gate metal electrode formed by formed by, consists, acceptor of said second semiconductor layer Concentration, and a 1 × 10 20 ^/ cm ³ or more at a portion to be joined to at least said first semiconductor layer, the n-type conductive region of the junction gate type field effect transistor structure that the channel layer is formed It is characterized by that.

Further, the invention of claim 2 is a semiconductor element, and each is expressed by a composition formula of Al _1-xy Ga _x In _y N (x ≧ 0, y ≧ 0, 0 ≦ x + y ≦ 1). It is formed by laminating first and second nitride layers composed of group III nitride, and is generated two-dimensionally in the vicinity of the laminating interface between the first and second nitride layers. a first semiconductor layer electron layer that act as a conductive region of substantially n-type, and a gate portion formed by bonding the first semiconductor layer, the second nitride layer is less 18nm A second semiconductor layer formed to have a p-type conductivity using a group IV semiconductor material on the first semiconductor layer; a gate metal electrode 2 semiconductor layer in contact ohmic made is formed, it consists of, the second semiconductor Acceptor concentration is at 1 × 10 20 ^/ cm ³ or more at a portion to be joined to at least said first semiconductor layer, the junction gate type field effect transistor structure of the n-type conductive region of the channel layer is formed It is characterized by.

The invention according to claim 3 is the semiconductor element according to claim 1 or 2 , wherein at least a portion of the _first semiconductor layer bonded to the second semiconductor layer is Al _1-x. It is characterized by using a group III nitride expressed by a composition formula Ga _x N (0 ≦ x ≦ 1).

The invention of claim 4 is the semiconductor device according to claim 2, in adjacent portions of at least the first and second nitride layers, III group constituting the second nitride layer The forbidden band width of the group III nitride constituting the first nitride layer is narrower than the forbidden band width of nitride.

The invention according to claim 5 is the semiconductor element according to claim 4 , wherein the second nitride layer is expressed by a composition formula of Al _1-x Ga _x N (0 ≦ x ≦ 1). It is composed of a group III nitride.

The invention according to claim 6 is the semiconductor element according to claim 5 , wherein the second nitride layer is formed using AlN at least in a portion adjacent to the first nitride layer. It is characterized by.

The invention according to claim 7 is the semiconductor element according to any one of claims 4 to 6 , wherein the first nitride layer is at least in a portion adjacent to the second nitride layer. Is composed of a group III nitride expressed by a composition formula Ga _{1 -w} In _w N (0 ≦ w ≦ 1).

The invention according to claim 8 is the semiconductor element according to claim 7 , wherein the first nitride layer is formed using GaN at least in a portion not adjacent to the second nitride layer. It is characterized by.

A ninth aspect of the present invention is the semiconductor element according to the eighth aspect , wherein the first nitride layer is made of GaN.

The invention of claim 10 is the semiconductor device according to any one of claims 4 to 9 , wherein each of the first and second nitride layers has a wurtzite structure. It is characterized in that it is formed with a (0001) plane as a main surface using nitride.

The invention according to claim 11 is the semiconductor element according to any one of claims 1 to 10 , wherein the hole concentration of the second semiconductor layer is at least bonded to the first semiconductor layer. Is 1 × 10 ¹⁹ / cm ³ or more.

The invention according to claim 12 is the semiconductor element according to any one of claims 1 to 11 , wherein the group IV semiconductor material is Si ₁ at least in a portion joined to the first semiconductor layer. _-Z Ge _z (0 ≦ z ≦ 1).

The invention according to claim 13 is the semiconductor element according to claim 12 , characterized in that the predetermined semiconductor material is Si at least in a portion joined to the first semiconductor layer. .

According to the first to thirteenth inventions, a junction gate type structure having a PN junction between the first semiconductor layer and the second semiconductor layer constituting the gate portion in the semiconductor element is realized. In addition, since the second semiconductor layer is formed of a group IV semiconductor material, a state in which the hole concentration inherent in the second semiconductor layer is high and the electron density is extremely low is realized. Thereby, the reverse gate leakage current based on the tunnel of electrons from the gate electrode side to the conductive layer side, which occurs in the case of the Schottky contact type structure, does not occur in principle in such a semiconductor element. That is, a semiconductor element in which the reverse gate leakage current is sufficiently reduced as compared with the Schottky type is realized.

In particular, according to the first aspect of the present invention, in the semiconductor element having the field effect transistor structure, the reverse gate leakage current is sufficiently reduced as compared with the Schottky type.

In particular, according to the invention of claim 2 and claims 4 to 10 , the semiconductor element having a high electron mobility transistor structure has a sufficient reverse gate leakage current as compared with a Schottky type. Reduction is realized.

In particular, according to the inventions of claims 4 to 10 , a two-dimensional electron gas layer is effectively formed at the interface between the first and second nitride layers. A semiconductor device having a structure can be realized.

In particular, according to the inventions of claims 11 to 13 , in addition to lowering the specific resistance of the second semiconductor layer, it is possible to reduce the contact resistance of the second semiconductor layer in the gate portion, and in the reverse direction. Since the spread of the depletion layer to the second semiconductor layer when the gate voltage is applied can be suppressed, the second semiconductor layer can be formed thin. As a result, the series resistance component when the forward gate voltage is applied in the second semiconductor layer can be reduced.

<First Embodiment>
<Overall configuration of semiconductor element>
FIG. 1 is a diagram for explaining a cross-sectional structure of a semiconductor element 10 according to the first embodiment of the present invention. In addition, the ratio of each part in each figure after FIG. 1 does not necessarily reflect an actual thing. The semiconductor element 10 mainly includes a substrate 1, a first semiconductor layer 2, a gate part 3, a source part electrode, a drain electrode 5, and an insulating protective layer 6. The semiconductor element 10 has various configurations for functioning as a so-called field effect transistor element (FET).

The first semiconductor layer 2 is configured using a group III nitride expressed by a composition formula of Al _1-xy Ga _x In _y N (x ≧ 0, y ≧ 0, 0 ≦ x + y ≦ 1). More specifically, the first semiconductor layer 2 has a stacked structure in which a base layer 2a and an n-type conductive layer 2b are stacked.

The underlayer 2a is a high specific resistance layer formed using the group III nitride, preferably GaN, so as to realize a high specific resistance state of 1 × 10 ⁷ Ωcm or more. is there. A preferred example is a thickness of about several μm.

On the other hand, the n-type conductive layer 2b is an n-type conductive region configured to use electrons as majority carriers. A predetermined donor element (n-type dopant) is preferably used for the group III nitride having the above-described composition, preferably for Al _1-x Ga _x N (0 ≦ x ≦ 1), more preferably for GaN. ). For example, Si or the like can be used as the donor element. For example, a suitable example is to form GaN with a thickness of about several nanometers to several hundred nanometers by doping Si with a concentration of 2 × 10 ¹⁷ / cm ³ .

  Such a first semiconductor layer 2 is preferably formed by epitaxially growing a group III nitride on the substrate 1 using a known film formation method such as MOCVD. As the substrate 1, for example, a single crystal base material such as SiC or sapphire can be used. Alternatively, the substrate 1 may be formed by appropriately forming a buffer layer made of a group III nitride such as AlN or GaN on the single crystal base material. In addition, what formed the 1st semiconductor layer 2 in the board | substrate 1 may be called a semiconductor substrate.

  The gate unit 3 is formed at a predetermined position on the upper surface of the first semiconductor layer 2. More specifically, the gate unit 3 has a stacked structure in which the second semiconductor layer 3a and the gate electrode 3b are stacked in this order. The formation position of the gate portion 3, that is, the junction portion between the first semiconductor layer 2 and the gate portion 3 is referred to as a junction portion 7.

  The second semiconductor layer 3a is a p-type semiconductor layer configured to use holes as majority carriers by doping a group IV semiconductor with a predetermined acceptor element (p-type dopant). For example, B (boron) can be used as the acceptor element.

  The gate electrode 3b is a metal electrode made of, for example, Al, and is ohmic-bonded to the second semiconductor layer 3a by a known method.

  Both the source electrode 4 and the drain electrode 5 are metal electrodes made of, for example, Ti / Al, and are arranged to face each other with the gate portion 3 interposed therebetween. Both are ohmic-bonded to the second semiconductor layer 3a by a known method.

  The insulating protective layer 6 is formed to protect the surface layer of the semiconductor element 10 and to ensure electrical insulation. The insulating protective layer 6 is made of, for example, SiN.

<PN junction of gate part>
In the semiconductor element 10 configured as described above, a PN junction is formed between the n-type conductive layer 2b and the second semiconductor layer 3a that constitutes the gate portion 3 and is a p-type conductive layer. Will be. Since the gate electrode 3b is formed on the second semiconductor layer 3a, in the semiconductor element 10, a junction gate type field effect transistor structure in which the n-type conductive layer 2b functions as a channel layer is realized. Will be.

  If the gate electrode is in Schottky contact with the n-type conductive layer, there is a high density of free electrons inside the Schottky metal used as the gate electrode (for example, Pt). Occasionally, a reverse gate leakage current occurs due to electrons tunneling from the Schottky metal side to the conductive layer side in the depletion region.

  However, in the semiconductor element 10 according to the present embodiment, the reverse gate leakage current based on the electron tunnel is generated by realizing the junction gate type structure by the PN junction as described above. It does n’t happen. Thus, the reverse gate leakage current is sufficiently suppressed as compared with the Schottky type.

  FIG. 2 is a diagram for explaining a band structure immediately below the gate portion 3 of the semiconductor element 10. 2A is a diagram showing a band structure of a conventional FET using a Schottky electrode shown for comparison, and FIG. 2B is a diagram showing a band structure of the semiconductor element 10. FIG. 2A shows a case where the n-type conductive layer 102 and the gate electrode 103 are in Schottky contact at the junction 107. The energy value (unit eV) in FIG. 2 is the same as that in FIG. 2A when the n-type conductive layer 102 is formed of n-GaN and the gate electrode 103 is formed of Pt. As for (b), the n-type conductive layer 2b is made of n-GaN, the second semiconductor layer 3a is made of polycrystalline Si, and the gate electrode 3b is made of Al. Value.

In the semiconductor element 10, the presence of the second semiconductor layer 3 a raises the band of the n-type conductive layer 2 b as compared with the case of the Schottky contact, so that the diffusion potential becomes larger than that in the case of the Schottky contact. ing. Along with this, the width of the depletion region in the n-type conductive layer 2b is also increased. That is, assuming that the width of the depletion region in the Schottky contact is W1, the diffusion potential is V _D 1, the width of the depletion region of the semiconductor element 10 is W2, and the diffusion potential is V _D 2, W2> W1, V _D 2 > V _D 1 holds. That is, instead of the conventional mode in which the gate electrode is in Schottky contact with the n-type conductive layer, the PN junction between the n-type conductive layer 2b and the second semiconductor layer 3a which is the p-type conductive layer in the gate portion 3 By providing the gate electrode 3b with the second semiconductor layer 3a in ohmic contact with the second semiconductor layer 3a, a depletion region wider than the conventional one and a large diffusion potential can be obtained.

  Further, the fact that the diffusion potential is large also means that the maximum gate applied voltage specified by the diffusion potential is increased. This is the voltage at which the main current is pinched off in addition to the effect that the gate voltage can be applied to the positive side more greatly by replacing the Schottky contact with the PN junction. This means that a semiconductor element having a higher threshold voltage can be obtained.

FIG. 3 is a conceptual diagram showing a change in output current with respect to a gate applied voltage for a normally-on type semiconductor element, which is shown for explaining this. When the first semiconductor layer has the same configuration, the gate portion is replaced with a PN junction instead of a Schottky contact so that the diffusion potential of the gate junction increases, so that the value of the maximum gate applied voltage is V1 to V2. Will increase. Further, with an increase of the diffusion potential of the gate junction, so that the threshold voltage of the transistor is shifted to the positive side from V _t 1 to _{V t 2 (> V t 1} ). These correspond to the parallel movement of the output current curve shown in FIG. 3 in the positive direction of the horizontal axis. That is, in the case of the Schottky contact, if the threshold voltages in the case of the PN junction are expressed as V _t 1 and V _t 2, respectively, when the value of the maximum gate applied voltage changes from V 1 to V 2, the threshold voltage The voltage will change from V _t 1 to V _t 2 (> V _t 1).

  Note that it is preferable that the semiconductor element 10 has a junction gate type structure with a PN junction even when the semiconductor element 10 realizes normally-off. This will be described later.

<Detailed configuration of first semiconductor layer>
As described above, the base layer 2a and the n-type conductive layer 2b constituting the first semiconductor layer 2 are Al _1-xy Ga _x In _y N (x ≧ 0, y ≧ 0, 0 ≦ x + y ≦ 1). It is composed of a group III nitride expressed by a composition formula. In such a case, the group III nitride need not have a uniform composition in the entire first semiconductor layer 2 or in each of the base layer 2a and the n-type conductive layer 2b. For example, a configuration having a gradient composition may be used. Preferably, at least the vicinity of the junction 7 of the n-type conductive layer 2b is a group III nitride having a composition of y = 0, that is, a group III nitride having a composition of Al _1-x Ga _x N (0 ≦ x ≦ 1). Constructed with things. Thereby, the PN junction in the junction 7 can be realized with better characteristics.

<Detailed configuration of second semiconductor layer>
The second semiconductor layer 3a is preferably configured so that the hole concentration at least in the vicinity of the junction 7 is 1 × 10 ¹⁹ / cm ³ or more. In the case of having such a configuration, in addition to the specific resistance of the second semiconductor layer 3a itself being lowered, the contact resistance between the second semiconductor layer 3a and the gate electrode 3b can be reduced. Further, since the depletion layer can be prevented from spreading to the second semiconductor layer 3a when the reverse gate voltage is applied, the second semiconductor layer 3a can be formed thin. As a result, the series resistance component when the reverse gate voltage is applied in the second semiconductor layer 3a can be reduced. The second semiconductor layer 3a can be easily realized by containing an acceptor element such as B at a concentration of 1 × 10 ²⁰ / cm ³ or more.

As the group IV semiconductor material, for example, Si _1-z Ge _z (0 ≦ z ≦ 1) can be used. Such a second semiconductor layer 3a is formed on the first semiconductor layer 2 by submicron order using various physical vapor deposition methods such as CVD method, sputtering method, vapor deposition method and chemical vapor deposition method. Can be easily realized by stacking to a thickness of about several μm or less. Among these, using Si is preferable in terms of high controllability of layer formation. In such a case, Si may be polycrystalline.

At least the vicinity of the junction 7 of the first semiconductor layer 2 is configured using a group III nitride of Al _1-x Ga _x N (0 ≦ x ≦ 1), and at least the vicinity of the junction of the second semiconductor layer 3a is formed. A PN junction is formed at the junction 7 using Si _1-z Ge _z (0 ≦ z ≦ 1). As a result, a state in which the hole concentration in the second semiconductor layer 3a is high and the electron density is extremely small is realized, so that an effect that the reverse gate leakage current can be greatly reduced when the reverse gate voltage is applied is obtained.

<Normally off>
Next, a case where normally-off is realized in the semiconductor element 10 will be described. In order to obtain a normally-off semiconductor element, it is necessary to realize pinch-off without applying a gate voltage. As shown in FIG. 2, in the semiconductor element 10 according to the present embodiment, an n-type conductive layer is formed by forming a PN junction between the gate portion 3 and the first semiconductor layer 2 at the junction portion 7. In 2b, a wider depletion region is formed than in the Schottky contact. From this, even when the thickness of the n-type conductive layer 2b is increased or the donor concentration of the n-type conductive layer 2b is increased as compared with the case of a normally-off type device using a Schottky contact, A pinch-off state can be realized. In other words, the conduction cross section in the n-type conductive layer 2b can be increased by increasing the thickness, or the specific resistance of the n-type conductive layer 2b can be reduced by increasing the donor concentration, resulting in a higher conduction resistance. A semiconductor layer having a low thickness can be used as the first semiconductor layer. That is, by forming a PN junction between the gate portion 3 and the first semiconductor layer 2 at the junction portion 7, it is possible to obtain a normally-off type element having a lower conduction resistance than in the case of a Schottky contact. It becomes.

  The specific thickness of the n-type conductive layer 2b for realizing the normally-off operation in the field effect transistor varies depending on the carrier concentration of the semiconductor. Similarly, the specific carrier concentration of the n-type conductive layer 2b is It depends on the thickness of the semiconductor. Further, these conditions differ depending on the specific configuration of the gate unit 3. Therefore, a normally-off type element can be obtained by appropriately adjusting these. However, when a PN junction is used instead of a Schottky contact as a configuration of the gate portion 3 as in the present invention, As described above, a semiconductor layer having a lower conduction resistance can be used as the first semiconductor layer. As a result, a semiconductor element having better on characteristics when a forward gate voltage is applied than that of a Schottky contact is realized. FIG. 4 is a conceptual diagram of the change in the output current with respect to the gate applied voltage for a normally-off type semiconductor device for indicating this. In other words, when a normally-off type device is manufactured, a semiconductor layer having a lower conduction resistance can be used by replacing the gate portion with a PN junction instead of a Schottky contact, so that the same gate applied voltage can be used. The output current obtained in this way becomes large. In addition, by making the configuration of the gate portion a PN junction as in the present invention, the diffusion potential of the junction portion can be increased, so that the maximum gate applied voltage increases from V1 to V2, and as a result The maximum output current of the semiconductor element can be increased.

  As described above, according to the present embodiment, the gate configuration is changed to a junction gate type using a PN junction instead of the Schottky contact type, thereby sufficiently suppressing the reverse gate leakage current. A semiconductor device can be obtained. Further, when a normally-off type semiconductor element is manufactured, a gate portion structure having a larger diffusion potential than that in the case of a Schottky contact can be formed, and in addition, a semiconductor layer having a lower conduction resistance can be used. Therefore, a normally-off semiconductor element having excellent on characteristics can be obtained.

<Second Embodiment>
The configuration of the n-type conductive region in the semiconductor element is not limited to the above-described embodiment. In the present embodiment, a mode in which a so-called two-dimensional electron gas bears conductivity in the first semiconductor layer, that is, a mode in which the semiconductor element has a HEMT structure will be described.

  FIG. 5 is a view for explaining a cross-sectional structure of the semiconductor element 20 according to the second embodiment of the present invention. In addition, about the component which has an effect substantially the same as the component of the semiconductor element 10 which concerns on 1st Embodiment in the semiconductor element 20, the same code | symbol is attached | subjected and the description is abbreviate | omitted. In the semiconductor element 20, the first semiconductor layer 12 includes a base layer 12a and a wide band gap layer 12b, and a two-dimensional electron gas region 8 is formed in the vicinity of the interface between the base layer 12a and the wide band gap layer 12b. This is different from the semiconductor element 10 according to the first embodiment. The semiconductor element 20 has various configurations for functioning as a so-called high electron mobility transistor element (HEMT).

Both the underlayer 12a and the wide band gap layer 12b constituting the first semiconductor layer 12 are composed of Al _1-xy Ga _x In _y N (x ≧ 0, y ≧ 0, 0 ≦ x + y ≦ 1). It is comprised using the group III nitride represented by. Similarly to the semiconductor layer 2 according to the first embodiment, the first semiconductor layer 12 according to the present embodiment can also be formed using a known film formation technique.

As in the case of the underlayer 2a according to the first embodiment, the underlayer 12a is made of the group III nitride, preferably GaN, and has a high specific resistance state of 1 × 10 ⁷ Ωcm or more. Is a high resistivity layer formed so as to be realized.

On the other hand, the wide band gap layer 12b is formed using a group III nitride having a larger band gap than the group III nitride constituting the base layer 12a. For example, if the underlying layer is composed of GaN, a group III nitride represented by a composition formula of Al _1-x Ga _x N (x ≧ 0, y ≧ 0, 0 ≦ x + y ≦ 1) is used. A preferred example is to use it.

  In the vicinity of the heterointerface formed between the base layer 12a and the wide band gap layer 12b, electrons serving as carriers from the wide band gap layer 12b are caused by the band gap difference between the group III nitrides constituting both layers. Supplied. As a result, a two-dimensional electron gas region 8 in which electrons exist two-dimensionally and at a high concentration is formed. The underlayer 12a is preferably formed to a thickness of about several μm. On the other hand, the wide band gap layer 12b is formed to be several tens of nm or less at most in terms of forming a high-quality film, forming the two-dimensional electron gas region 8, and operating the device (that is, the main voltage applied to the gate voltage). This is preferable from the viewpoint of current controllability.

  In the semiconductor element 20 having such a structure, the two-dimensional electron gas region 8 substantially functions as an n-type conductive region.

  Further, since the semiconductor element 20 is the same as the semiconductor element 10 according to the first embodiment in that it has a junction gate type structure by a PN junction, it is in the reverse direction compared to the Schottky type. The gate leakage current is sufficiently suppressed.

FIG. 6 is a diagram for explaining a band structure immediately below the gate portion 3 of the semiconductor element 20. FIG. 6A is a diagram showing a band structure of a conventional HEMT using a Schottky electrode shown for comparison, and FIG. 6B is a diagram showing a band structure of the semiconductor element 20. In FIG. 6A, the two-dimensional electron gas layer 108 is formed at the junction interface between the base layer 112a and the wide band gap layer 112b, and the wide band gap layer 112b and the gate electrode 103 are Schottky at the junction 107. The case where it comes into contact is shown. Further, in FIG. 6A, the energy value (unit eV) in the figure is such that the base layer 112a is formed of high specific resistance GaN, and the wide band gap layer 112b is formed of Al _0.2 Ga _0.8 N. In FIG. 6B, when the gate electrode 103 is made of Pt, the base layer 12a is made of GaN having a high resistivity, and the wide band gap layer 12b is made of Al _0.2 Ga _0.8 N. These are approximate values when the second semiconductor layer 3a is made of polycrystalline Si and the gate electrode 3b is made of Al.

  As shown in FIG. 6, also in the semiconductor element 20 having the HEMT structure, the band of the wide band gap layer 12b is raised more than the case of the Schottky contact due to the presence of the second semiconductor layer 3a. Thereby, a large diffusion potential is realized as compared with the case of Schottky contact. That is, the semiconductor element 20 having a high maximum gate applied voltage can be obtained.

Also, a normally-off type semiconductor device 20 can be obtained as in the semiconductor device according to the first embodiment. However, in the case of the semiconductor element 20, the pinch-off state is realized by appropriately adjusting the thickness of the wide band gap layer 12b and the concentration of the two-dimensional electron gas in the two-dimensional electron gas region 8 according to the configuration of the gate portion. It will be. The concentration of the two-dimensional electron gas depends on the composition and thickness of the wide band gap layer 12b. For example, when the wide band gap layer 12b is Al _1-x Ga _x N, the concentration of the two-dimensional electron gas increases as the Al concentration increases. In addition, the concentration of the two-dimensional electron gas increases as the film thickness of the wide band gap layer 12b increases. That is, the pinch-off state can be realized by adjusting the composition and film thickness of the wide band gap layer 12b.

In the semiconductor element 20 according to the present embodiment, by using a PN junction instead of a Schottky contact as a configuration of the gate portion 3, as shown in FIG. It will be in the state where it was lifted rather than the case of contact. Therefore, if the film thickness is the same, a phenomenon occurs in which the concentration of the two-dimensional electron gas in the two-dimensional electron gas region 8 is substantially reduced as compared with the case of the Schottky contact. This means that a pinch-off state can be realized even when the wide band gap layer 12b is made thicker than in the case of a normally-off type element using a Schottky contact. Further, when the wide band gap layer 12b is Al _1-x Ga _x N, it means that a pinch-off state can be realized even when the Al concentration is increased. In other words, a semiconductor layer having a lower conduction resistance can be used as the first semiconductor layer.

  That is, by forming a PN junction between the gate portion 3 and the first semiconductor layer 2 at the junction portion 7, it is possible to obtain a normally-off type element having a lower conduction resistance than in the case of a Schottky contact. It becomes. As a result, a semiconductor element having a higher output current than that of a Schottky contact is realized, more specifically, an on characteristic when a forward gate voltage is applied. In addition, since the diffusion potential at the junction can be increased by configuring the gate portion as a PN junction, the maximum gate applied voltage increases from V1 to V2, resulting in the maximum output of the semiconductor element. The current can be increased.

<Detailed structure of first semiconductor layer>
Both the base layer 2a and the n-type conductive layer 2b that form the first semiconductor layer 12 do not need to exist as a uniform composition layer, and may have a gradient composition. Alternatively, at least one of the base layer 2a and the n-type conductive layer 2b may be formed by laminating a plurality of layers formed using Group III nitrides having different compositions. Such a laminated structure can also be easily manufactured by using a known film forming method such as MOCVD method or molecular beam epitaxial growth method or a combination thereof.

For example, the wide band gap layer 12b has a thickness of about several nm to several tens of nm using a group III nitride having a composition in which at least the vicinity of the junction 7 is Al _1-x Ga _x N (0 ≦ x ≦ 1). Preferably it is comprised. In that case, in a mode in which a plurality of layers having different compositions (that is, a plurality of layers having different values of x) are laminated by a group III nitride having a composition of Al _1-x Ga _x N (0 ≦ x ≦ 1). There may be. In such a case, for example, an n-type conductive layer doped with Si may be included. Further, from the viewpoint of effectively generating the two-dimensional electron gas, it is more preferable to configure the portion adjacent to the base layer 12a using AlN.

On the other hand, the base layer 12a is at least a part adjacent to the wide band gap layer 12b by using several hundreds of group III nitrides represented by the composition formula Ga _{1 -w} In _w N (0 ≦ w ≦ 1). It is preferable to have a thickness of about nm to several μm. In that case, in a mode in which a plurality of layers having different compositions (that is, a plurality of layers having different values of w) are laminated by a group III nitride having a composition of Ga _1-w In _w N (0 ≦ w ≦ 1). There may be.

  From the standpoint of effectively generating a two-dimensional electron gas, the underlayer 12a is preferably configured using GaN at least in a portion not adjacent to the wide band gap layer 12b. Since GaN has particularly good crystal quality among the group III nitrides, it is possible to improve the crystallinity in the two-dimensional electron gas region 8 formed thereon and responsible for conduction. Thereby, the series resistance component when the forward gate voltage is applied can be further reduced, and the gate leakage current when the reverse gate voltage is applied can be further reduced.

  Furthermore, it is more preferable that the underlying layer 12a is made of GaN in the portion adjacent to the wide band gap layer 12b. Thereby, it is possible to further reduce the series resistance component when the forward gate voltage is applied and further reduce the gate leakage current when the reverse gate voltage is applied.

  In addition, it is desirable that the group III nitride constituting the stacked structure as described above in the first semiconductor layer 12 has a wurtzite crystal structure. Furthermore, it is desirable that the laminated surface corresponds to the (0001) plane of the wurtzite crystal. In the case of such a configuration, a two-dimensional electron gas is effectively generated due to the piezoelectric polarization effect and the spontaneous polarization effect generated inside the crystal, and this is also the series resistance of the semiconductor element 20. This is because it contributes to the reduction of components.

  As described above, according to the present embodiment, even when the HEMT structure is provided, the structure of the gate portion is changed to the junction gate type by the PN junction instead of the Schottky contact type. A semiconductor element in which the reverse gate leakage current is sufficiently suppressed can be obtained. In addition, a normally-off semiconductor element having excellent on characteristics can be obtained.

<Modification>
The structure of the junction gate type semiconductor element having a PN junction in the gate portion is not limited to that of the above-described embodiment. FIG. 7 is a diagram for explaining a cross-sectional structure of a semiconductor element 30 which is a junction gate type semiconductor element and has a gate recess structure. In FIG. 7, the same reference numerals are given to the constituent elements having the same operational effects as the constituent elements of the semiconductor element according to the above-described embodiment in the semiconductor element 30, and the description thereof is omitted.

  In the semiconductor element 30, the wide band gap layer 12 c formed by etching just below the gate portion 3 is provided on the base layer 12 a formed on the substrate 1 in the same manner as the second embodiment. A gate recess structure is realized.

  In such a semiconductor element 30, the thickness d (residual film thickness after etching) of the wide band gap layer 12 c immediately below the gate portion 3 is appropriately determined, that is, by adjusting the etching depth, An off-type can also be obtained.

  As examples and comparative examples, various semiconductor elements were produced and their characteristics were evaluated. FIG. 8 is a diagram showing a list of characteristics of each semiconductor element. Note that, as the maximum output current density in FIG. 8, a value obtained when the gate voltage is set to the allowable maximum value is described.

Example 1
As Example 1, a normally-on type semiconductor device according to the first embodiment was manufactured.

A semi-insulating SiC substrate and a single crystal sapphire substrate were prepared. A buffer layer (a layer made of 200 nm thick AlN in the case of a SiC substrate and a layer made of GaN 30 nm in the case of a single crystal sapphire substrate) was formed on these substrates by MOCVD. As a result, two types of substrates 1 are obtained. Hereinafter, the substrate 1 using a semi-insulating SiC substrate is simply referred to as an SiC substrate, and the substrate 1 using a single crystal sapphire substrate is simply referred to as a sapphire substrate. Subsequently, a GaN layer having a specific resistance of 1 × 10 ⁷ Ωcm or more is formed to a thickness of 2 μm on the two kinds of substrates 1 as an underlayer 2a by MOCVD, and an Si concentration is 2 as an n-type conductive layer 2b. A GaN layer having a thickness of × 10 ¹⁷ / cm ³ was formed to a thickness of 0.2 μm. The sheet resistance value of the semiconductor substrate thus obtained was about 4000 Ω / sq for the SiC substrate and about 4500 Ω / sq for the sapphire substrate.

  On the main surface of each of the obtained semiconductor substrates, a metal layer made of Ti / Al is formed at the formation position of the source electrode 4 and the drain electrode 5 using photolithography and vacuum deposition, and then in a nitrogen atmosphere The ohmic contact was obtained about each metal layer by heat-processing. Thereby, the source electrode 5 and the drain electrode 6 were obtained.

Subsequently, at the position where the gate portion 3 is formed, photolithography and low-pressure CVD are used, and the second semiconductor layer 3a layer has a hole concentration of about 2 × 10 ²⁰ / cm3 so that the hole concentration becomes 1 × 10 ¹⁹ / cm ³ or more. A polycrystalline Si layer doped with cm ³ boron was formed to a thickness of 0.5 μm.

  Further, an Al metal layer is formed on the polycrystalline Si layer using a vacuum deposition method, and a heat treatment at 440 ° C. is performed in a mixed atmosphere of nitrogen and hydrogen, whereby the polycrystalline Si layer is formed on the Al metal layer. Ohmic contact was obtained. Thereby, the gate electrode 3b was obtained.

  Finally, a wiring extraction pad (not shown) was formed for each electrode to obtain a junction gate type field effect transistor as the semiconductor element 10. It was confirmed that the obtained semiconductor element 10 was a normally-on operation type device in which a main current flows at a gate voltage of 0V.

  Note that the gate length and gate width of the fabricated junction gate field effect transistor are 0.5 μm and 100 μm, respectively.

(Comparative Example 1)
As Comparative Example 1, a normally-on type field effect transistor element having a Schottky contact type gate structure was manufactured.

  Specifically, except for the formation of the gate portion, it is performed in the same manner as in the case of the SiC substrate of Example 1, and instead of forming the gate portion, using the photolithography and the vacuum deposition method at the formation position of the gate portion, A gate electrode made of Pt / Au was formed by Schottky contact.

  The semiconductor element obtained in this comparative example was also confirmed to be a normally-on device.

(Example 2)
As Example 2, a normally-off type semiconductor device according to the first embodiment was manufactured.

  Specifically, semiconductor elements having different thicknesses of the GaN layers as the n-type conductive layer 2b were manufactured in the same procedure as that for the SiC substrate of Example 1. As a result, a GaN layer having a thickness of 65 nm or less was obtained as a normally-off operation type semiconductor element in which a main current does not flow at a gate voltage of 0 V. The sheet resistance value of the semiconductor substrate having a GaN layer thickness of 65 nm was about 6000 Ω / sq.

(Comparative Example 2)
As Comparative Example 2, a normally-off type field effect transistor element having the same configuration as Comparative Example 1 was produced.

  Specifically, semiconductor elements having different thicknesses of GaN layers as n-type conductive layers were prepared in the same procedure as in Comparative Example 1. As a result, a GaN layer having a thickness of 50 nm or less was obtained as a normally-off operation type semiconductor element in which a main current does not flow at a gate voltage of 0V. In such a case, the sheet resistance value of the semiconductor substrate was about 8500 Ω / sq.

(Example 3)
As Example 3, a normally-on type semiconductor device according to the second embodiment was manufactured.

A SiC substrate and a sapphire substrate similar to those of Example 1 are prepared as the substrate 1, and a specific resistance 1 × 10 ^{7 is formed} thereon as a buffer layer made of AlN having a thickness of 200 nm and an underlayer 12a by using MOCVD. A GaN layer of Ωcm or more was formed to a thickness of 2 μm, and an AlGaN layer having an Al mixed crystal ratio of 0.2 was formed as a wide band gap layer 12b to a thickness of 25 nm. When the Hall effect measurement was performed on the semiconductor substrate thus obtained, the sheet electron concentration was about 1 × 10 ¹³ / cm ² , the electron mobility was about 1400 cm ² / Vs, and the sheet resistance was about the SiC substrate. The sheet electron concentration was about 1 × 10 ¹³ / cm ² , the electron mobility was about 1250 cm ² / Vs, and the sheet resistance was about 500 Ω / sq.

  Using the obtained semiconductor substrate, a source electrode, a drain electrode, and a gate part (second semiconductor layer and gate electrode) were formed in the same manner as in the process shown in Example 1, and a semiconductor element 20 was obtained. The obtained semiconductor element 20 was confirmed to be a normally-on operation type device in which a main current flows at a gate voltage of 0 V.

(Comparative Example 3)
As Comparative Example 3, a normally-on type high-electron mobility transistor element having a Schottky contact type gate structure was manufactured.

  Except for the formation of the gate part, it is performed in the same manner as in the case of the SiC substrate of Example 3, and instead of forming the gate part, the formation position of the gate part is made of Pt / Au using photolithography and vacuum deposition. A gate electrode was formed by Schottky contact.

  The semiconductor element obtained in this comparative example was also confirmed to be a normally-on device.

Example 4
As Example 4, a normally-off type semiconductor device according to the second embodiment was manufactured.

  Specifically, semiconductor elements having different thicknesses of the AlGaN layer as the wide band gap layer 12b were manufactured in the same procedure as that of the SiC substrate of Example 3. As a result, an AlGaN layer having a thickness of 18 nm or less was obtained as a normally-off operation type semiconductor element in which a main current does not flow at a gate voltage of 0V.

In the Hall effect measurement performed on a semiconductor substrate having an AlGaN layer thickness of 18 nm, the sheet electron concentration is about 0.9 × 10 ¹³ / cm ² , the electron mobility is about 1400 cm ² / Vs, and the sheet resistance is about 500Ω / A result of sq was obtained.

(Comparative Example 4)
As Comparative Example 4, a normally-off type high-electron mobility transistor element having the same configuration as that of Comparative Example 3 was produced.

  Specifically, semiconductor elements with different thicknesses of the AlGaN layer as the wide band gap layer were prepared in the same procedure as in Comparative Example 3. As a result, an AlGaN layer having a thickness of 8 nm or less was obtained as a normally-off operation type semiconductor element in which a main current does not flow at a gate voltage of 0V.

In the Hall effect measurement performed on a semiconductor substrate having an AlGaN layer thickness of 18 nm, the sheet electron concentration is about 0.7 × 10 ¹³ / cm ² , the electron mobility is about 1000 cm ² / Vs, and the sheet resistance is about 900 Ω / A result of sq was obtained.

(Contrast between Example 1 to Example 4 and Comparative Example 1 to Comparative Example 4)
As shown in Table 1, in the semiconductor elements of Examples 1 to 4 having the junction gate type structure, the reverse gate leakage current is larger than that of the semiconductor elements of Comparative Examples 1 to 4 having the Schottky contact type structure. Was found to be significantly lower. This is understood to be due to the fact that the junction gate type structure using the p-type semiconductor layer having a low electron concentration has suppressed the inflow of electrons when the reverse gate voltage is applied.

  Further, in Example 1 in which a normally-on type semiconductor device was manufactured using different substrates, it was confirmed that the output current characteristics were superior when the SiC substrate was used. Similar results were confirmed in Example 3. This is understood based on the fact that a semiconductor layer having a lower sheet resistance is obtained by using the SiC substrate. On the other hand, since there is no significant difference in the reverse gate leakage current, it is clear that the present invention is effective regardless of the substrate material.

  Further, when Example 1 and Example 3 in which normally-on type semiconductor elements are both manufactured are compared with Comparative Example 1 and Comparative Example 3, the former is greater in terms of the maximum gate applied voltage and the threshold voltage. It was confirmed to be large.

  Furthermore, when Example 2 and Example 4 which produced the normally-off type semiconductor element were compared with Comparative Example 2 and Comparative Example 4, the former had a larger maximum gate applied voltage and maximum output current density. It was confirmed. This shows that the normally-off state can be realized by using a semiconductor substrate having a lower sheet resistance value as a result of the diffusion potential at the gate junction being increased by using the p-type semiconductor layer. .

(Example 5)
As Example 5, a normally-on type semiconductor device according to the second embodiment having a wide band gap layer having a two-layer structure was manufactured.

  Specifically, the same procedure as in Example 3 was performed except for the formation of the wide band gap layer. The wide band gap layer was obtained by forming an AlN layer with a thickness of 1 nm by MOCVD and then forming an AlGaN layer with an Al mixed crystal ratio of 0.2 to a thickness of 25 nm.

When the Hall effect measurement was performed on the semiconductor substrate thus obtained, the sheet electron concentration was about 1 × 10 ¹³ / cm ² , the electron mobility was about 2000 cm ² / Vs, and the sheet resistance was about 300 Ω / sq. there were.

  With respect to the obtained semiconductor element, it was confirmed that the main current flows at a gate voltage of 0 V, that is, a normally-on operation type device.

(Example 6)
As Example 6, in the semiconductor element according to the second embodiment, a base layer having a two-layer structure and a normally-on type was manufactured.

  Specifically, the same procedure as in Example 3 was performed except for the formation of the underlayer.

As the underlayer, an MOGaN method is used to form a GaN layer having a specific resistance of 1 × 10 ⁷ Ωcm or more to a thickness of 2 μm, and an InGaN layer having an In mixed crystal ratio of 0.1 is formed to a thickness of 5 nm. Was obtained by

When the Hall effect measurement was performed on the semiconductor substrate thus obtained, the sheet electron concentration was about 1.5 × 10 ¹³ / cm ² , the electron mobility was about 1000 cm ² / Vs, and the sheet resistance was about 400 Ω / sq. I got the value.

  With respect to the obtained semiconductor element, it was confirmed that the main current flows at a gate voltage of 0 V, that is, a normally-on operation type device.

(Example 7)
As Example 7, a normally-off type semiconductor device according to a modification was manufactured.

  Specifically, the same procedure as in Example 3 was performed until the formation of the source electrode and the drain electrode.

  Subsequently, using photolithography and reactive ion etching, etching was performed in a region above the position where the gate portion 3 was to be formed so that the remaining film thickness d of the AlGaN layer was 18 nm or less.

  Thereafter, in the etched region, a gate portion made of a polycrystalline Si layer as the second semiconductor layer 3a and an Al metal layer as a gate electrode was formed in the same manner as in Example 1.

  With respect to the obtained semiconductor element, it was confirmed that the main current does not flow at a gate voltage of 0 V, that is, it is a normally-off operation type device.

(Contrast between Example 3 and Example 5 and Example 6)
The semiconductor elements manufactured in Example 5 and Example 6 have different layer configurations based on the structure of a normally-on semiconductor element having a high electron mobility transistor structure according to Example 3. . In any of the semiconductor elements, it was confirmed that a maximum output current density higher than that of the semiconductor element according to Example 3 was obtained. This means that the sheet resistance can be made lower than that of the semiconductor element shown in Example 3 by forming a plurality of wide band gap layers and underlying layers.

(Contrast between Example 4 and Example 7)
The semiconductor device manufactured in Example 7 realized a normally-off state similar to that of the semiconductor device having the high electron mobility transistor structure according to Example 4 by thinning only the AlGaN layer immediately below the gate portion. . The output current characteristics in Example 7 are better than those in Example 4. In the case of Example 7, unlike Example 4, a normally-off state can be realized without forming the AlGaN layer thin at the time of layer formation, and the thickness of the AlGaN layer in the portion other than directly below the gate portion is the layer thickness. Since it remains as formed, it is understood that low sheet resistance is maintained in the AlGaN layer other than just below the gate portion.

It is a figure for demonstrating the cross-section of the semiconductor element 10 which concerns on 1st Embodiment. 2 is a diagram for explaining a band structure of a semiconductor element 10. FIG. It is a conceptual diagram of the change of the output current with respect to the gate applied voltage about the normally-on type semiconductor element. It is a conceptual diagram of the change of the output current with respect to the gate applied voltage about the normally-off type semiconductor element. It is a figure for demonstrating the cross-section of the semiconductor element 20 which concerns on 2nd Embodiment. 3 is a diagram for explaining a band structure of a semiconductor element 20. FIG. It is a figure for demonstrating the cross-section of the semiconductor element 30 concerning a modification. It is a figure which lists and shows the characteristic of the semiconductor element obtained in the Example and the comparative example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Board | substrate 2 1st semiconductor layer 2a, 12a Underlayer 2b N-type conductive layer 3 Gate part 3a 2nd semiconductor layer 3b Gate electrode 4 Source electrode 5 Drain electrode 6 Insulating protective layer 7 Junction part 8 Two-dimensional electron gas area 10, 20 , 30 Semiconductor element 12 Semiconductor layer 12a Underlayer 12b, 12c Wide band gap layer

Claims (13)

A semiconductor element,
Each non-conductive first layer is composed of a group III nitride expressed by a composition formula of Al _1-xy Ga _x In _y N (x ≧ 0, y ≧ 0, 0 ≦ x + y ≦ 1). A first semiconductor layer formed by laminating one nitride layer and a second nitride layer which is an n-type conductive region in this order;
A gate portion formed by bonding to the first semiconductor layer;
With
The second nitride layer is formed to a thickness of 65 nm or less with a dopant concentration of 2 × 10 ¹⁷ / cm ³ ;
The gate portion is
A second semiconductor layer formed on the first semiconductor layer using a group IV semiconductor material so as to have a p-type conductivity;
A gate metal electrode formed in ohmic contact with the second semiconductor layer;
Consists of
The acceptor concentration of the second semiconductor layer is 1 × 10 ²⁰ / cm ³ or more at least in a portion joined to the first semiconductor layer ,
A junction gate field effect transistor structure having the n-type conductive region as a channel layer is formed;
The semiconductor element characterized by the above-mentioned. A semiconductor element,
The first and second layers each composed of a group III nitride expressed by a composition formula of Al _1-xy Ga _x In _y N (x ≧ 0, y ≧ 0, 0 ≦ x + y ≦ 1). The electron layer formed two-dimensionally in the vicinity of the stack interface between the first and second nitride layers substantially acts as an n-type conductive region. 1 semiconductor layer;
A gate portion formed by bonding to the first semiconductor layer;
With
The second nitride layer is formed to a thickness of 18 nm or less;
The gate portion is
A second semiconductor layer formed on the first semiconductor layer using a group IV semiconductor material so as to have a p-type conductivity;
A gate metal electrode formed in ohmic contact with the second semiconductor layer;
Consists of
The acceptor concentration of the second semiconductor layer is 1 × 10 ²⁰ / cm ³ or more at least in a portion joined to the first semiconductor layer ,
A junction gate field effect transistor structure having the n-type conductive region as a channel layer is formed;
The semiconductor element characterized by the above-mentioned. The semiconductor device according to claim 1 or 2, wherein
Of the first semiconductor layer, at least a portion bonded to the second semiconductor layer is configured by using a group III nitride expressed by a composition formula of Al _1-x Ga _x N (0 ≦ x ≦ 1). To be
The semiconductor element characterized by the above-mentioned. The semiconductor device according to claim 2,
At least in the adjacent part of the first and second nitride layers, the group III nitride forming the first nitride layer is larger than the band gap of the group III nitride forming the second nitride layer. The forbidden bandwidth of things is narrower,
The semiconductor element characterized by the above-mentioned. The semiconductor device according to claim 4,
The second nitride layer is configured using a group III nitride expressed by a composition formula of Al _1-x Ga _x N (0 ≦ x ≦ 1).
The semiconductor element characterized by the above-mentioned. The semiconductor device according to claim 5,
The second nitride layer is formed using AlN at least in a portion adjacent to the first nitride layer.
The semiconductor element characterized by the above-mentioned. The semiconductor device according to claim 4, wherein:
The first nitride layer uses a group III nitride expressed by a composition formula Ga _1-w In _w N (0 ≦ w ≦ 1) at least in a portion adjacent to the second nitride layer. Composed of,
The semiconductor element characterized by the above-mentioned. The semiconductor device according to claim 7,
The first nitride layer is formed using GaN at least in a portion not adjacent to the second nitride layer.
The semiconductor element characterized by the above-mentioned. The semiconductor device according to claim 8,
The first nitride layer is made of GaN;
The semiconductor element characterized by the above-mentioned. The semiconductor device according to claim 4, wherein:
Each of the first and second nitride layers is formed using a group-III nitride having a wurtzite structure and having a (0001) plane as a main surface.
The semiconductor element characterized by the above-mentioned. A semiconductor device according to any one of claims 1 to 10,
The hole concentration of the second semiconductor layer is 1 × 10 ¹⁹ / cm ³ or more at least in a portion bonded to the first semiconductor layer.
The semiconductor element characterized by the above-mentioned. A semiconductor device according to any one of claims 1 to 11,
The group IV semiconductor material is Si _1-z Ge _z (0 ≦ z ≦ 1) at least in a portion bonded to the first semiconductor layer .
The semiconductor element characterized by the above-mentioned. The semiconductor device according to claim 12 ,
The group IV semiconductor material is Si at least in a portion bonded to the first semiconductor layer.
The semiconductor element characterized by the above-mentioned.

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