CN109545851A - Enhanced GaN base power device and preparation method thereof - Google Patents
Enhanced GaN base power device and preparation method thereof Download PDFInfo
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- CN109545851A CN109545851A CN201811227030.0A CN201811227030A CN109545851A CN 109545851 A CN109545851 A CN 109545851A CN 201811227030 A CN201811227030 A CN 201811227030A CN 109545851 A CN109545851 A CN 109545851A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 19
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 229920005591 polysilicon Polymers 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 10
- 230000000873 masking effect Effects 0.000 claims abstract description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 9
- 238000005566 electron beam evaporation Methods 0.000 claims abstract description 8
- 238000000137 annealing Methods 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000001259 photo etching Methods 0.000 claims abstract description 7
- 238000001312 dry etching Methods 0.000 claims abstract description 6
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 238000004151 rapid thermal annealing Methods 0.000 claims description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 3
- 230000005611 electricity Effects 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 229910002601 GaN Inorganic materials 0.000 description 35
- 239000000463 material Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- 229910017083 AlN Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- -1 InP compound Chemical class 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 244000078703 ectoparasite Species 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention belongs to field of semiconductor devices, specially a kind of enhanced GaN base power device and preparation method thereof.The present invention selects AlGaN/GaN on Si to expose the source electrode and drain electrode figure of Ohmic contact out on substrate as substrate, and the first metal of electron beam evaporation forms the source electrode and drain electrode of device after remove photoresist removing and annealing；Then masking layer is formed, the table top figure of device out, masking layer described in dry etching and the AlGaN layer is exposed and crosses and carve, form device region.Photoetching, etching form grid opening, and depositing polysilicon carries out p-type doping and anneals, and photoetching, etching form P-type polysilicon gate；Finally, the figure of exposed metal lead, the second metal of electron beam evaporation, by removing photoresist, removing obtains metal lead wire, obtains enhanced GaN base power device.The present invention uses p-type grid, effectively inhibits grid leak electricity, improves device threshold voltage stability, and have higher compatibility with silicon integrated circuit technique.
Description
Technical field
The invention belongs to field of semiconductor devices, and in particular to a kind of enhanced GaN base power device and preparation method thereof.
Background technique
GaN material is after first generation Ge, Si semiconductor material, second generation GaAs, InP compound semiconductor materials
Third generation semiconductor material, due to its material property outstanding, such as its distinctive polarity effect, biggish forbidden bandwidth, high strike
Electric field, high density two-dimensional electron gas are worn, hot operation etc. is production high temperature, high pressure, the reason of high-frequency large-power microwave power device
Think material, these advantages determine that AlGaN/GaN HEMT will have bright application prospect, depletion type in terms of microwave power
AlGaN/GaN HEMTs device and its mmic chip obtain batch application in phased-array radar T/R component, this also indicates height
Fast digital-to-analog circuit, high-speed power transformation is expected to the new opplication as GaN device, and will likely become mainstream Si power half in the latter
One of conductor device and its integrated very strong competitor.
However, traditional AlGaN/GaN HEMT device forms natural electricity because of polarity effect between source-drain electrode
Sub-channel, therefore need after grid making alive, the two-dimensional electron gas in grid lower channels can be just exhausted, channel is off
State.Therefore, depletion type GaN device had both been unfavorable for the low-power consumption of chip, also needed to increase the negative supply realization turn-off function assisted,
This is compatible with universal electronic system standard more difficult.Currently, researcher proposes respectively utilizes D-Mode GaN/N-MOS
(Si) concatenated cascode structure (Cascode), the enhanced GaN device of growth P-GaN cap realization in AlGaN potential barrier
Part, but the ectoparasite element of more piece is introduced by the former circuit framework influence device performance and reliability more seriously, and
There are grid grade electric current I in device exploitation for P-GaN cap structuregIt is larger cause threshold voltage shift, grid generate it is larger
Heat power consumption, and the technique of etching cap many technical problems such as is not easy to monitor, and sets in subsequent GaN power drive
Biggish design difficulty is increased again in meter and integrated application, also needs to provide the buffer of ampere grade current driving ability
(Buffer) driving stage.
Summary of the invention
The purpose of the present invention is to provide a kind of increasings that can be effectively inhibited grid leak electricity, improve device threshold voltage stability
Strong type GaN base power device and preparation method thereof.
Enhanced GaN base power device preparation method provided by the invention, comprising the following steps:
AlGaN/GaN is as substrate on selection Si；
The source electrode and drain electrode figure of Ohmic contact out, the first metal of electron beam evaporation, by stripping of removing photoresist are exposed over the substrate
From with after annealing, the source electrode and drain electrode of device is formed；
Masking layer is formed, the table top figure of device out, masking layer described in dry etching and the AlGaN layer is exposed and crosses and carve, shape
At device region；
Photoetching, etching form grid opening；
Depositing polysilicon carries out p-type doping and anneals, and photoetching, etching form p-type grid；And
The figure of exposed metal lead, the second metal of electron beam evaporation obtain metal lead wire by removing of removing photoresist.
In preparation method of the present invention, preferably, the masking layer is Si3N4。
In preparation method of the present invention, preferably, the polysilicon with a thickness of the nm of 100 nm ~ 150.
In preparation method of the present invention, preferably, the doping concentration of the p-type grid is 5e18/cm3~3e19/cm3。
In preparation method of the present invention, preferably, dosage is carried out to the polysilicon using ion implanting or method of diffusion
For 1e14/cm2~2e14/cm2, energy be the keV of 30keV ~ 35 B adulterate.
In preparation method of the present invention, preferably, to the polysilicon in 800 ~ 850 DEG C of 30 ~ 35 s of rapid thermal annealing, or
In 900 ~ 950 DEG C of 5 ~ 10 min of furnace annealing.
In preparation method of the present invention, preferably, the depth carved of crossing is the nm of 5nm ~ 10.
In preparation method of the present invention, preferably, first metal is Au/Ni/Al/Ti, it is followed successively by 20 from bottom to top ~
The Ti layer of 40nm thickness, the Al layer of 120 ~ 150 nm thickness, the Ni layer of 50 ~ 65nm thickness and the Au layer of 65 ~ 80nm thickness；
Second metal is Au/Ni, is followed successively by the Ni layer of 20 ~ 40nm thickness and the Au layer of 60 ~ 90nm thickness from bottom to top.
The invention also includes the enhanced GaN base power devices obtained by above-mentioned preparation method, comprising:
The upper AlGaN/GaN substrate of Si, source electrode, drain and gate, wherein the grid is p-type.
Enhanced GaN base power device of the invention, preferably, the doping concentration of the p-type grid are 5e18/cm3
~3e19/cm3。
The present invention can effectively inhibit reverse-biased grid leak electricity as grid using p-type, improve the threshold voltage of device,
To obtain enhanced GaN base power device.In addition, can be had with silicon integrated circuit technique using p-type as gate electrode
Higher compatibility.
Detailed description of the invention
Fig. 1 is the flow chart of enhanced GaN base power device preparation method of the invention.
Fig. 2 is the device architecture schematic diagram after forming source electrode and drain electrode.
Fig. 3 is the device architecture schematic diagram after forming device region.
Fig. 4 is the device architecture schematic diagram after forming p-type grid.
Fig. 5 is the structural schematic diagram of enhanced GaN base power device.
Fig. 6 is the enhanced GaN base power device of the invention based on p-type grid and traditional based on p-type GaN grid
Enhanced GaN base power device performance analysis chart.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it should be understood that described herein
Specific examples are only used to explain the present invention, is not intended to limit the present invention.Described embodiment is only the present invention one
Divide embodiment, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making
All other embodiment obtained, shall fall within the protection scope of the present invention under the premise of creative work.
In the description of the present invention, it should be noted that the orientation or positional relationship of the instructions such as term " on ", "lower" is base
In orientation or positional relationship shown in the drawings, it is merely for convenience of description of the present invention and simplification of the description, rather than indication or suggestion
Signified device or element must have a particular orientation, be constructed and operated in a specific orientation, therefore should not be understood as to this
The limitation of invention.
In addition, many specific details of the invention, such as the structure of device, material, size, place are described hereinafter
Science and engineering skill and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can be with
The present invention is not realized according to these specific details.Unless hereinafter particularly point out, the various pieces in device can be by
Material well known to those skilled in the art is constituted, or can be using the material with similar functions of exploitation in the future.
Fig. 1 is the flow chart of enhanced GaN base power device preparation method of the invention.This hair is directed to below in conjunction with Fig. 1
The specific steps of bright enhanced GaN base power device preparation method are illustrated.
AlGaN102/GaN101 is as substrate material on step S1, the Si100 of selection, wherein AlGaN102 layers with a thickness of
5nm ~8nm.But the present invention is not limited thereto, and silicon carbide, sapphire, gallium nitride, aluminium nitride, oxygen can be selected in substrate material
Change the monocrystal material of gallium, the suitable nitride epitaxial growth such as silicon-on-insulator (SOI) as support substrate, AlGaN/GaN layers
It can be multilayer.Then, normalized optical photoetching process is used on AlGaN102/GaN101 substrate on Si100, exposes ohm out
The source electrode and drain electrode figure of contact.Then, deposited by electron beam evaporation sequentially forms the Al of the Ti layer of 20 nm of thickness, 120 nm of thickness
Layer, 55 nm of thickness 65 nm of Ni layer and thickness Au layer.After removing of removing photoresist, in 800 DEG C ~ 850 DEG C rapid thermal annealings
50 s form source electrode 103 and the drain electrode 104 of device.The signal of the device architecture after forming source electrode and drain electrode is shown in FIG. 2
Figure.
Step S2 deposits 100 nm Si using physical gas-phase deposite method (PECVD)3N4105 are used as masking layer, expose out
Table top (MESA) figure of device.Then, reactive ion etching dry etching Si is utilized3N4105 and AlGaN layer 102, and cross and carve
5nm ~ 10nm is clean to guarantee to etch AlGaN layer, forms device region, resulting structures are as shown in Figure 3.
Step S3 exposes the figure of grid opening out, dry etching Si3N4 105 form grid opening.Then, low-pressure is utilized
The polysilicon of chemical vapour deposition technique (LPCVD) deposit 100nm ~ 150nm thickness.Carrying out dosage using ion implanting or diffusion is
1e14/cm2~2e14/cm2, the B that energy is the keV of 30keV ~ 35 adulterates, and annealed at 800 DEG C with rapid thermal annealing 30 s or
Person furnace annealing 5min ~ 10min at 900 DEG C, obtaining doping concentration is 5e18/cm3~3e19/cm3P-type.Finally, exposing
Light goes out the figure of p-type grid, with the unshielded polysilicon membrane of dry etching and removes photoresist, obtains p-type grid
106, as shown in Figure 4.
Step S4, the figure of exposed metal lead, deposited by electron beam evaporation form the Au of Ni and the 60nm thickness of 20nm thickness, pass through
It removes photoresist removing, obtains metal lead wire 107, and finally prepare the enhanced GaN base power device based on p-type grid, such as
Shown in Fig. 5.
More than, it has been carried out in detail for the specific embodiment of enhanced GaN base power device preparation method of the invention
Illustrate, but the present invention is not limited thereto.The specific embodiment of each step according to circumstances can be different, such as doping concentration,
Annealing temperature, metal species etc..In addition, the sequence of part steps can exchange, part steps be can be omitted.
Fig. 5 is the schematic diagram of enhanced GaN base power device of the invention.As shown in figure 5, enhanced GaN base power device
Part includes AlGaN102/GaN101 substrate on Si100, source electrode 103, drain electrode 104 and grid 106, wherein grid 106 is that p-type is more
Crystal silicon.It is further preferred that the doping concentration of p-type grid is 5e18/cm3~3e19/cm3。
Enhanced GaN base power device of the invention has the advantages that due to existing between p-type and AlGaN
Biggish conduction band is poor, and electronics needs, which cross bigger potential barrier, to transit to AlGaN from p-type, so as to effectively press down
Make reverse-biased grid leak electricity.Using p-type as gate electrode, AlGaN/GaN hetero-junctions conduction band difference △ Ec reduces, as shown in fig. 6,
The threshold voltage of device can be effectively improved, to obtain enhanced GaN base power device.In addition, using p-type as grid
Electrode can have higher compatibility with silicon integrated circuit technique.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by those familiar with the art, all answers
It is included within the scope of the present invention.
Claims (10)
1. a kind of enhanced GaN base power device preparation method, which is characterized in that specific steps are as follows:
AlGaN/GaN is as substrate on selection Si；
The source electrode and drain electrode figure of Ohmic contact out, the first metal of electron beam evaporation, by stripping of removing photoresist are exposed over the substrate
From with after annealing, the source electrode and drain electrode of device is formed；
Masking layer is formed, the table top figure of device out, masking layer described in dry etching and the AlGaN layer is exposed and crosses and carve, shape
At device region；
Photoetching, etching form grid opening；
Depositing polysilicon carries out p-type doping and anneals, and photoetching, etching form p-type grid；
The figure of exposed metal lead, the second metal of electron beam evaporation obtain metal lead wire by removing of removing photoresist.
2. enhanced GaN base power device preparation method according to claim 1, which is characterized in that the masking layer is
Si3N4。
3. enhanced GaN base power device preparation method according to claim 1, which is characterized in that the polysilicon
With a thickness of the nm of 100 nm ~ 150.
4. enhanced GaN base power device preparation method according to claim 1, which is characterized in that the p-type
The doping concentration of grid is 5e18/cm3~3e19/cm3。
5. enhanced GaN base power device preparation method according to claim 4, which is characterized in that utilize ion implanting
Or it is 1e that method of diffusion, which carries out dosage to the polysilicon,14/cm2~2e14/cm2, energy be 30keV ~ 35keV B adulterate.
6. enhanced GaN base power device preparation method according to claim 1, which is characterized in that the polysilicon
In 800 DEG C of 30 s of rapid thermal annealing or in 900 DEG C of furnace annealing 5 min ~ 10 min.
7. enhanced GaN base power device preparation method according to claim 1, which is characterized in that described to cross the depth carved
Degree is 5nm ~ 10nm.
8. enhanced GaN base power device preparation method according to claim 1, which is characterized in that first metal
For Au/Ni/Al/Ti, it is followed successively by the Ti layer of 20 ~ 40nm thickness, the Al layer of 120 ~ 150 nm thickness, the Ni of 50 ~ 65nm thickness from bottom to top
The Au layer of layer and 65 ~ 80nm thickness；Second metal is Au/Ni, be followed successively by from bottom to top the Ni layer of 20 ~ 40nm thickness with 60 ~
The Au layer of 90nm thickness.
9. a kind of enhanced GaN base power device that the preparation method as described in one of claim 1-8 obtains, feature exist
In, comprising:
The upper AlGaN/GaN substrate of Si, source electrode, drain and gate；
Wherein, the grid is p-type.
10. enhanced GaN base power device according to claim 9, which is characterized in that the p-type grid are mixed
Miscellaneous concentration is 5e18/cm3~3e19/cm3。
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| CN201811227030.0A CN109545851A (en) | 2018-10-22 | 2018-10-22 | Enhanced GaN base power device and preparation method thereof |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008053436A (en) * | 2006-08-24 | 2008-03-06 | Ngk Insulators Ltd | Semiconductor element |
| CN105977292A (en) * | 2015-03-13 | 2016-09-28 | 株式会社东芝 | Semiconductor device and manufacturing method thereof |
-
2018
- 2018-10-22 CN CN201811227030.0A patent/CN109545851A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008053436A (en) * | 2006-08-24 | 2008-03-06 | Ngk Insulators Ltd | Semiconductor element |
| CN105977292A (en) * | 2015-03-13 | 2016-09-28 | 株式会社东芝 | Semiconductor device and manufacturing method thereof |
Non-Patent Citations (1)
| Title |
|---|
| J. CHEN ET AL: "Poly-Si gate electrodes for AlGaN/GaN HEMT with high reliability and low gate leakage current", 《MICROELECTRONICS RELIABILITY》 * |
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Application publication date: 20190329 |