CN107958928A - A kind of enhancement mode field effect transistor based on lateral channel modulation and preparation method thereof - Google Patents
A kind of enhancement mode field effect transistor based on lateral channel modulation and preparation method thereof Download PDFInfo
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- 230000005669 field effect Effects 0.000 title claims abstract description 15
- 238000002360 preparation method Methods 0.000 title claims description 4
- 239000010410 layer Substances 0.000 claims abstract description 104
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 69
- 238000005036 potential barrier Methods 0.000 claims abstract description 64
- 229910052751 metal Inorganic materials 0.000 claims abstract description 49
- 239000002184 metal Substances 0.000 claims abstract description 49
- 238000002161 passivation Methods 0.000 claims abstract description 40
- 239000002070 nanowire Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000011241 protective layer Substances 0.000 claims abstract description 28
- 230000005611 electricity Effects 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 55
- 238000009616 inductively coupled plasma Methods 0.000 claims description 45
- 238000005530 etching Methods 0.000 claims description 29
- 230000008569 process Effects 0.000 claims description 24
- 238000001259 photo etching Methods 0.000 claims description 17
- 239000007789 gas Substances 0.000 claims description 15
- 238000005566 electron beam evaporation Methods 0.000 claims description 14
- 238000006243 chemical reaction Methods 0.000 claims description 13
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 10
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 9
- 230000000737 periodic effect Effects 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000012545 processing Methods 0.000 claims description 4
- 229910052594 sapphire Inorganic materials 0.000 claims description 4
- 239000010980 sapphire Substances 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 238000001459 lithography Methods 0.000 claims description 3
- -1 oxonium ion Chemical class 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 240000007594 Oryza sativa Species 0.000 claims description 2
- 235000007164 Oryza sativa Nutrition 0.000 claims description 2
- 239000004411 aluminium Substances 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 238000010894 electron beam technology Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims description 2
- 238000002955 isolation Methods 0.000 claims description 2
- 235000012149 noodles Nutrition 0.000 claims description 2
- 235000009566 rice Nutrition 0.000 claims description 2
- 230000002708 enhancing effect Effects 0.000 abstract description 4
- 238000004891 communication Methods 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 35
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 32
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 22
- 239000011248 coating agent Substances 0.000 description 22
- 238000000576 coating method Methods 0.000 description 22
- 229910052757 nitrogen Inorganic materials 0.000 description 16
- 229910021642 ultra pure water Inorganic materials 0.000 description 16
- 239000012498 ultrapure water Substances 0.000 description 16
- 239000003292 glue Substances 0.000 description 14
- 238000004026 adhesive bonding Methods 0.000 description 13
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 12
- 238000001035 drying Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 238000002604 ultrasonography Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 239000008236 heating water Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000001883 metal evaporation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 230000005428 wave function Effects 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 150000002576 ketones Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 238000013517 stratification Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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Abstract
The present invention provides a kind of GaN base enhancement mode field effect transistor based on lateral channel modulation, mainly solves the problems, such as that existing similar device leaks electricity as caused by tunnelling and threshold voltage is insufficient.It includes substrate, AlN nucleating layers, GaN cushions and AlGaN potential barrier from bottom to top; the both ends of AlGaN potential barrier are equipped with source electrode and drain electrode; source electrode and drain electrode is equipped with metal interconnection layer; the a plurality of nanowire channel separated is equipped with AlGaN potential barrier and GaN cushions; AlGaN potential barrier is equipped with groove and the recessed gate electrode perpendicular to nanowire channel; region beyond recessed gate electrode is passivation layer; the SiN passivation layers are equipped with HfO with being equipped with SiN protective layers on recessed gate electrode between groove and recessed gate electrode2Dielectric layer.The present invention greatly reduces electric leakage, improves the enhancing effect of GaN base device, the basic device available for microwave, millimeter wave communication system and radar system.
Description
Technical field
The invention belongs to technical field of semiconductor device, more particularly to a kind of enhanced field effect based on lateral channel modulation
Transistor is answered, can be as the basic device of microwave, millimeter wave communication system and radar system.
Background technology
Semiconductor material with wide forbidden band nitridation is sowed to be become after first generation element half with its good physical chemistry and electric property
The third generation that conductor silicon and second generation arsenide compound semiconductor are transferred, phosphatization is transferred, are developed rapidly after phosphorus phosphide etc. is partly led
Body material.Compared with current most of semi-conducting material, there is big direct band gap energy, high saturation drift velocity, big
Conduction band discontinuity, good heat endurance and strong spontaneous and piezoelectric polarization effect, predictive of it high temperature, high frequency,
It is high-power to wait electronic field that there is great application potential.Wherein, device is respectively provided with microwave high power and high temperature application aspect
Obvious advantage.
In wide band gap semiconducter semi-conducting material, material not only itself has excellent material property, more importantly
It can also form the AlGaN/GaN structures of modulation doping, which can obtain very high electron mobility at room temperature, high
Peak electron speed and saturated electrons speed can simultaneously obtain than second generation compound semiconductor heterojunction device AlGaAs/
The two-dimensional electron gas diffusion of GaAs highers.So high electron mobility transistor (HEMT) based on AlGaN/GaN hetero-junctions
There is extraordinary application prospect in terms of HIGH-POWERED MICROWAVES device.
Oneself shows AlGaN/GaN hetero-junctions high electron mobility transistor in terms of high-temperature device and HIGH-POWERED MICROWAVES device
Advantageous advantage is gone out, has pursued device high-frequency, high pressure, high power and attracted numerous research.HEMT device is according to zero
The working status of device during grid voltage, can be divided into depletion type and enhanced two major class.The device of existing conducting channel when grid voltage is zero
Part, is known as depletion device.The opposite positive grid voltage only when application necessarily could form the device of conducting channel, referred to as strengthen
Type device.Enhancement device has very big usage in high-speed low-power-consumption circuit.
GaN and AlGaN can form hetero-junctions, the formation Quantum Well at hetero-junctions, and the electronics in Quantum Well becomes along different
Matter knot can be with free movement and perpendicular to interface the two-dimensional electron gas that is restricted of movement.Due to two-dimensional electron gas wave function and
Separation on donor impurity wave function space, reduces ionized impurity scattering, so the mobility of two-dimensional electron gas is very high.And
The relative dielectric constant of GaN material is smaller than the relative dielectric constant of Si and GaAs, under identical operating voltage, its junction capacity compared with
Small, along with electron concentration high in hetero-junctions, and high electron mobility, it is very suitable for the application of high-frequency element.
But also it is difficult to realize enhanced just because of high two-dimensional electron gas, traditional GaN base HEMT device, it is impossible to meet high
The requirement of speed, high frequency and low-power consumption modulus hydrid integrated circuit.
The content of the invention
It is an object of the invention in view of the above shortcomings of the prior art, there is provided a kind of GaN based on lateral channel modulation
Base field-effect transistor enhancement device and preparation method thereof, increases the threshold value of device to reduce the leakage current as caused by tunnelling
Voltage, improves the enhancing effect of GaN base device.
Realizing the object of the invention key problem in technology is:Dielectric layer is inserted between groove and grid, to keep grid electricity
While appearance, it is ensured that dielectric layer has enough physical thickness to limit the influence of tunneling effect, while increases the threshold value electricity of device
Pressure, improves the enhancing effect of GaN base device.
A kind of GaN base enhancement mode field effect transistor based on lateral channel modulation of the invention to achieve the above object,
Include substrate, AlN nucleating layers, GaN cushions and AlGaN potential barrier from bottom to top, the both ends of AlGaN potential barrier are equipped with source electrode
And drain electrode, source electrode and drain electrode are equipped with metal interconnection layer, a plurality of receive are equipped with AlGaN potential barrier and GaN cushions
Rice noodles raceway groove, is separated by isolated area between raceway groove, and AlGaN potential barrier is equipped with groove and recessed gate electrode, notched gates electricity
Pole is perpendicular to nanowire channel, it is characterised in that：HfO2 dielectric layers are equipped between groove and recessed gate electrode.
A kind of enhanced field effect transistor of GaN base based on lateral channel modulation of making of the invention to achieve the above object
The method of pipe, including：
1) epitaxial substrate containing substrate, AlN nucleating layers, GaN cushions and AlGaN potential barrier is obtained, and is delayed in its GaN
Rush and source electrode and drain electrode is made on layer；
2) make the electric isolution domain of active area between device by lithography in AlGaN potential barrier, and utilize inductive couple plasma
Body etches the electrically isolated area of ICP techniques or ion implanting making devices；
3) on AlGaN potential barrier surface, with the active area between electron beam litho machine photoetching source electrode and drain electrode, formed by bar
Shape isolated area figure and strip nanowire channel figure press the pattern of periodic arrangement；
4) inductively coupled plasma etching ICP techniques are utilized using inductively coupled plasma etching, isolated area bar graph
Two-dimensional electron gas channel in shape carves disconnected, the nanowire channel of one periodic arrangement of formation；
5) in the AlGaN potential barrier of source electrode, drain electrode and active area, plasma enhanced chemical vapor deposition is utilized
Pecvd process grows SiN passivation layers；
6) photoetching will make the region of groove grid on SiN passivation layers, and use ICP techniques, using CF4 gases to the area
SiN passivation layers in domain perform etching；
7) in the region of the SiN passivation layers etched away, AlGaN potential barrier is etched by 5nm using Cl2 gas using ICP methods
~15nm, forms groove；
8) ICP techniques are used, AlGaN potential barrier is aoxidized using oxygen plasma,
9) sputtering technology dielectric layer deposited HfO2 is utilized on groove；
10) on groove dielectric layer grid is made using electron beam evaporation process；
11) on the SiN passivation layers beyond gate electrode and gate electrode region, SiN protective layers are given birth to using pecvd process；
12) the photoetching metal interconnection aperture area on SiN protective layers, and interconnection aperture area is sequentially etched using ICP techniques
SiN protective layers and SiN passivation layers；
13) in metal interconnection aperture area and non-aperture area photolithographic interconnection region, and electron beam evaporation process system is utilized
Make interconnection metal, draw source electrode and drain electrode, complete element manufacturing.
The present invention, can be while grid capacitance be kept, it is ensured that medium due to being inserted into dielectric layer between groove and grid
Layer has enough physical thickness to limit the influence of tunneling effect, while increases the threshold voltage of device, improves GaN base device
The enhancing effect of part.
Brief description of the drawings
Fig. 1 is the vertical stratification figure of device of the present invention；
Fig. 2 is AlGaN potential barrier and the nanowire channel period profile figure on GaN cushions in Fig. 1；
Fig. 3 is the side sectional view of Fig. 1；
Fig. 4 is the process flow chart for making device of the present invention.
Specific embodiment
The present invention is described in detail referring to the drawings.
With reference to Fig. 1, Fig. 2 and Fig. 3, device of the present invention includes:Substrate 1, AlN nucleating layers 2, GaN cushions 3, AlGaN potential barriers
Layer 4, source electrode 5, drain electrode 6, SiN passivation layers 7, HfO2Dielectric layer 8, recessed gate electrode 9, SiN protective layers 10, metal interconnection layer
11st, nanowire channel 12, trench isolation regions 13 and groove 14.Wherein
Substrate 1 uses SiC or sapphire or Si, its thickness is 400 μm~500 μm；The thickness of AlN nucleating layers 2 is
The thickness of 180nm, GaN cushion 3 be 1.3 μm~2 μm, the AlN nucleating layers 2 and 3 extension of GaN cushions on substrate 1, as
The workspace of device；The thickness of AlGaN potential barrier 4 is 22nm~27nm, and aluminium component is 22%~30%, it is deposited on GaN and delays
Rush on layer 3；A plurality of 12 width of nanowire channel is 50nm~120nm, it is located in AlGaN potential barrier and GaN cushions, raceway groove
Between by width be 100nm, depth separates for 60nm~100nm isolated areas 13；Source electrode 5 is arranged on AlGaN with drain electrode 6
The both ends of barrier layer, spacing between the two is 2 μm, and the spacing of source electrode 5 and recessed gate electrode 9 is 0.5 μm, metal interconnection layer
11 are located in the source electrode and drain electrode；14 depth of groove is located in AlGaN potential barrier for 5nm~15nm；HfO2Dielectric layer 8
Thickness is 20nm, it is arranged between groove 14 and recessed gate electrode 9；The length of recessed gate electrode 9 is 0.25 μm, it uses T
Type structure, the horizontal stripe grid of the T-type structure are located at the lower part of SiN protective layers 10, and vertical bar gate electrode is by HfO2Dielectric layer 8 wraps up；It is blunt
It is 60nm to change 7 thickness of layer, it is passivated beyond recessed gate electrode；The thickness of SiN protective layers 10 is 200nm, it is located at SiN passivation
On layer 7 and recessed gate electrode 9.
With reference to Fig. 4, the present invention makes the technique stream of the GaN base enhancement mode field effect transistor based on lateral channel modulation
Journey, technique, different nanowire channel width and depth, different oxygen plasma oxidation works are electrically isolated according to different active areas
Skill, provides following three kinds of embodiments：
The present invention is that the GaN base enhancement device based on lateral channel modulation is made on existing epitaxial substrate, existing
Epitaxial substrate has different substrates, thereon including AlN nucleating layers, GaN cushions and AlGaN potential barrier.
Embodiment one, it is 60nm, width 50nm to make nano wire electricity isolated region depth on the epitaxial substrate of SiC substrate
Based on lateral channel modulation GaN base enhancement device.
Step 1, it is that source electrode and leakage are made on 1.3 μm in the GaN buffer layer thicknesses of 400 μm of SiC substrate epitaxial substrate
Electrode, such as Fig. 4 (a).
1a) photoetching source electrode region and drain regions in AlGaN potential barrier：
First, SiC substrate epitaxial substrate is placed on 200 DEG C of hot plate and toasts 5min；
Then, thick in 22nm, Al components are the gluing and whirl coating for carrying out peeling off glue in 22% AlGaN potential barrier, it gets rid of
Glue thickness is 0.35 μm, and sample is placed on 200 DEG C of hot plate and toasts 5min；
Then, the gluing and whirl coating of photoresist are carried out on glue is peeled off, its whirl coating thickness is 0.77 μm, and sample is placed on
1min is toasted on 90 DEG C of hot plate；
Afterwards, the sample for completing gluing and whirl coating is put into litho machine, by ohm layer domain to source electrode region and
Photoresist in drain regions is exposed；
Finally, the sample for completing exposure is put into the photoresist removed in developer solution in source electrode region and drain regions
With peel off glue, and it is carried out ultrapure water and nitrogen drying；
1b) in the AlGaN potential barrier in source electrode region and drain regions and source electrode region and drain regions
Vaporing source electrode and drain electrode on overseas photoresist：
First, the sample of active electrode and drain electrode litho pattern is put into progress counterdie processing in plasma degumming machine,
Its time handled is 5min；
Then, sample is put into electron beam evaporation platform, treat that the reaction chamber vacuum of electron beam evaporation platform reaches 2 ×
In AlGaN potential barrier after 10-6Torr in 10 region of source electrode and drain regions and source electrode region and drain electrode
Ohmic metal is evaporated on photoresist outside region, which is bottom-up successively by tetra- layers of metal group of Ti, Al, Ni and Au
Into metal stack structure；
Then, the sample for completing ohmic metal evaporation is peeled off, it is overseas to remove source electrode region and drain regions
Ohmic metal, photoresist and peel off glue；
Finally, dried up with ultrapure water sample and with nitrogen；
1c) ohmic metal makes annealing treatment：The sample completed ohmic metal evaporation and peeled off is put into rapid thermal anneler
Made annealing treatment, so that the ohmic metal of AlGaN potential barrier sinks down into GaN cushions in source electrode and drain electrode region, from
And the Ohmic contact between ohmic metal and hetero-junctions raceway groove is formed, its process conditions annealed is：Annealing atmosphere is N2, annealing
Temperature is 830 DEG C, annealing time 30s.
Step 2, the electrically isolated area of source region is carved with AlGaN potential barrier glazing, utilizes ICP technique making devices active areas
Electric isolution, such as Fig. 4 (b).
2a) the photoetching electrically isolated area in AlGaN potential barrier：
First, sample is placed on 200 DEG C of hot plate and toasts 5min；
Then, the gluing and whirl coating of photoresist are carried out, its whirl coating rotating speed is 3500 turns/min, and sample is placed on 90 DEG C
1min is toasted on hot plate；
Then, sample is put into litho machine, the photoresist in electrically isolated area is exposed by mesa-isolated domain
Light；
Finally, the sample after exposing will be completed to be put into remove the photoresist in electrically isolated area in developer solution, and to it
Carry out ultrapure water and nitrogen drying；
Electrically isolated area 2b) is etched in AlGaN potential barrier：
First, the AlGaN potential barrier and GaN epitaxial layer of electrically isolated area are sequentially etched using ICP techniques, it is active to realize
The mesa-isolated in area, its total etching depth are 100nm；
Then, sample is sequentially placed into acetone soln, stripper, acetone soln and ethanol solution and is cleaned, to move
Except the overseas photoresist of electricity isolated region；
Finally, dried up with ultrapure water sample and with nitrogen.
Step 3, the active area between source electrode, drain electrode is etched into periodic arrangement and from each other two dimension using ICP
The nanowire channel that electron gas is mutually not turned on, such as Fig. 4 (c).
3a) the isolated area in AlGaN potential barrier between photoetching nanowire channel：
First, sample is placed on 200 DEG C of hot plate and toasts 5min, then carry out the gluing and whirl coating of photoresist, its whirl coating
Thickness is 2 μm, and sample is placed on 90 DEG C of hot plate and toasts 1min,
Then, it is right in beamwriter lithography machine sample to be put into, by nanowire channel field-effect transistor domain to nanometer
The photoresist of electricity isolated region is exposed between wire channel；
Finally, the sample after exposing will be completed to be put into remove the photoresist in electrically isolated area in developer solution, and to it
Carry out ultrapure water and nitrogen drying；
3b) using the AlGaN potential barrier and GaN cushions of the electrically isolated area between ICP etching nanowire channels, with reality
Electric isolution between existing nanowire channel, its etching depth is 60nm, and etching width is 50nm；Then sample is sequentially placed into third
Cleaned in ketone solution, stripper, acetone soln and ethanol solution, to remove the overseas photoresist of electricity isolated region；Finally use
Ultrapure water sample is simultaneously dried up with nitrogen.
Step 4, in the AlGaN potential barrier of source electrode, drain electrode and nanowire channel, SiN is grown using pecvd process
Passivation layer, such as Fig. 4 (d).
Sample 4a) being electrically isolated to completing active area carries out surface clean：
First, sample is put into acetone soln and is cleaned by ultrasonic 3min, its ultrasound intensity is 3.0；
Then, sample is put into heating water bath 5min in the stripper that temperature is 60 DEG C；
Then, sample is sequentially placed into acetone soln and ethanol solution and is cleaned by ultrasonic 3min, its ultrasound intensity is 3.0；
Finally, dried up with ultrapure water sample and with nitrogen；
4b) in the AlGaN potential barrier of source electrode, drain electrode and nanowire channel, it is using pecvd process growth thickness
The SiN passivation layers of 60nm, the process conditions of its growth are：Using NH3 and SiH4 as reacting gas, underlayer temperature is 250 DEG C,
Reaction chamber pressure is 600mTorr, and RF power is 22W.
Step 5, in SiN passivation layer glazing flutings region, and the SiN in the patterned area is passivated using ICP techniques
Layer and part AlGaN potential barrier perform etching.
5a) in SiN passivation layer glazing flutings region：
First, sample is placed on 200 DEG C of hot plate and toasts 5min；
Then, the gluing and whirl coating of photoresist are carried out, its whirl coating rotating speed is 3500 turns/min, and sample is placed on 90 DEG C
1min is toasted on hot plate；
Then, sample is put into litho machine, the photoresist of recess region is exposed by groove domain；
Finally, the sample after exposure will be completed to be put into developer solution to remove the photoresist in recess region, and to its into
Row ultrapure water and nitrogen drying；
The SiN passivation layers in recess region 5b) are removed using ICP etching technics, its condition etched is：Reacting gas is
The radio-frequency power of CF4 and O2, reaction chamber pressure 10mTorr, top electrode and bottom electrode is respectively 100W and 10W, etching
Depth is 60nm to AlGaN potential barrier.
A part of AlGaN potential barrier in recess region 5c) is removed using ICP etching technics, etches away AlGaN potential barrier
5nm, its condition etched are：Reacting gas is Cl2, reaction chamber pressure 5mTorr, the radio frequency work(of top electrode and bottom electrode
Rate is respectively 100W and 10W.
The vertical bar region of T-shaped notched gates is formed by this step.
Step 6, by ICP techniques, the AlGaN potential barrier under groove is aoxidized using oxonium ion, its chamber pressure
For 5mTorr, oxygen flow 5sccm, top electrode and lower electrode power are respectively 300W and 0W.
Step 7, in the horizontal stripe region of SiN passivation layer glazing fluting grid, in the horizontal stripe region of notched gates and notched gates
Horizontal stripe region outside photoresist on sputtering technology HfO is deposited on groove2Film, such as Fig. 4 (e).
Step 8, in HfO2Recessed gate electrode is made using electron beam evaporation process on dielectric layer, such as Fig. 4 (f).
8a) in the horizontal stripe region of SiN passivation layer glazing fluting grid：
First, the sample etched is placed on 200 DEG C of hot plate and toasts 5min；
Then, carrying out peeling off the gluing and whirl coating of glue on SiN passivation layers, its whirl coating thickness is 0.35 μm, and by sample
It is placed on 200 DEG C of hot plate and toasts 5min；
Then, the gluing and whirl coating of photoresist are carried out on glue is peeled off, its whirl coating thickness is 0.77 μm, and sample is placed on
1min is toasted on 90 DEG C of hot plate；
Afterwards, the sample for completing gluing and whirl coating is put into litho machine, the horizontal stripe region by grid domain to notched gates
Photoresist be exposed；
Finally, photoresist and the stripping sample for completing exposure being put into the horizontal stripe region that notched gates are removed in developer solution
Glue, and ultrapure water and nitrogen drying are carried out to it；
8b) gate electrode is evaporated on the photoresist in the horizontal stripe region of notched gates and outside the horizontal stripe region of notched gates：
First, sample is put into progress counterdie processing in plasma degumming machine, its time handled is 5min；
Then, sample is put into electron beam evaporation platform, treat that the reaction chamber vacuum of electron beam evaporation platform reaches 2 ×
After 10-6Torr, grid metal is evaporated on the photoresist in the horizontal stripe region of notched gates and outside the horizontal stripe region of notched gates, should
Grid metal is the metal stack structure being made of successively Ni, Au and Ni three-layer metal from bottom to top；
Then, the sample for completing notched gates evaporation of metal is peeled off, to remove the grid outside the horizontal stripe region of notched gates
Metal, photoresist and stripping glue；
Finally, dried up with ultrapure water sample and with nitrogen.
By by the vertical bar region that above-mentioned 5th step is formed with the horizontal stripe region that above-mentioned 7th step is formed be combined form it is T-shaped
Grid.
Step 9, on the SiN passivation layers on recessed gate electrode and beyond recessed gate electrode region, given birth to using pecvd process
Long SiN protective layers, such as Fig. 4 (g).
Sample 9a) made to completing recessed gate electrode carries out surface clean：
First, sample is put into acetone soln and is cleaned by ultrasonic 3min, its ultrasound intensity is 3.0；
Then, sample is put into heating water bath 5min in the stripper that temperature is 60 DEG C；
Then, sample is sequentially placed into acetone soln and ethanol solution and is cleaned by ultrasonic 3min, its ultrasound intensity is 3.0；
Finally, dried up with ultrapure water sample and with nitrogen；
9b) on the SiN passivation layers on recessed gate electrode and beyond recessed gate electrode region, grown using pecvd process
Thickness is the SiN protective layers of 200nm, and the process conditions of its growth are：Using NH3 and SiH4 as reacting gas, underlayer temperature
For 250 DEG C, reaction chamber pressure 600mTorr, radio-frequency power 22W.
Step 10, the photoetching metal interconnection layer aperture area on SiN protective layers, and interconnection is sequentially etched using ICP techniques
SiN protective layers, the SiN passivation layers of aperture area.
10a) the photoetching metal interconnection layer aperture area on SiN protective layers：
First, sample is placed on 200 DEG C of hot plate and toasts 5min；
Then, the gluing and whirl coating of photoresist are carried out, its whirl coating rotating speed is 3500 turns/min, and sample is placed on 90 DEG C
1min is toasted on hot plate；
Then, sample is put into litho machine, by interconnecting perforate domain to the photoetching in metal interconnection layer opening area
Glue is exposed；
Finally, the sample after exposing will be completed to be put into remove the photoresist in interconnection opening area in developer solution, and it is right
It carries out ultrapure water and nitrogen drying；
Be 10b) CF4 and O2 in reacting gas using ICP etching technics, reaction chamber pressure 10mTorr, top electrode with
The radio-frequency power of bottom electrode is respectively the SiN guarantors of the 200nm thickness in first removal interconnection opening area under conditions of 100W and 10W
Sheath, then etch away the SiN passivation layers of 60nm thickness.
Step 11, on the SiN protective layers that the source electrode and drain electrode of metal interconnection layer aperture area and non-perforate etch
Photolithographic interconnection layer region, and metal interconnection layer is made using electron beam evaporation process, for drawing source electrode and drain electrode,
Such as Fig. 4 (h).
11a) the photoetching on the SiN protective layers that the source electrode and drain electrode of metal interconnection layer aperture area and non-perforate etch
Metal interconnection layer region：
First, the sample for completing metal interconnection layer perforate etching is placed on 200 DEG C of hot plate and toasts 5min；
Then, it is enterprising in the SiN protective layers of the source electrode and drain electrode of metal interconnection layer aperture area and non-perforate etching
Row peels off the gluing and whirl coating of glue, its whirl coating thickness is 0.35 μm, and sample is placed on 200 DEG C of hot plate and toasts 5min；
Then, the gluing and whirl coating of photoresist are carried out on glue is peeled off, its whirl coating thickness is 0.77 μm, and sample is placed on
1min is toasted on 90 DEG C of hot plate；
Afterwards, the sample for completing gluing and whirl coating is put into litho machine and the photoresist in metal interconnection area is exposed
Light；
Finally, the sample for completing exposure is put into photoresist and the stripping removed in developer solution in metal interconnection layer region
Glue, and ultrapure water and nitrogen drying are carried out to it；
11b) evaporated on the photoresist outside the electrode in metal interconnection area and SiN protective layers and metal interconnection area
Metal interconnects：
First, the sample for having metal interconnection litho pattern is put into progress counterdie processing in plasma degumming machine, it is handled
Time be 5min；
Then, sample is put into electron beam evaporation platform, treat that the reaction chamber vacuum of electron beam evaporation platform reaches 2 ×
Evaporated on electrode after 10-6Torr in interconnection metallic region and the photoresist outside SiN protective layers and metal interconnection area
Metal is interconnected, which is the metal stack structure being made of successively Ti and Au double layer of metal from bottom to top；
Then, the sample for completing interconnection evaporation of metal is peeled off, to remove the gold of the interconnection outside metal interconnection layer region
Category, photoresist and stripping glue；
Finally, dried up with ultrapure water sample and with nitrogen, complete element manufacturing.
Embodiment two, it is 80nm to make nano wire electricity isolated region depth on the epitaxial substrate of Sapphire Substrate, and width is
The GaN base enhancement device based on lateral channel modulation of 80nm.
Step 1, is to be made on 1.6 μm in the GaN buffer layer thicknesses for the Sapphire Substrate epitaxial substrate that thickness is 450 μm
Source electrode and drain electrode.
The specific implementation of this step is identical with the step 1 in example one.
Step 2, is 25nm in thickness, Al components are that 26% AlGaN potential barrier glazing is carved with the electricity isolated region of source region
Domain, utilizes the electric isolution of ICP technique making devices active areas.
The specific implementation of this step is identical with the step 2 in example one.
Step 3, using ICP dry etchings the active area between source electrode, drain electrode be etched into periodic arrangement and mutually
Between the nanowire channel that is mutually not turned on of two-dimensional electron gas.
3.1) in AlGaN potential barrier photoetching nanowire channel isolated area：
The specific implementation of this step and the step 3a in example one) it is identical：
3.2) AlGaN potential barrier and GaN cushions of the electrically isolated area between nanowire channel are etched using ICP, with
Realize the electric isolution between nanowire channel, its etching depth is 80nm, and etching width is 80nm, is then sequentially placed into sample
Cleaned in acetone soln, stripper, acetone soln and ethanol solution, to remove the overseas photoresist of electricity isolated region, finally
Dried up with ultrapure water sample and with nitrogen.
Step 4, in the AlGaN potential barrier of source electrode, drain electrode and nanowire channel, is grown using pecvd process
SiN passivation layers.
The specific implementation of this step is identical with the step 4 in example one.
Step 5, is passivated the SiN in the patterned area in SiN passivation layer glazing flutings region, and using ICP techniques
Layer and part AlGaN potential barrier perform etching.
5.1) in SiN passivation layer glazing flutings region：
The specific implementation of this step and the step 5a in example one) it is identical；
5.2) the SiN passivation layers in recess region are removed using ICP etching technics；
The specific implementation of this step and the step 5b in example one) it is identical；
5.3) a part of AlGaN potential barrier in recess region is removed using ICP etching technics, AlGaN potential barrier is carved
Eating away 20nm, its condition etched are：Reacting gas is Cl2, reaction chamber pressure 5mTorr, and top electrode and bottom electrode are penetrated
Frequency power is respectively 100W and 10W.
Step 6, by ICP techniques, using the AlGaN potential barrier of oxonium ion oxidation recess region, its chamber pressure is：
7mTorr, oxygen flow are：12sccm, top electrode and lower electrode power a point ratio are 300W and 0W.
Step 7, in the horizontal stripe region of SiN passivation layer glazing fluting grid, in the horizontal stripe region of notched gates and notched gates
Horizontal stripe region outside photoresist on sputtering technology HfO is deposited on groove2Film
The specific implementation of this step is identical with the step 7 in example one.
Step 8, in HfO2On dielectric layer recessed gate electrode is made using electron beam evaporation process.
The specific implementation of this step is identical with the step 8 in example one.
Step 9, with the SiN passivation layers beyond recessed gate electrode region on recessed gate electrode, utilizes pecvd process
Grow SiN protective layers.
The specific implementation of this step is identical with the step 9 in example one.
Step 10, the photoetching metal interconnection layer aperture area on SiN protective layers, and it is sequentially etched interconnection using ICP techniques
SiN protective layers, the SiN passivation layers of aperture area.
The specific implementation of this step is identical with the step 10 in example one.
Step 11, in the SiN protective layers that the source electrode and drain electrode of metal interconnection layer aperture area and non-perforate etch
Upper photoetching metal interconnection layer region, and metal interconnection layer is made using electron beam evaporation process, for drawing source electrode and electric leakage
Pole, completes element manufacturing.
The specific implementation of this step is identical with the step 11 in example one.
Embodiment three, it is 100nm to make nano wire electricity isolated region depth on the epitaxial substrate of Si substrates, and width is
The GaN base enhancement device based on lateral channel modulation of 120nm.
Step A, the GaN buffer layer thicknesses for the Si substrate epitaxial substrates that thickness is 500 μm be on 2 μm make source electrode and
Drain electrode.
The specific implementation of this step is identical with the step 1 in example one；
Step B, is 28nm in thickness, and Al components are that 30% AlGaN potential barrier glazing is carved with the electrically isolated area of source region,
Utilize the electric isolution of ICP technique making devices active areas.
The specific implementation of this step is identical with the step 2 in example one.
Step C, using ICP dry etchings the active area between source electrode, drain electrode be etched into periodic arrangement and mutually
Between the nanowire channel that is mutually not turned on of two-dimensional electron gas.
C1) in AlGaN potential barrier photoetching nanowire channel isolated area：
The specific implementation of this step and the step 3a in example one) it is identical：
C2) using the AlGaN potential barrier and GaN cushions of the electrically isolated area between ICP etching nanowire channels, with reality
Electric isolution between existing nanowire channel, its etching depth is 100nm, and etching width is 120nm, is then sequentially placed into sample
Cleaned in acetone soln, stripper, acetone soln and ethanol solution, to remove the overseas photoresist of electricity isolated region, finally
Dried up with ultrapure water sample and with nitrogen.
Step D, in the AlGaN potential barrier of source electrode, drain electrode and nanowire channel, grows SiN using pecvd process
Passivation layer.
The specific implementation of this step is identical with the step 4 in example one.
Step E, is passivated the SiN in the patterned area in SiN passivation layer glazing flutings region, and using ICP techniques
Layer and part AlGaN potential barrier perform etching.
E1) in SiN passivation layer glazing flutings region：
The specific implementation of this step and the step 5a in example one) it is identical；
E2 the SiN passivation layers in recess region) are removed using ICP etching technics；
The specific implementation of this step and the step 5b in example one) it is identical；
E3 a part of AlGaN potential barrier in recess region) is removed using ICP etching technics, AlGaN potential barrier is etched
Fall 15nm, its condition etched is：Reacting gas is Cl2, reaction chamber pressure 5mTorr, the radio frequency of top electrode and bottom electrode
Power is respectively 100W and 10W.
Step F, by ICP techniques, using the AlGaN potential barrier of oxonium ion oxidation recess region, its chamber pressure is：
10mTorr, oxygen flow are：25sccm, top electrode and lower electrode power a point ratio are 300W and 0W.
With sputtering technology recessed on photoresists of the step G in the horizontal stripe region of notched gates and outside the horizontal stripe region of notched gates
HfO is deposited on groove2Film
Step H, groove is made in the horizontal stripe region of SiN passivation layer glazing fluting grid, and using electron beam evaporation process
Gate electrode.
The specific implementation of this step is identical with the step 7 in example one.
Step I, with the SiN passivation layers beyond recessed gate electrode region on recessed gate electrode, is given birth to using pecvd process
Long SiN protective layers.
The specific implementation of this step is identical with the step 8 in example one.
Step J, the photoetching metal interconnection layer aperture area on SiN protective layers, and be sequentially etched interconnection using ICP techniques and open
SiN protective layers, the SiN passivation layers of porose area.
The specific implementation of this step is identical with the step 9 in example one.
Step K, in the SiN protective layer glazings that the source electrode and drain electrode of metal interconnection layer aperture area and non-perforate etch
Metal interconnection layer region is carved, and metal interconnection layer is made using electron beam evaporation process, it is complete for drawing source electrode and drain electrode
Into element manufacturing.
The specific implementation of this step is identical with the step 10 in example one.
Above description is only three instantiations of the present invention, does not form any limitation of the invention, it is clear that for
, all may be without departing substantially from the principle of the invention, structure after present invention and principle has been understood for one of skill in the art
In the case of, the various modifications and variations in progress form and details, but these modifications and variations based on inventive concept
Still within the claims of the present invention.
Claims (10)
1. it is a kind of based on lateral channel modulation GaN base enhancement mode field effect transistor, from bottom to top including substrate (1), AlN into
Stratum nucleare (2), GaN cushions (3) and AlGaN potential barrier (4), the both ends of AlGaN potential barrier (4) are equipped with source electrode (5) and electric leakage
Pole (6), source electrode and drain electrode are equipped with metal interconnection layer (11), a plurality of receive are equipped with AlGaN potential barrier and GaN cushions
Rice noodles raceway groove (12), is separated between raceway groove, AlGaN potential barrier is equipped with groove (14) and recessed gate electrode by isolated area (13)
(9), region of the recessed gate electrode beyond nanowire channel, recessed gate electrode is passivation layer (7), the SiN passivation layers
With being equipped with SiN protective layers (10) on recessed gate electrode, it is characterised in that：HfO is equipped between groove and recessed gate electrode2Medium
Layer (8).
2. the GaN base enhancement mode field effect transistor according to claim 1 based on lateral channel modulation, its feature exist
In：HfO2The nanowire channel (12) that dielectric layer (8) is wrapped in AlGaN potential barrier (4) is exterior.
3. the GaN base enhancement mode field effect transistor according to claim 1 based on lateral channel modulation, its feature exist
In：Recessed gate electrode (9) uses T-type structure, and the horizontal stripe grid of the T-type structure are located at the lower part of SiN protective layers (10), notched gates electricity
It is down extremely HfO2Dielectric layer (8).
4. the GaN base enhancement mode field effect transistor according to claim 1 based on lateral channel modulation, its feature exist
In：
The thickness of substrate (1) is 400 μm~500 μm；
The thickness of AlN nucleating layers (2) is 180nm；
The thickness of GaN cushions (3) is 1.3 μm~2 μm,
The thickness of AlGaN potential barrier (4) is 22nm~27nm, and aluminium component is 22%~30%；
The width of nanowire channel (12) is 50nm~120nm；
The width of trench isolation regions (13) is 100nm, and depth is 60nm~100nm；
The thickness of SiN passivation layers (7) is 60nm；
The thickness of SiN protective layers (10) is 200nm；
HfO2Dielectric layer (8) thickness is 20nm,
The length of recessed gate electrode (9) is 0.25 μm.
5. the GaN base enhancement mode field effect transistor based on lateral channel modulation according to claim (1), its feature exist
In：Spacing between source electrode (5) and drain electrode (6) is 2 μm；Source electrode (5) and the spacing of recessed gate electrode (9) are 0.5 μm.
6. the GaN base enhancement mode field effect transistor according to claim 1 based on lateral channel modulation, its feature exist
In：Substrate (1) uses SiC or sapphire or Si.
7. a kind of preparation method of the GaN base enhancement device based on lateral channel modulation of oxonium ion processing notched gates, including
Following steps：
1) epitaxial substrate containing substrate, AlN nucleating layers, GaN cushions and AlGaN potential barrier is obtained, and in its GaN cushion
Upper making source electrode and drain electrode；
2) make the electric isolution domain of active area between device by lithography in AlGaN potential barrier, and carved using inductively coupled plasma
Lose the electrically isolated area of ICP techniques or ion implanting making devices；
3) on AlGaN potential barrier surface, with the active area between electron beam litho machine photoetching source electrode and drain electrode, formed by strip every
From the pattern that area's figure and strip nanowire channel figure press periodic arrangement；
4) inductively coupled plasma etching ICP techniques are utilized using inductively coupled plasma etching, in isolated area flagpole pattern
Two-dimensional electron gas channel carve disconnected, form the nanowire channel of a periodic arrangement；
5) in the AlGaN potential barrier of source electrode, drain electrode and active area, plasma enhanced chemical vapor deposition PECVD works are utilized
Skill grows SiN passivation layers；
6) photoetching will make the region of groove grid on SiN passivation layers, and use ICP techniques, use CF4Gas is in the region
SiN passivation layers perform etching；
7) in the region of the SiN passivation layers etched away, Cl is used using ICP methods2Gas by AlGaN potential barrier etch 5nm~
15nm, forms groove；
8) ICP techniques are used, AlGaN potential barrier is aoxidized using oxygen plasma,
9) sputtering technology dielectric layer deposited HfO is utilized on groove2；
10) on groove dielectric layer grid is made using electron beam evaporation process；
11) on the SiN passivation layers beyond gate electrode and gate electrode region, SiN protective layers are grown using pecvd process；
12) the photoetching metal interconnection aperture area on SiN protective layers, and it is sequentially etched using ICP techniques the SiN of interconnection aperture area
Protective layer and SiN passivation layers；
13) in metal interconnection aperture area and non-aperture area photolithographic interconnection region, and made mutually using electron beam evaporation process
Join metal, draw source electrode and drain electrode, complete element manufacturing.
8. according to the method described in claim 7, wherein step 2), 4) and 7) in utilize inductively coupled plasma ICP etchings
Technique etches AlGaN potential barrier and GaN cushions, its process conditions are as follows：
Reacting gas is Cl2,
Cl2Flow is 25sccm
Reaction chamber pressure is 5mTorr
The radio-frequency power of top electrode and bottom electrode is respectively 100W and 10W.
9. according to the method described in claim 7, wherein carved in step 6) and step 11) using inductively coupled plasma ICP
Etching technique etches SiN passivation layers and SiN protective layers, its process conditions are as follows：
Reacting gas is CF4And O2,
CF4Flow is 25sccm,
O2Flow is 5sccm,
Reaction chamber pressure is 10mTorr,
The radio-frequency power of top electrode and bottom electrode is respectively 100W and 10W.
10. according to the method described in claim 7, the ICP methods wherein in step 7), its process conditions are as follows：
Reacting gas is O2,
O2 flow 5sccm~25sccm,
Reaction chamber pressure is 5mTorr~10mTorr,
The radio-frequency power of top electrode and bottom electrode is respectively 300W and 0W.
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| CN108899366A (en) * | 2018-06-11 | 2018-11-27 | 西安电子科技大学 | A kind of enhancement device and preparation method thereof of novel P-GaN grid structure |
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| CN106887454A (en) * | 2017-03-14 | 2017-06-23 | 西安电子科技大学 | GaN base fin grid enhancement device and preparation method thereof |
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| CN106887454A (en) * | 2017-03-14 | 2017-06-23 | 西安电子科技大学 | GaN base fin grid enhancement device and preparation method thereof |
| CN107316901A (en) * | 2017-07-10 | 2017-11-03 | 西安电子科技大学 | Based on doping HfO2The enhanced HEMT devices of AlGaN/GaN and preparation method of ferroelectricity gate medium |
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| CN108899366A (en) * | 2018-06-11 | 2018-11-27 | 西安电子科技大学 | A kind of enhancement device and preparation method thereof of novel P-GaN grid structure |
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| CN109411349A (en) * | 2018-09-10 | 2019-03-01 | 西安电子科技大学 | A kind of High Linear millimetric wave device based on the modulation of charge branch |
| CN109977531A (en) * | 2019-03-20 | 2019-07-05 | 天津工业大学 | A kind of domain structure of the standard block for digital integrated electronic circuit |
| CN113939917A (en) * | 2019-06-17 | 2022-01-14 | 苏州晶湛半导体有限公司 | Semiconductor structure and manufacturing method thereof |
| CN113299734A (en) * | 2021-04-19 | 2021-08-24 | 厦门市三安集成电路有限公司 | Gallium nitride transistor device and preparation method thereof |
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Application publication date: 20180424 |