CN107393959A - GaN hyperfrequencies device and preparation method based on sag - Google Patents

GaN hyperfrequencies device and preparation method based on sag Download PDF

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Publication number
CN107393959A
CN107393959A CN201710549494.2A CN201710549494A CN107393959A CN 107393959 A CN107393959 A CN 107393959A CN 201710549494 A CN201710549494 A CN 201710549494A CN 107393959 A CN107393959 A CN 107393959A
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grid
potential barrier
electrode
layer
gan
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马晓华
郝跃
武盛
宓珉瀚
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Xidian University
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Xidian University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Abstract

The invention discloses a kind of high-gain hyperfrequency GaN device and preparation method thereof, mainly solves the problems, such as that existing similar device frequency, gain and power conversion efficiency are low.The device includes substrate (1) from bottom to top, AlN nucleating layers (2), GaN cushions (3), AlN insert layers (4), AlGaN potential barrier (5) passivation layer (7), the both ends of GaN cushions are provided with source electrode (8) and drain electrode (9), source electrode and drain electrode are provided with metal interconnection layer (11), wherein the top of AlGaN potential barrier is provided with self aligned step-like double-T shaped gate electrode (10), the grid pin (101) of gate electrode is provided with groove, gate dielectric layer (6) is provided with above groove, passivation layer is located at the potential barrier layer surface of gate electrode grid pin both sides.Present invention decreases electric leakage of the grid and parasitic capacitance, it is suppressed that current collapse, improves the power conversion efficiency, frequency and gain characteristic of device, can be used as high-gain hyperfrequency device.

Description

GaN hyperfrequencies device and preparation method based on sag
Technical field
The invention belongs to microelectronics technology, more particularly to a kind of high-gain hyperfrequency device, available for communicate, satellite In navigation, radar system and base station system.
Background technology
Progressive with science and technology is lifted, and existing first and second generation semiconductor devices can not meet higher frequency, higher The demand of the technical field of communication development of power, more low-power consumption, new wide bandgap compound semiconductor material GaN, must help it Broad stopband width, high breakdown electric field, and higher thermal conductivity, and a series of silicon-based semiconductor materials such as corrosion-resistant, radioresistance Not available good characteristic, it can dramatically meet the growth requirement of Nowadays communication technology, substantially increase device Can so that the third generation semi-conducting material using GaN as representative has in the manufacture of microwave and millimeter wave device to be widely applied.Into After twentieth century nineties, due to the breakthrough of p-type doping techniques and the introducing of nucleating layer technology so that GaN material obtains soon The development of speed.GaN material can form the heterojunction structure of the types such as AlGaN/GaN, InAlN/GaN, and this kind of heterojunction structure is in room Temperature is lower to obtain very high electron mobility, and high peak electron speed and saturated electrons speed, while spontaneous polarization Effect makes the two-dimensional electron gas of its acquisition also higher than second generation compound semiconductor hetero-junctions.These features have established nitrogen Compound semiconductor HEMT is led in the high-power of microwave and millimeter wave frequency range, high efficiency, wide bandwidth, low noise etc. Domain surmounts rapidly GaAs based hemts and InP-base HEMT inexorable trend.
However, in order to adapt to ever-increasing working frequency, current main flow way is continuous reduction Gate length and source and drain Spacing, it is very low that this results in its operating voltage, substantially defeated not out of high-power, while in order to pursue high-frequency, device is typically all Passivation is not introduced into so as to reduce parasitic capacitance, potential barrier layer surface does not have passivation to be easy to that current collapse effect occurs, so as to serious Influence the output of device power and the lifting of efficiency.
At present, at home and in the world, mainly include etched recesses under grid and, to improve grid-control ability, gate medium is added under grid To reduce electric leakage, surface introduces passivation layer to suppress current collapse, and these methods include：
Jinwook W.Chung in 2010 et al. are in " JAlGaN/GaN HEMT With 300-GHz fmax.IEEE Employ in ELECTRON DEVICE LETTERS, VOL.31, NO.3, MARCH 2010. " and grown with molecular beam epitaxy (MBE) SiC substrate on, AlGaN/GaN heterojunction structures are grown, using inductively coupled plasma etching ICP technologies in AlGaN layer Position and ohm source-drain area position etched recesses under Schottky gate, employ size and be 1.1 μm of source and drain spacing, and be prepared for 60nm T-shaped grid, finally give fT/fmax=70/300GHz device, its mutual conductance are 410mS/mm, and maximum drain current is 1.2A/mm, ON resistance are 1.1~1.2 Ω mm, and drain-source resistance is 95.7 Ω mm, breakdown voltage 20V.
2013, D.Denninghoff et al. was in " N-polar GaN/InAlN/AlGaN MIS-HEMTs with 1.89S/mm extrinsic transconductance,4A/mm drain current,204GHz fT and 405GHz fmax.IEEE, proposing a kind of mutual conductance in 2013. " is up to 1.89S/mm, and leakage current density is up to 4A/mm, and ON resistance is 0.23 Ω mm depletion type n faces GaN/AlGaN/InAlN-MISHEMT devices.The device uses T-shaped slot grid structure, and grid are a length of 70nm, fTAnd fmax204GHz and 405GHz are respectively reached.
2013, S.Bouzid-Driad et al. was in " AlGaN/GaN HEMTs on Silicon Substrate With One is proposed in 206-GHz FMAX.IEEE ELECTRON DEVICE LETTERS, VOL.34, NO.1, JANUARY 2013. " Kind deposits the thick SiNx passivation films of one layer of 50nm using plasma-reinforced chemical vapor deposition PECVD under the grid wing, utilizes electricity Three layers of anti-etching glue of beamlet photoetching expose the grid of 90nm length, and AlGaN/GaN-HEMT devices are prepared on H-R Si substrates, The drain saturation current for finally giving device is 1.03A/mm, mutual conductance 440mS/mm, fTAnd fmaxRespectively reached 100GHz and 206GHz。
In summary, currently, the making of millimeter wave GaN base device is all to be etched under grid using dry etching in the world Go out grid recess to improve grid-control ability, or one layer of gate medium is deposited to reduce electric leakage and suppress current collapse under grid, and or In abarrier layer material surface passivation layer of sinXMethod so as to improve the power conversion efficiency of device, but these methods there is also Following deficiency：
First, when device carries out etched recesses under grid, because common method is unstable, etched recesses side wall is frequently resulted in Extend out and etching precision is difficult to control, reduce the confinement of grid pin, reduce output current, influence device gain, cause on piece Device uniformity is bad；
Second, conventional T-shaped grid and grid it is recessed it is groove etched adhere to two processing steps separately, this is carried to two step alignment precisions Go out very high requirement, preparation method yield rate is not high；
Third, deposit SiO under device gate2After gate medium, the parasitic capacitance of MIS structure can not only make device frequency special Sexual involution, and reduce with the equal proportion of device size, SiO2It is thinned can cause Gate control ability and device voltage endurance capability be cured Hair dies down, and leaks electricity also than more serious；
Fourth, the passivation technology introduced in device surface, passivation layer thickness is not easy to control, blocked up, can introduce excessive post Raw electric capacity, causes device frequency performance degradation.
The content of the invention
It is an object of the invention to for above-mentioned the deficiencies in the prior art, propose a kind of high-gain hyperfrequency device and making Method, to improve grid-control ability, reduce electric leakage of the grid, improve device gain；Reduce parasitic gate electric capacity and grid source gate-drain parasitic Electric capacity, improve device frequency characteristic；Suppress current collapse under high frequency, improve device power transformation efficiency.
To achieve the above object, hyperfrequency sag GaN device of the invention, from bottom to top including substrate 1, AlN into Stratum nucleare 2, GaN cushions 3, AlN insert layers 4, AlGaN potential barrier 5 and passivation layer 7, the both ends of GaN cushions 3 are provided with source electrode 8 With drain electrode 9, source electrode 8 and drain electrode 9 are provided with metal interconnection layer 11, it is characterised in that region under the grid of AlGaN potential barrier 5 Provided with groove, gate dielectric layer 6 is introduced in groove, to improve grid-control ability, device gain is improved and suppressor grid electric leakage is reduced and closed State is leaked electricity；The top of gate dielectric layer 6 is provided with gate electrode 10, and thin passivation layer 7 is located at the potential barrier layer surface outside the region of grid pin 101, To suppress current collapse, the power conversion efficiency of device is improved.
To achieve the above object, high-gain hyperfrequency GaN device technique of the present invention, comprises the following steps：
1) substrate 1, AlN nucleating layers 2, GaN cushions 3, AlN insert layers 4, the epitaxial base of AlGaN potential barrier 5 are being included successively Source electrode and drain electrode are made on the GaN cushions of piece；
2) electrically isolated area of source region is carved with AlGaN potential barrier glazing, utilizes inductively coupled plasma etching ICP techniques Or the electric isolution of ion implantation technology making devices active area；
3) photoetching grid pin width is 60nm~90nm in AlGaN potential barrier 5, grid neck height 160nm~200nm, grid Cap width is the 360nm~540nm T-shaped grid structure of autoregistration；
4) 5nm~12nm depth is etched to the AlGaN potential barrier 5 in T-shaped grid grid pin region using ICP techniques；
5) plasma oxidation is carried out in T-shaped grid low groove, it is 4nm~8nm gate dielectric layers 6 to form thickness；
6) electron beam evaporation process is utilized, evaporation grid metal makes gate electrode 10 in gate electrode figure area；
7) Low Temperature Plasma Treating for 60 DEG C of the sample surfaces progress that gate electrode makes is completed, is forming 2nm~6nm's Thin layer passivation layer 7；
8) in sample surfaces photolithographic interconnection layer region, metal interconnection layer 11 is made using electron beam evaporation process, is used In drawing source electrode 8 and drain electrode 9, element manufacturing is completed.
The present invention has the following advantages that compared with prior art：
1. the present invention directly carries out recess etch and corona treatment to the T-shaped grid patterned area of autoregistration so that groove, Gate dielectric layer and step-like double-T shaped gate electrode are among a T-shaped gate region, realize the autoregistration of three technique, are eliminated The error of conventional alignment process, improve the yield rate of device fabrication process.
2. the recess etch of the invention for AlGaN potential barrier under grid 5 become air pressure, and other region AlGaN potential barriers 5 Keep original thickness constant, so can both reach the accurate etching of depth of groove, can improve grid-control ability again, improve and move Device output current is not reduced also while shifting rate and raising mutual conductance, ensures device power conversion efficiency.
3. the present invention carries out autoregistration N to recess etch region2O corona treatments, technique is simple, the high-k of formation Medium A l2O3As Gate dielectric layers 6, it so can both suppress the electric leakage of the grid caused by recess etch and increase, can prevent again Device size, which reduces caused voltage endurance capability, to be reduced, and so as to reduce the quiescent dissipation of device, improves device efficiency.
4. the present invention carries out N to the surface of AlGaN potential barrier 52O Low Temperature Plasma Treating, form thin Al2O3Passivation Layer 7, preferably suppresses current collapse, Al2O3Thickness compare conventional SiNxPassivation layer reduces more than an order of magnitude, effectively drop Low parasitic gate electric capacity, improve device frequency characteristic.
Brief description of the drawings
Fig. 1 is the device cross-section schematic diagram of the present invention；
Fig. 2 is the Making programme schematic diagram of device of the present invention.
Embodiment
Reference picture 1, high-gain hyperfrequency GaN device of the invention, from bottom to top successively include substrate 1, AlN nucleating layers 2, GaN cushions 3, AlN insert layers 4, AlGaN potential barrier 5, gate dielectric layer 6 and passivation layer 7, the both ends of GaN cushions 3 are provided with source Groove structure is carved with electrode 8 and drain electrode 9, the surface of AlGaN potential barrier 5, and to improve device grid-control ability, gate dielectric layer is located at 6 In groove, being leaked electricity with suppressor grid reduces OFF state electric leakage, improves the power conversion efficiency of device, the top of gate medium 6 is provided with grid Electrode 10, source electrode 8 and drain electrode 9 are provided with metal interconnection layer 11.
The substrate 1 uses insulating sapphire or Si or SiC substrate of the thickness for 400 μm~500 μm, the thickness of AlN nucleating layers 2 It is 1.5 μm~2 μm to spend for 180nm, the thickness of GaN cushions 3；The thickness of AlN insert layers 4 is 1nm；The thickness of AlGaN potential barrier 5 For 20nm~25nm, aluminium component is 20%~30%, and the length of grid pin 101 of the gate electrode 10 on its surface is 60nm~90nm, The height of grid neck 102 is 160nm~200nm, and the width of grid cover 103 is 360nm~540nm；The groove of the part of Gate pin 101 is deep Spend for 5nm~12nm, the thickness of the gate dielectric layer 6 above groove is 4~8nm；The thickness of the passivation layer 7 of the both sides of Gate pin 101 is 2 ~6nm.
Reference picture 2, the present invention make high-gain hyperfrequency GaN device structure, according to different backing materials, different have Source region is electrically isolated technique and different gate dielectric layer thickness, provides following three kinds of embodiments.
The original material that the present invention makes laminated gate medium GaN base insulation gate transistor with high electron mobility is the outer of purchase Epitaxial substrate, the epitaxial substrate include substrate 1, AlN nucleating layers 2, GaN cushions 3, the and of AlN insert layers 4 successively from bottom to top AlGaN potential barrier 5, such as Fig. 2 (a).
Embodiment one, makes on sic substrates, depth of groove 5nm, gate dielectric layer thickness 4nm, passivation layer thickness 2nm, grid Neck is highly 160nm high-gain hyperfrequency GaN device structure.
Step 1, source electrode 8 and drain electrode 9 are made on the GaN cushions 3 of epitaxial substrate, such as Fig. 2 (b).
1a) photoetching source electrode figure and drain electrode patterns in AlGaN potential barrier 5：
1a-1) epitaxial substrate is placed on 200 DEG C of hot plate and toasts 5min, substrate moisture is removed to dry；
1a-2) carry out peeling off glue PMGI-SF6 gluing and whirl coating in AlGaN potential barrier 5, under 2000rpm rotating speeds its Whirl coating thickness is about 350nm, and the sample of formation is placed on 200 DEG C of hot plate and toasts 5min；
Photoresist EPI621 gluing and whirl coating, its whirl coating thickness under 5000rpm rotating speeds 1a-3) are carried out on glue is peeled off For 770nm, then sample is placed on 90 DEG C of hot plate and toasts 1min；
1a-4) sample for completing gluing and whirl coating is put into stepper to source electrode region and drain regions Interior photoresist is exposed intensity and exposed for 240ms；
The sample for completing exposure 1a-5) is put into developer solution about 85s, in source electrode region to be removed and drain regions Double-deck glue after, it is rinsed using ultra-pure water and dried up using nitrogen；
1b) the patterned area evaporated metal using electron beam evaporation to electrode, makes electrode：
The sample of active electrode and drain electrode litho pattern 1b-1) is put into progress counterdie processing in plasma degumming machine, Its time handled is 5min；
1b-2) sample is put on electron beam evaporation platform, is 2 × 10 in reaction chamber vacuum-6It is right under conditions of Torr Substrate surface is integrally evaporated metal, and metal-layer structure is the gold for evaporating tetra- layers of metal of Ti, Al, Ni and Au successively from bottom to top Belong to stack architecture, whereinIn source electrode graphics field and drain electrode patterns region Metal be ohmic metal；
Stripping technology 1b-3) is carried out to the sample for completing ohmic metal evaporation, is sequentially placed into acetone soln, stripper, third Cleaned in ketone solution and ethanol solution, with remove the ohmic metal outside source electrode graphics field and drain electrode patterns region, Photoresist and stripping glue；
1b-4) dried up with ultrapure water sample and with nitrogen；
Quick thermal annealing process 1c) is carried out to sample：
The sample completed ohmic metal evaporation and peeled off is put into rapid thermal anneler, in N2840 DEG C are carried out under environment 30s quick thermal annealing process, to cause the ohmic metal in source electrode figure and drain electrode patterns region in AlGaN potential barrier 5 Electrode sags, so as to form Ohmic contact between ohmic metal and heterojunction semiconductor raceway groove, complete source to GaN cushions 3 The making of electrode 8 and drain electrode 9.
Step 2, the electrically isolated area of source region is carved with the glazing of AlGaN potential barrier 5, and is had using ICP technique making devices The electric isolution of source region.
2a) the photoetching electrically isolated area in AlGaN potential barrier 5：
2a-1) sample is placed on 200 DEG C of hot plate and first toasts 5min；
The whirl coating that rotating speed is 3500rpm 2a-2) is carried out to anti-etching photoresist EPI621 in sample surfaces, forming thickness is 400nm glue-line, and sample is placed on 90 DEG C of hot plate and toasts 1min；
2a-3) sample is put into stepper the photoresist in electrically isolated area is exposed, exposure intensity For 260ms；
The sample after exposing 2a-4) will be completed and be put into 60s in developer solution EPD1000, to remove the light in electrically isolated area Photoresist, ultrapure water and nitrogen drying are carried out to it；
2b) photoresist perforate electrically isolated area carries out inductive couple plasma ICP etchings in AlGaN potential barrier 5：
2b-1) using ICP techniques with SF6For etching gas, AlGaN potential barrier 5, the AlN of electrically isolated area are sequentially etched Insert layer 4 and GaN epitaxial layer 3, the two-dimensional electron gas 2DEG of sample is carved and broken, to realize the mesa-isolated of device active region, its Total etching depth is 120nm, and etching power is 80W, and etch period is about 120s；
2b-2) sample is sequentially placed into acetone soln, stripper, acetone soln and ethanol solution and cleaned, to move Except the overseas photoresist of electricity isolated region；
2b-3) dried up with ultrapure water sample and with nitrogen.
Step 3, the T-shaped grid structure of photoetching autoregistration in AlGaN potential barrier 5, such as Fig. 2 (c).
The whirl coating of T-shaped tri- layers of photoresists of Gate 3a) is carried out in sample surfaces：
3a-1) sample is placed on 200 DEG C of hot plate and toasts 5min；
The whirl coating that rotating speed is 4000rpm 3a-2) is carried out to anti-etching electron beam resist PMMA679.03 in sample surfaces, The bottom glue-line that thickness is about 160nm is formed, and sample is placed on 180 DEG C of hot plate and toasts 2min；
3a-3) it is to peeling off glue PMGI-SF6 progress rotating speeds on anti-etching electron beam resist PMMA679.03 surfaces 2000rpm whirl coating, the intermediate gelatine layer that thickness is about 350nm is formed, and sample is placed on 200 DEG C of hot plate and toasts 5min；
3a-4) carrying out rotating speed to anti-etching electron beam resist AR6200.13 on stripping glue PMGI-SF6 surfaces is 4000rpm whirl coating, the top glue-line that thickness is about 400nm is formed, and sample is placed on 150 DEG C of hot plate and toasts 1min；
3b) sample for completing whirl coating is put into beamwriter lithography machine EBL to the photoetching in the T-shaped grid target area of autoregistration Glue carries out subregion high contrast exposure, and the wherein width in grid pin region is 60nm, positioned at the grid cover region at grid pin region both ends Width is 120nm, grid pin region and grid cover it is interregional every 30nm to compensate the kindred effect of electronics art photoetching；
The sample after exposing 3c) will be completed to be sequentially placed into developer solution corresponding to two kinds to remove the photoetching in recess region Glue, i.e., the sample for completing exposure is first put into developer solution AR600-546 the 90s that develops, then put it into when being carried out in isopropanol Between be 30s fixing processing, putting it into developer solution MIBK afterwards：IPA=1:Develop what 4min developed completely to reach in 3 Effect, isopropanol immersion and nitrogen drying are finally carried out to it.
Step 4, the AlGaN potential barrier 5 in the region of grid pin 101 is performed etching using ICP techniques it is thinned, such as Fig. 2 (d).
Using ICP etching technics with BCl3The AlGaN potential barrier 5 in grid pin region, the depth of etching are removed for etching gas Spend for 5nm, upper electrode power 100W, lower electrode power 8W, BCl3Flow 25sccm, pressure 5mT, etching power are 40W, etching Time is about 10s.
Step 5, in the AlGaN potential barrier 5 in T-shaped grid grid underfooting side recess region, gate dielectric layer 6 is grown, such as Fig. 2 (e)。
Sample is put into chemical plasma enhancing chemical vapor deposition PECVD device, is 100W, N in power2O flows For 100sccm, N2Flow is 100sccm, pressure 600mTorr, under conditions of temperature is 60 DEG C, to the AlGaN of recess region Barrier layer 5 carries out the laughing gas N that the time is 20min2O oxidation processes, form the thick Al of 4nm2O3As gate dielectric layer 6；
Step 6, on gate dielectric layer 6, gate electrode 10 is made using electron beam evaporation process, such as Fig. 2 (f).
The sample for having gate electrode litho pattern 6a) is subjected to counterdie processing：
The sample for having gate electrode litho pattern is put into progress counterdie processing in plasma degumming machine, its power is 200W, O2Flow is 50sccm, operating time 1min；
6b) electron beam evaporation is carried out in the sample surfaces for completing counterdie processing：
Sample is put into electron beam evaporation platform, is 2 × 10 in reaction chamber vacuum-6To substrate table under conditions of Torr Face is integrally evaporated grid metal, and the grid metal is the metal stack being made up of successively Ni, Au and Ni three-layer metal from bottom to top Structure, whereinGate dielectric layers 6 and the Gate metals of photoresist exposure area are the grid of device Electrode 10；
6c) sample for completing grid metal evaporation is peeled off：
6c-1) sample is sequentially placed into acetone soln, stripper, acetone soln and ethanol solution and cleaned, to move Except the overseas photoresist of electricity isolated region；
6c-2) dried up with ultrapure water sample and with nitrogen, complete stripping technology.
Step 7, in the AlGaN potential barrier 5 outside Gate electrode Gate pin region, plasma treatment is carried out using PECVD device Passivation layer 7 is formed, such as Fig. 2 (g).
Sample is put into chemical plasma enhancing chemical vapor deposition PECVD device, is 200W, N in power2O flows For 100sccm, N2Flow is 100sccm, pressure 600mTorr, under conditions of temperature is 60 DEG C, to Gate electrode Gate pin region Outer AlGaN potential barrier 5 carries out the laughing gas N that the time is 8min2O Passivation Treatments, form the thick passivation layers 7 of 2nm.
Step 8, metal interconnection layer 11 is made using electron beam evaporation process, element manufacturing is completed, such as Fig. 2 (h).
8a) the photoetching metal interconnection region in the source electrode 8 of metal interconnection aperture area and drain electrode 9：
8a-1) sample for completing metal interconnection perforate etching is placed on 200 DEG C of hot plate and toasts 5min；
8a-2) carry out peeling off glue PMGI-SF6 gluing in the source electrode 8 of metal interconnection aperture area and drain electrode 9 and get rid of Glue, it is 350nm that it peels off glue thickness under rotating speed 4500rpm, and sample is placed on 200 DEG C of hot plate and toasts 5min；
Photoresist EPI621 gluing and whirl coating 8a-3) is carried out on glue is peeled off, its photoresist under rotating speed 5000rpm is thick Spend for 770nm, and sample is placed on 90 DEG C of hot plate and toasts 1min；
8a-4) sample for completing gluing and whirl coating is put into stepper to the photoresist in metal interconnection region It is exposed；
The sample for completing exposure 8a-5) is put into the photoresist removed in developer solution in metal interconnection region and peels off glue, And ultrapure water and nitrogen drying are carried out to it；
8b) evaporated metal on the photoresist on the electrode in metal interconnection region and outside metal interconnection region：
8b-1) sample for having metal interconnection litho pattern is put into plasma degumming machine and carries out counterdie under vacuum conditions Processing, its power is 200W, O2Flow is 50sccm, processing time 5min；
8b-2) sample is put into electron beam evaporation platform, is 2 × 10 in reaction chamber vacuum-6It is right under conditions of Torr Substrate surface is integrally evaporated interconnection metal, wherein, the interconnection metal is to be successively from bottom to top by thicknessTi and Thickness isAu composition metal stack structure, the metal in metal interconnection region is metal interconnection layer 11；
8b-3) sample for completing to interconnect evaporation of metal is peeled off, to remove the gold of the interconnection outside metal interconnection layer region Category, photoresist and stripping glue；
8b-4) dried up with ultrapure water sample and with nitrogen, complete the preparation of device.
Embodiment two, depth of groove 12nm, gate dielectric layer thickness 4nm, passivation layer thickness 2nm height are made on a si substrate Gain hyperfrequency GaN device structure.
Step 1, source electrode 8 and drain electrode 9 are made on the GaN cushions 3 of epitaxial substrate, such as Fig. 2 (b).
1.1) photoetching source electrode figure and drain electrode patterns in AlGaN potential barrier 5：
The specific implementation of this step and the step 1a in embodiment one) it is identical；
1.2) the patterned area evaporated metal using electron beam evaporation to electrode, makes electrode：
The specific implementation of this step and the step 1b in embodiment one) it is identical；
1.3) quick thermal annealing process is carried out to sample：
The sample completed ohmic metal evaporation and peeled off is put into rapid thermal anneler, in N2830 DEG C are carried out under environment 30s quick thermal annealing process, to cause the ohmic metal in source electrode figure and drain electrode patterns region in AlGaN potential barrier 5 Electrode sags are to GaN cushions 3, and so as to form Ohmic contact between ohmic metal and heterojunction semiconductor raceway groove, it is annealed Process conditions be：Annealing atmosphere is N2, annealing temperature is 830 DEG C, annealing time 30s, completes source electrode 8 and drain electrode 9 Making.
Step 2, the electrically isolated area of source region is carved with the glazing of AlGaN potential barrier 5, utilizes ion implantation technology maker The electric isolution of part active area.
2.1) the photoetching electrically isolated area in AlGaN potential barrier 5：
The specific implementation of this step and the step 2a in embodiment one) it is identical；
2.2) photoresist perforate electrically isolated area carries out inductive couple plasma ICP etchings in AlGaN potential barrier 5：
2.2.1) AlGaN potential barrier 5 of N ion implantings to electrically isolated area, AlN are inserted successively using ion implantation technology Enter layer 4 and GaN epitaxial layer 3, to realize the electric isolution of active area, its depth injected is 120nm；
2.2.2) sample is sequentially placed into acetone soln, stripper, acetone soln and ethanol solution and cleaned, to move Except the overseas photoresist of electricity isolated region；
2.2.3) dried up with ultrapure water sample and with nitrogen.
Step 3, the T-shaped grid structure of photoetching autoregistration in AlGaN potential barrier 5, such as Fig. 2 (c).
3.1) gluing and whirl coating of T-shaped tri- layers of photoresists of Gate are carried out：
The specific implementation of this step and the step 3a in embodiment one) it is identical；
3.2) the T-shaped grid target area of autoregistration is exposed using beamwriter lithography machine EBL：
The specific implementation of this step and the step 3b in embodiment one) it is identical；
3.3) sample after exposing will be completed to be developed：
The specific implementation of this step and the step 3c in embodiment one) it is identical.
Step 4, the AlGaN potential barrier 5 in the region of grid pin 101 is performed etching it is thinned, such as Fig. 2 (d).
Using ICP etching technics with BCl3The AlGaN potential barrier 5 in grid pin region, the depth of etching are removed for etching gas Spend for 12nm, upper electrode power 100W, lower electrode power 8W, BCl3Flow 25sccm, pressure 5mT, etching power are 40W, are carved It is about 24s to lose the time.
Step 5, in the AlGaN potential barrier 5 in the T-shaped grid low groove region of autoregistration, gate dielectric layer 6 is grown, such as Fig. 2 (e)。
The specific implementation of this step is identical with the step 5 in embodiment one.
Step 6, on gate dielectric layer 6, gate electrode 10 is made using electron beam evaporation process, such as Fig. 2 (f).
6.1) litho pattern for having gate electrode region is subjected to counterdie processing：
The specific implementation of this step and the step 6a in embodiment one) it is identical；
6.2) electron beam evaporation is carried out in sample surfaces：
The specific implementation of this step and the step 6b in embodiment one) it is identical；
6c) sample for completing grid metal evaporation is peeled off：
The specific implementation of this step and the step 6c in embodiment one) it is identical.
Step 7, in AlGaN potential barrier 5, carry out plasma treatment using PECVD device and form passivation layer 7, such as Fig. 2 (g)。
The specific implementation of this step is identical with the step 7 in embodiment one.
Step 8, metal interconnection layer 11 is made using electron beam evaporation process, element manufacturing is completed, such as Fig. 2 (h).
8a) the photoetching metal interconnection layer region in the source electrode 8 of metal interconnection layer aperture area and drain electrode 9：
The specific implementation of this step and the step 8a in embodiment one) it is identical.
8b) interconnection metal is evaporated on the electrode in metal interconnection region and the photoresist outside metal interconnection region：
The specific implementation of this step and the step 8b in embodiment one) it is identical.
Embodiment three, makes on a sapphire substrate, depth of groove 12nm, gate dielectric layer thickness 8nm, passivation layer thickness 6nm high-gain hyperfrequency GaN device structure.
Step A, source electrode 8 and drain electrode 9 are made on the GaN cushions 3 of epitaxial substrate, such as Fig. 2 (b).
A-1) photoetching source electrode figure and drain electrode patterns on AGaN barrier layers 5：
The specific implementation of this step and the step 1a in embodiment one) it is identical；
A-2) in the AlGaN potential barrier 5 in source electrode region and drain regions and source electrode region and drain electrode Region
Vaporing source electrode 8 and drain electrode 9 on outer photoresist：
The specific implementation of this step and the step 1b in embodiment one) it is identical；
A-3 quick thermal annealing process) is carried out to sample：
The specific implementation of this step is identical with the step 2.3) in embodiment two.
Step B, the electrically isolated area of source region is carved with the glazing of AlGaN potential barrier 5, utilizes ion implantation technology making devices The electric isolution of active area：
B-1) the photoetching electrically isolated area in AlGaN potential barrier 5：
The specific implementation of this step and the step 2a in embodiment one) it is identical；
B-2) photoresist perforate electrically isolated area carries out inductive couple plasma ICP etchings in AlGaN potential barrier 5：
The specific implementation of this step is identical with the step 2.2) in embodiment two.
Step C, the T-shaped grid structure of photoetching autoregistration in AlGaN potential barrier 5, such as Fig. 2 (c).
C-1 the gluing and whirl coating of T-shaped tri- layers of photoresists of Gate) are carried out：
The specific implementation of this step and the step 3a in embodiment one) it is identical；
C-2) the T-shaped grid target area of autoregistration is exposed using beamwriter lithography machine EBL：
The specific implementation of this step and the step 3b in embodiment one) it is identical；
C-3 the sample after exposing) will be completed to be developed：
The specific implementation of this step and the step 3c in embodiment one) it is identical.
Step D, the AlGaN potential barrier 5 in the region of grid pin 101 is performed etching it is thinned, such as Fig. 2 (d).
The specific implementation of this step is identical with the step four in embodiment two.
Step E, in the AlGaN potential barrier 5 in the T-shaped grid low groove region of autoregistration, gate dielectric layer 6 is grown, such as Fig. 2 (e)。
Sample is put into chemical plasma enhancing chemical vapor deposition PECVD device, to the AlGaN potential barriers of recess region Layer 5 carries out laughing gas N2The processing of O plasma oxidations, power 100W, N2O flows 100sccm, N2Flow 100sccm, pressure 600mTorr, temperature 60 C, time 40min, form the thick Al of 8nm2O3As gate dielectric layer 6.
Step F, on gate dielectric layer 6, gate electrode 10 is made using electron beam evaporation process, such as Fig. 2 (f).
On gate dielectric layer 6, gate electrode 10 is made using electron beam evaporation process.
F-1 gate electrode region litho pattern) will carries out counterdie processing：
The specific implementation of this step and the step 6a in embodiment one) it is identical；
F-2) electron beam evaporation is carried out in sample surfaces：
The specific implementation of this step and the step 6b in embodiment one) it is identical；
F-3) sample for completing grid metal evaporation is peeled off：
The specific implementation of this step and the step 6c in embodiment one) it is identical.
Step G, in AlGaN potential barrier 5, carry out plasma treatment using PECVD device and form passivation layer 7, such as Fig. 2 (g)。
Sample is put into chemical plasma enhancing chemical vapor deposition PECVD device, AlGaN potential barrier 5 is laughed at Gas N2O Passivation Treatments, power 200W, N2O flows 100sccm, N2Flow 100sccm, pressure 600mTorr, temperature 60 C, time 24min, form the thick passivation layers 7 of 6nm.
Step H, metal interconnection layer 11 is made using electron beam evaporation process, element manufacturing is completed, such as Fig. 2 (h).
H-1) the photoetching metal interconnection region in the source electrode 8 of metal interconnection layer aperture area and drain electrode 9：
The specific implementation of this step and the step 8a in embodiment one) it is identical；
H-2) interconnection metal is evaporated on the electrode in metal interconnection region and the photoresist outside metal interconnection region：
The specific implementation of this step and the step 8b in embodiment one) it is identical.
Above description is only three instantiations of the present invention, does not form any limitation of the invention, it is clear that for , all may be without departing substantially from the principle of the invention, structure after present invention and principle has been understood for one of skill in the art In the case of, the various modifications and variations in progress form and details, but these modifications and variations based on inventive concept Still within the claims of the present invention.

Claims (10)

  1. A kind of 1. hyperfrequency sag GaN device, from bottom to top including substrate (1), AlN nucleating layers (2), GaN cushions (3), AlN insert layers (4), AlGaN potential barrier (5) passivation layer (7), the both ends of GaN cushions (3) are provided with source electrode (8) and leakage Electrode (9), source electrode (8) and drain electrode (9) are provided with metal interconnection layer (11), it is characterised in that AlGaN potential barrier (5) it is upper Side is provided with self aligned step-like double-T shaped gate electrode (10), and the grid pin (101) of gate electrode (10) is provided with groove, to improve device Grid-control ability, mutual conductance and mobility, so as to improve device gain；Gate dielectric layer (6) is provided with above groove, is leaked electricity with suppressor grid Reduce OFF state electric leakage；Passivation layer (7) is located at the potential barrier layer surface of gate electrode grid pin both sides to suppress current collapse, further improves Device gain.
  2. 2. device according to claim 1, it is characterised in that the thickness of passivation layer (7) is 2~6nm.
  3. 3. device according to claim 1, it is characterised in that：
    Grid pin (101) length of gate electrode (10) litho pattern is 60nm~90nm, the height of grid neck (102) for 160nm~ 200nm, the width of grid cover (103) is 360nm~540nm；
    The recess width of grid pin (101) part is 60nm~90nm, and depth is 5nm~12nm.
  4. 4. device according to claim 1, it is characterised in that the thickness of gate dielectric layer (6) is 4nm~8nm.
  5. 5. device according to claim 1, it is characterised in that the thickness of AlGaN potential barrier (5) is 20nm~25nm.
  6. 6. device according to claim 1, it is characterised in that substrate (1) uses SiC or sapphire or Si substrates.
  7. 7. a kind of hyperfrequency sag GaN device structure, its making step are as follows：
    1) delay in the GaN successively including substrate, AlN nucleating layers, GaN cushions, AlN insert layers, AlGaN potential barrier epitaxial substrate Rush and source electrode and drain electrode are made on layer；
    2) electrically isolated area of source region is carved with AlGaN potential barrier glazing, using inductively coupled plasma etching ICP techniques or from The electric isolution of sub- injection technology making devices active area；
    3) photoetching grid pin width is 60nm~90nm in AlGaN potential barrier, grid neck height 160nm~200nm, grid cover width For the 360nm~540nm T-shaped grid structure of autoregistration；
    4) groove using ICP techniques to the AlGaN potential barrier etching depth in T-shaped grid grid pin region for 5nm~12nm；
    5) plasma oxidation is carried out in T-shaped grid low groove, it is 4nm~8nm gate dielectric layers to form thickness；
    6) electron beam evaporation process is utilized, evaporation grid metal makes gate electrode in gate electrode figure area；
    7) Low Temperature Plasma Treating for 60 DEG C of the sample surfaces progress that gate electrode makes is completed, is forming 2nm~6nm thin layer Passivation layer；
    8) in sample surfaces photolithographic interconnection layer region, metal interconnecting layer is made using electron beam evaporation process, for drawing Source electrode and drain electrode, complete element manufacturing.
  8. 8. according to the method for claim 8, wherein step 4) further groove etch technological condition is as follows：
    Etching gas：Flow 25sccm ± 2sccm BCl3,
    Upper electrode power：100W, lower electrode power：8W；
    Time：2min；
    Chamber pressure：≤5mT；
    Reaction chamber temperature：30℃±0.5℃.
  9. 9. the work of plasma oxidation according to the method for claim 8, is carried out wherein in step 5) in T-shaped grid low groove Skill condition is as follows：
    N2O flows：100sccm ± 5sccm, N2Flow：100sccm±5sccm；
    Power：100W；
    Pressure：≤600mTorr；
    Temperature：60℃±0.5℃.
  10. 10. according to the method for claim 8, wherein low-temperature passivation process conditions are as follows in step 7)：
    N2O flows：100sccm ± 5sccm, N2Flow：100sccm±5sccm；
    Power：200W；
    Pressure：≤600mTorr；
    Temperature：60℃±0.5℃.
CN201710549494.2A 2017-07-07 2017-07-07 GaN hyperfrequencies device and preparation method based on sag Pending CN107393959A (en)

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CN114883193A (en) * 2022-07-06 2022-08-09 江苏第三代半导体研究院有限公司 Enhanced HEMT device with stacked gate dielectric layers and preparation method thereof

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Application publication date: 20171124