CN112968059B - Novel enhancement mode gaN HEMT device structure - Google Patents

Novel enhancement mode gaN HEMT device structure Download PDF

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CN112968059B
CN112968059B CN202110154220.XA CN202110154220A CN112968059B CN 112968059 B CN112968059 B CN 112968059B CN 202110154220 A CN202110154220 A CN 202110154220A CN 112968059 B CN112968059 B CN 112968059B
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gan
gate
etching
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CN112968059A (en
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翁加付
周炳
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Ningbo Haitechuang Electronic Control Co ltd
Guilin University of Technology
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Ningbo Haitechuang Electronic Control Co ltd
Guilin University of Technology
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Abstract

The invention provides a novel enhanced GaN HEMT device structure which is prepared by the following steps: epitaxial growth; growing a PN junction gate stack; cleaning the Si-based GaN epitaxial wafer; photoetching and forming an alignment mark; isolating the table top; etching the PN junction laminated layer; source and drain ohmic contacts; depositing a passivation layer; etching the gate groove; depositing gate metal; depositing a protective layer; opening holes and metal interconnection. The PN junction gate type GaN HEMT is designed on the basis of the p-type gate, a layer of n-GaN is added on the p-GaN to form a PN junction, the PN junction is reversely biased when voltage is applied to the gate by utilizing the PN junction, the breakdown voltage Vg of the gate is increased, the gate voltage Vg has large gate voltage swing amplitude, the power switch is very suitable for application, and larger gate driving bias can be obtained to ensure safe operation.

Description

Novel enhancement mode gaN HEMT device structure
Technical Field
The invention relates to the technical field of electronic component manufacturing, in particular to a novel enhanced GaN HEMT (gallium nitride high electron mobility transistor) device structure.
Background
Enhancement mode GaN-based High Electron Mobility Transistor (HEMT) devices are always hot spots in nitride device research, and in several reported mainstream methods for realizing enhancement mode application, p-GaN is used as a gate cap layer, so that the enhancement mode GaN HEMT device technology has great potential in the aspects of interface quality, device on-state characteristics, GaN high-power application and the like, and is widely concerned in recent years.
Although p-GaN gate HEMTs produce forward gate breakdown voltages greater than 10V, the maximum gate bias voltage allowed for long term reliable operation will be significantly reduced due to gate leakage at high electric fields causing degradation of the gate/p-GaN interface. The threshold voltage of the schottky p-GaN gate power HEMT is relatively small in high power switch applications, which in turn puts high requirements on suppressing gate ringing and mis-conduction. Therefore, it is highly desirable to develop a device structure capable of further reducing gate leakage and increasing forward gate breakdown voltage so that a larger gate driving bias can be obtained to ensure safe operation.
Disclosure of Invention
The invention aims to provide a novel enhanced GaN HEMT device structure, which is characterized in that a PN junction gate type GaN HEMT is designed on the basis of a p-type gate, a layer of n-GaN is added on the p-GaN to form a PN junction, the PN junction is reversely biased when grid voltage is applied by utilizing the PN junction, the grid breakdown voltage Vg is increased, the grid voltage swing amplitude is large, the novel enhanced GaN HEMT device structure is very suitable for application of a power switch, and larger grid driving bias can be obtained to ensure safe operation.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a novel enhanced GaN HEMT device structure is prepared by the following steps:
1) and (3) epitaxial growth: respectively growing an AlN nucleating layer, a GaN buffer layer, an AlN inserting layer, an AlGaN barrier layer and a GaN capping layer from bottom to top on a Si substrate through Metal Organic Chemical Vapor Deposition (MOCVD) to form a Si-based GaN epitaxial wafer;
2) growing a PN junction gate stack: growing PN junction gate stack by metal organic chemical vapor deposition, which consists of a p-GaN layer with the thickness of 100nm and an n-GaN layer with the thickness of 30nm from bottom to top, wherein the Mg doping concentration of the p-GaN layer is 3 multiplied by 1019cm-3And the n-GaN layer has a Si doping concentration of 1 × 1019cm-3；
3) Cleaning a Si-based GaN epitaxial wafer: sequentially putting the epitaxial substrate into MOS grade acetone and MOS grade ethanol, performing ultrasonic treatment for 3min, cleaning the sample wafer with flowing deionized water for 2min, and blow-drying with a nitrogen gun; the device is then immersed in HF HCl H2Removing natural oxides on the surface of the solution with the volume ratio of O being 1:4:20 for 1min, then washing the solution for 2min by using deionized water and drying the solution by using a nitrogen gun to finish sample cleaning;
4) photoetching and forming an alignment mark: throwing positive photoresist S9912 to the sample at the rotating speed of 6000 rpm, baking the sample on a hot plate at the temperature of 100 ℃ for 5min, forming a corrosion window through ultraviolet lithography, developing and fixing, and simultaneously forming an alignment mark on the photoresist;
5) isolating the table top: using Reactive Ion Etching (RIE) method with Cl2Dry etching the GaN cap layer, the AlGaN barrier layer, the AlN insert layer and part of the GaN buffer layer as reactive etching gas; etching out two-dimensional electron gas of heterojunction outside the active region to form isolation between active regions of devices；
6) Etching the PN junction laminated layer: throwing positive glue AZ6130 to the sample, the rotating speed is 6000 r/min, and baking on a hot plate at the temperature of 95 ℃ for 2 min; photoetching, developing and fixing the alignment mark for the first time to form a gate electrode window; use of Low Damage BCl3/Cl2Dry etching by a basic Inductively Coupled Plasma (ICP) method to remove the n-GaN/p-GaN laminated layer outside the gate region; then, in N2Annealing at 850 deg.C for 25min in atmosphere to reactivate n-GaN/p-GaN stack at a distance of 3 μm from the source and a gate-source spacing of 15 μm, and a length of 2 μm;
7) source and drain ohmic contacts: throwing positive glue AZ6130 to the sample, the rotating speed is 6000 r/min, and baking on a hot plate at the temperature of 95 ℃ for 2 min; photoetching, developing and fixing the alignment mark in the step 3) to form a source/drain electrode window; then, completing metal stack deposition by adopting electron beam evaporation equipment to form a Ti/Al/Ni/Au metal layer; performing rapid thermal annealing at 850 ℃ for 30s to form an ohmic contact electrode with a source electrode and a drain electrode;
8) deposition of a passivation layer: SiH gas flow rate of 600sccm by Plasma Enhanced Chemical Vapor Deposition (PECVD)41960sccm of N2And NH of 20sccm3As a chemical reaction source, 160nm thick Si is deposited under the conditions that the temperature is 250 ℃, the radio frequency power is 60W, and the pressure of a chamber for plasma enhanced chemical vapor deposition is 500Torr3N4A passivation layer;
9) etching a gate groove: throwing polymethyl methacrylate (PMMA) electron beam glue to the sample, wherein the rotating speed is 2000 r/min, and drying on a hot plate at 180 ℃ for 10 min; exposing a grid groove graph at a position which is 3 mu m away from a source electrode and has a grid-source spacing of 15 mu m by adopting an electron beam, wherein the length of the grid groove graph is 2 mu m; forming a grid groove window through development for 25s and fixation for 5 s; using RIE technique, at 50W power for 2min, by CF4Removing Si in grid region by plasma dry etching3N4A layer forming a gate trench;
10) and (3) gate metal deposition: throwing double-layer electron beam glue to the sample, wherein the lower layer is Copolymer (Copolymer) glue with the rotating speed of 3000 r/min, the hot plate at 150 ℃ is used for baking for 15min, the upper layer is PMMA glue with the rotating speed of 3000 r/min, and the hot plate at 180 ℃ is used for bakingBaking for 10 min; at the position of the gate groove, a gate electrode pattern is etched by adopting electron beam exposure, the size of the gate electrode is set to be 2 mu m, and a gate electrode pattern window is formed by developing for 25s and fixing for 5s after exposure; growing a Ni/Au metal layer on the dielectric layer forming the grid pattern window by adopting an electron beam evaporation method, forming Schottky contact between the Ni/Au metal layer and the dielectric layer, and removing the photoresist by using acetone; then at N2In the atmosphere, carrying out rapid thermal annealing for 30s at 400 ℃ to form a Schottky gate electrode;
11) and (3) deposition of a protective layer: by plasma enhanced chemical vapor deposition, with a gas flow rate of 1420sccm of N2O, 150sccm SiH4And N of 392sccm2As a chemical reaction source, SiO with the thickness of 200nm is deposited under the conditions that the temperature is 300 ℃, the radio frequency power is 15W, and the pressure of a chamber for plasma enhanced chemical vapor deposition is 0.9Torr2A protective layer;
12) opening holes and interconnecting metals: throwing positive photoresist S9912 to the sample at the rotating speed of 6000 rpm, baking the sample on a hot plate at the temperature of 100 ℃ for 5min, and forming a photoetching window through ultraviolet photoetching, developing and fixing; finally, removing the SiO2 protective layer materials covered on the surfaces of the ohmic contact electrode and the Schottky gate electrode by using a reactive ion etching technology, wherein CF is adopted as an etching reaction gas4And O2The radio frequency power is 50W to complete the hole opening; the interconnection metal is formed by Ti/Au metal lamination with good adhesion and is completed by electron beam evaporation and stripping processes.
According to the scheme, in the step 1), the AlN nucleating layer is 20nm thick, the GaN buffer layer is 2 μm thick, the AlN inserting layer is 1nm thick, the AlGaN barrier layer is 20nm thick, and the GaN cap layer is 2nm thick.
According to the scheme, the wavelength of the photoetching in the step 4), the step 6) and the step 12) is 435nm, the developing solution is tetramethylammonium hydroxide (TMAH) with the mass concentration of 2.38%, and the fixing solution is water.
According to the scheme, the dry etching in the step 5) lasts for 2min under the power of 50W, and the etching depth is 280 nm.
According to the scheme, the width of the source and the drain in the step 7) is 2 μm, and the distance between the source and the drain is 20 μm.
According to the above scheme, the developing solution in the step 9) and the developing solution in the step 10) are mixed solution of methyl isobutyl ketone and isopropanol (MIBK: IPA) in a volume ratio of 1:3, and the fixing solution is IPA.
The invention has the beneficial effects that:
1) the PN junction gate type GaN HEMT is designed on the basis of a p-type gate, a layer of n-GaN is added on the p-GaN to form a PN junction, and the PN junction is reversely biased when a grid voltage is applied by utilizing the PN junction, so that the grid breakdown voltage Vg is increased, the grid voltage Vg has large grid voltage swing amplitude, and the power switch is very suitable for application of a power switch.
2) Compared with the traditional p-enhanced GaN HEMT, under the condition of the same peak electric field, the PN junction of the invention can bear higher gate breakdown voltage, because the breakdown voltage of Schottky mainly depends on the Schottky junction, the Schottky junction is a sudden change junction and belongs to unilateral depletion, and the PN junction is bidirectional depletion, the width of the whole depletion layer is much higher than that of the Schottky gate, and the gate breakdown voltage of the device is improved.
Drawings
FIG. 1 is a schematic view of a workpiece configuration during cleaning of a substrate according to the present invention;
FIG. 2 is a schematic view of the workpiece configuration for mesa isolation of the present invention;
FIG. 3 is a schematic diagram of a workpiece structure during PN junction etching according to the present invention;
FIG. 4 is a schematic illustration of a workpiece structure in ohmic contact according to the invention;
FIG. 5 is a schematic view of a workpiece structure during deposition of a passivation layer according to the present invention;
FIG. 6 is a schematic diagram of the workpiece structure during gate trench etching according to the present invention;
FIG. 7 is a schematic view of the workpiece structure during deposition of the gate metal of the present invention;
FIG. 8 is a schematic view of the workpiece structure during the protective deposition of the present invention;
figure 9 is a schematic view of the workpiece structure during the deposition of the opening and interconnect metal of the present invention.
Detailed Description
The technical solution of the present invention is described below with reference to the accompanying drawings and examples.
Example 1, see fig. 1 to 9:
the invention provides a novel enhanced GaN HEMT device structure which is prepared by the following steps:
1) and (3) epitaxial growth: respectively growing an AlN nucleating layer with the thickness of 20nm, a GaN buffer layer with the thickness of 2 microns, an AlN inserting layer with the thickness of 1nm, an AlGaN barrier layer with the thickness of 20nm and a GaN capping layer with the thickness of 2nm from bottom to top on a 6-inch (111) Si substrate through Metal Organic Chemical Vapor Deposition (MOCVD) to form a Si-based GaN epitaxial wafer;
2) growing a PN junction gate stack: growing PN junction gate stack by metal organic chemical vapor deposition, which consists of a p-GaN layer with the thickness of 100nm and an n-GaN layer with the thickness of 30nm from bottom to top, wherein the Mg doping concentration of the p-GaN layer is 3 multiplied by 1019cm-3And the n-GaN layer has a Si doping concentration of 1 × 1019cm-3；
3) Cleaning a Si-based GaN epitaxial wafer: sequentially putting the epitaxial substrate into MOS grade acetone and MOS grade ethanol, performing ultrasonic treatment for 3min, cleaning the sample wafer with flowing deionized water for 2min, and blow-drying with a nitrogen gun; the device is then immersed in HF HCl H2Removing natural oxide on the surface of the solution with the volume ratio of O being 1:4:20 for 1min, then washing the solution with deionized water for 2min and drying the solution with a nitrogen gun to complete sample cleaning (see figure 1);
4) photoetching and forming an alignment mark: throwing positive photoresist S9912 to a sample at the rotating speed of 6000 rpm, baking the sample on a hot plate at the temperature of 100 ℃ for 5min, forming a corrosion window through ultraviolet lithography (wavelength of 435nm) and development (developing solution is TMAH with the mass concentration of 2.38%)/fixation (fixing solution is water), and simultaneously forming an alignment mark on the photoresist;
5) isolating the table top: using Reactive Ion Etching (RIE) method, using chlorine gas (Cl)2) As a reactive etching gas, the etching depth is 280nm under the power of 50W for 2min, and the GaN cap layer, the AlGaN barrier layer, the AlN insert layer and part of the GaN buffer layer are etched by a dry method; etching away the heterojunction two-dimensional electron gas outside the active region to form isolation between the active regions of the device (see fig. 2);
6) etching the PN junction laminated layer: throwing positive glue AZ6130 to the sample, the rotating speed is 6000 r/min, and baking on a hot plate at the temperature of 95 ℃ for 2 min; alignment with the first timePerforming mark overlay photoetching (with the wavelength of 435nm), developing (with the developing solution being TMAH with the mass concentration of 2.38%) and fixing (with the fixing solution being water) to form a gate electrode window; use of Low Damage BCl3/Cl2Dry etching by a basic Inductively Coupled Plasma (ICP) method to remove the n-GaN/p-GaN laminated layer outside the gate region; then, in N2Annealing at 850 deg.C for 25min in an atmosphere to reactivate the n-GaN/p-GaN stack at a length of 2 μm at a gate-source spacing of 15 μm from the source (see FIG. 3);
7) source and drain ohmic contacts: throwing positive glue AZ6130 to the sample, the rotating speed is 6000 r/min, and baking on a hot plate at the temperature of 95 ℃ for 2 min; photoetching (with the wavelength of 435nm) with the alignment mark in an alignment manner, developing (with the developing solution being TMAH with the mass concentration of 2.38%) and fixing (with the fixing solution being water) to form a source-drain electrode window; then, completing metal stack deposition by adopting electron beam evaporation equipment to form a Ti/Al/Ni/Au (20nm/50nm/40nm/50nm) metal layer; performing rapid thermal annealing at 850 deg.C for 30s to form ohmic contact electrode with source/drain electrode width of 2 μm and source/drain spacing of 20 μm (see FIG. 4);
8) deposition of a passivation layer: SiH gas flow rate of 600sccm by Plasma Enhanced Chemical Vapor Deposition (PECVD)41960sccm of N2And NH of 20sccm3As a chemical reaction source, 160nm thick Si is deposited under the conditions that the temperature is 250 ℃, the radio frequency power is 60W, and the pressure of a chamber for plasma enhanced chemical vapor deposition is 500Torr3N4A passivation layer (see fig. 5);
9) etching a gate groove: throwing PMMA glue on a sample, drying the sample on a hot plate at 180 ℃ for 10min at the rotating speed of 2000 r/min; exposing the substrate to 2 μm away from the source by electron beam, wherein the pattern length of the gate groove is 2 μm; forming a gate groove window by developing (developing solution MIBK: IPA 1: 3) for 25s and fixing (fixing solution IPA) for 5 s; using RIE technique, at 50W power for 2min, by CF4Removing Si in grid region by plasma dry etching3N4A layer forming a gate trench (see fig. 6);
10) and (3) gate metal deposition: throwing double-layer electron beam glue to the sample, wherein the lower layer is made of Copolymer glue, the rotating speed is 3000 r/min, the hot plate at 150 ℃ is used for baking for 15min, the upper layer is made of PMMA glue, the rotating speed is 3000 r/min, and the hot plate at 180 ℃ is used for heatingBaking for 10 min; at the position of the gate groove, a gate electrode pattern is aligned by adopting electron beam exposure, the size of the gate electrode is set to be 2 mu m, and a gate electrode pattern window is formed by developing (developing solution MIBK: IPA is 1: 3) for 25s and fixing (fixing solution is IPA) for 5s after exposure; growing a Ni/Au (30nm/50nm) metal layer on the dielectric layer forming the grid pattern window by adopting an electron beam evaporation method, forming Schottky contact between the metal layer and the dielectric layer, and removing the photoresist by using acetone; then at N2Carrying out rapid thermal annealing at 400 ℃ for 30s in an atmosphere to form a Schottky gate electrode (see figure 7);
11) and (3) deposition of a protective layer: by PECVD method, with a gas flow rate of 1420sccm N2O, 150sccm SiH4And N of 392sccm2As a chemical reaction source, SiO with the thickness of 200nm is deposited under the conditions that the temperature is 300 ℃, the radio frequency power is 15W, and the pressure of a PECVD chamber is 0.9Torr2A protective layer (see fig. 8);
12) opening holes and interconnecting metals: throwing positive photoresist S9912 to a sample at the rotating speed of 6000 rpm, baking the sample on a hot plate at the temperature of 100 ℃ for 5min, and forming a photoetching window through ultraviolet photoetching (the wavelength is 435nm) and developing (the developing solution is TMAH with the mass concentration of 2.38%)/fixing (the fixing solution is water); finally, removing the SiO2 protective layer material covered on the surfaces of the ohmic contact electrode and the Schottky gate electrode by using RIE etching technology, wherein CF is adopted as etching reaction gas4And O2The radio frequency power is 50W to complete the hole opening; the interconnection metal is made of a Ti/Au (20nm/200nm) metal laminate with good adhesion by electron beam evaporation and lift-off process (see FIG. 9).
The above embodiments are only used for illustrating but not limiting the technical solutions of the present invention, and although the above embodiments describe the present invention in detail, those skilled in the art should understand that: modifications and equivalents may be made thereto without departing from the spirit and scope of the invention and any modifications and equivalents may fall within the scope of the claims.

Claims (6)

1. A novel enhanced GaN HEMT device structure is characterized by being prepared by the following steps:
1) and (3) epitaxial growth: respectively growing an AlN nucleating layer, a GaN buffer layer, an AlN inserting layer, an AlGaN barrier layer and a GaN capping layer from bottom to top on a Si substrate through metal organic chemical vapor deposition to form a Si-based GaN epitaxial wafer;
2) growing a PN junction gate stack: growing PN junction gate stack by metal organic chemical vapor deposition, which consists of a p-GaN layer with the thickness of 100nm and an n-GaN layer with the thickness of 30nm from bottom to top, wherein the Mg doping concentration of the p-GaN layer is 3 multiplied by 1019cm-3And the n-GaN layer has a Si doping concentration of 1 × 1019cm-3；
3) Cleaning a Si-based GaN epitaxial wafer: sequentially putting the epitaxial substrate into MOS grade acetone and MOS grade ethanol, performing ultrasonic treatment for 3min, cleaning the sample wafer with flowing deionized water for 2min, and blow-drying with a nitrogen gun; the device is then immersed in HF HCl H2Removing natural oxides on the surface of the solution with the volume ratio of O being 1:4:20 for 1min, then washing the solution for 2min by using deionized water and drying the solution by using a nitrogen gun to finish sample cleaning;
4) photoetching and forming an alignment mark: throwing positive photoresist S9912 to the sample at the rotating speed of 6000 rpm, baking the sample on a hot plate at the temperature of 100 ℃ for 5min, forming a corrosion window through ultraviolet lithography, developing and fixing, and simultaneously forming an alignment mark on the photoresist;
5) isolating the table top: adopting a reactive ion etching method, and etching the GaN cap layer, the AlGaN barrier layer, the AlN insert layer and part of the GaN buffer layer by a dry method by using chlorine as reactive etching gas; etching two-dimensional electron gas of the heterojunction outside the active region to form isolation between the active regions of the devices;
6) etching the PN junction laminated layer: and (3) throwing positive glue AZ6130 to the sample at the rotating speed of 6000 revolutions per minute, and drying on a hot plate at the temperature of 95 ℃ for 2 minutes. Photoetching, developing and fixing the alignment mark for the first time to form a gate electrode window; use of Low Damage BCl3/Cl2Removing the n-GaN/p-GaN laminated layer outside the gate region by dry etching of the base inductance coupling plasma; then, in N2Annealing at 850 deg.C for 25min in atmosphere to reactivate n-GaN/p-GaN stack at a distance of 3 μm from the source and a gate-source spacing of 15 μm, and a length of 2 μm;
7) source and drain ohmic contacts: throwing positive glue AZ6130 to the sample, the rotating speed is 6000 r/min, and baking on a hot plate at the temperature of 95 ℃ for 2 min; photoetching, developing and fixing the alignment mark to form a source/drain electrode window; then, completing metal stack deposition by adopting electron beam evaporation equipment to form a Ti/Al/Ni/Au metal layer; performing rapid thermal annealing at 850 ℃ for 30s to form an ohmic contact electrode with a source electrode and a drain electrode;
8) deposition of a passivation layer: SiH with a gas flow of 600sccm by plasma enhanced chemical vapor deposition41960sccm of N2And NH of 20sccm3As a chemical reaction source, 160nm thick Si is deposited under the conditions that the temperature is 250 ℃, the radio frequency power is 60W, and the pressure of a chamber for plasma enhanced chemical vapor deposition is 500Torr3N4A passivation layer;
9) etching a gate groove: throwing polymethyl methacrylate electron beam adhesive to the sample, wherein the rotating speed is 2000 r/min, and drying on a hot plate at 180 ℃ for 10 min; exposing a grid groove graph at a position which is 3 mu m away from a source electrode and has a grid-source spacing of 15 mu m by adopting an electron beam, wherein the length of the grid groove graph is 2 mu m; forming a grid groove window through development for 25s and fixation for 5 s; using RIE technique, at 50W power for 2min, by CF4Removing Si in grid region by plasma dry etching3N4A layer forming a gate trench;
10) and (3) gate metal deposition: throwing double-layer electron beam glue on a sample, wherein the lower layer is copolymer glue, the rotating speed is 3000 r/min, the hot plate at the temperature of 150 ℃ is used for baking for 15min, the upper layer is polymethyl methacrylate electron beam glue, the rotating speed is 3000 r/min, and the hot plate at the temperature of 180 ℃ is used for baking for 10 min; at the position of the gate groove, a gate electrode pattern is etched by adopting electron beam exposure, the size of the gate electrode is set to be 2 mu m, and a gate electrode pattern window is formed by developing for 25s and fixing for 5s after exposure; growing a Ni/Au metal layer on the dielectric layer forming the grid pattern window by adopting an electron beam evaporation method, forming Schottky contact between the Ni/Au metal layer and the dielectric layer, and removing the photoresist by using acetone; then at N2In the atmosphere, carrying out rapid thermal annealing for 30s at 400 ℃ to form a Schottky gate electrode;
11) and (3) deposition of a protective layer: by plasma enhanced chemical vapor deposition, with a gas flow rate of 1420sccm of N2O, 150sccm SiH4And N of 392sccm2As a chemical reaction source, the temperature is 300 ℃, and the radio frequency power is15W, 200nm thick SiO was deposited under a chamber pressure of 0.9Torr in the PECVD chamber2A protective layer;
12) opening holes and interconnecting metals: throwing positive photoresist S9912 to the sample at the rotating speed of 6000 rpm, baking the sample on a hot plate at the temperature of 100 ℃ for 5min, and forming a photoetching window through ultraviolet photoetching, developing and fixing; finally, removing the SiO2 protective layer materials covered on the surfaces of the ohmic contact electrode and the Schottky gate electrode by using a reactive ion etching technology, wherein CF is adopted as an etching reaction gas4And O2The radio frequency power is 50W to complete the hole opening; the interconnection metal is formed by Ti/Au metal lamination with good adhesion and is completed by electron beam evaporation and stripping processes.
2. The structure of the novel enhancement mode GaN HEMT device according to claim 1, wherein in the step 1), the AlN nucleation layer has a thickness of 20nm, the GaN buffer layer has a thickness of 2 μm, the AlN insertion layer has a thickness of 1nm, the AlGaN barrier layer has a thickness of 20nm, and the GaN cap layer has a thickness of 2 nm.
3. The structure of the novel enhancement mode GaN HEMT device according to claim 1, wherein the wavelengths of the photoetching in the step 4), the step 6) and the step 12) are 435nm, the developing solution is tetramethylammonium hydroxide with the mass concentration of 2.38%, and the fixing solution is water.
4. The novel enhancement mode GaN HEMT device structure of claim 1, wherein in the step 5), the dry etching lasts for 2min under the power of 50W, and the etching depth is 280 nm.
5. The structure of the novel enhancement mode GaN HEMT device according to claim 1, wherein in the step 7), the width of the source electrode and the width of the drain electrode are both 2 μm, and the distance between the source electrode and the drain electrode is 20 μm.
6. The novel enhancement-type GaN HEMT device structure as claimed in claim 1, wherein the developing solution in step 9) and step 10) is a mixed solution of methyl isobutyl ketone and isopropanol with a volume ratio of 1:3, and the fixing solution is isopropanol.
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