CN110752185B - Wide-swing bidirectional amplitude limiting circuit based on gallium nitride and preparation method thereof - Google Patents

Wide-swing bidirectional amplitude limiting circuit based on gallium nitride and preparation method thereof Download PDF

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CN110752185B
CN110752185B CN201810811324.1A CN201810811324A CN110752185B CN 110752185 B CN110752185 B CN 110752185B CN 201810811324 A CN201810811324 A CN 201810811324A CN 110752185 B CN110752185 B CN 110752185B
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electrode
metal
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photoetching
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CN110752185A (en
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杨凌
马晓华
芦浩
宓珉翰
侯斌
周小伟
祝杰杰
郝跃
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Xidian University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors

Abstract

The invention relates to a preparation method of a wide-swing bidirectional amplitude limiting circuit based on gallium nitride, which comprises the steps of manufacturing a PIN diode, a Schottky diode and a GaN-based device, connecting the PIN diode and the Schottky diode in parallel and then connecting the PIN diode and the Schottky diode with the GaN-based device through a metal interconnection process, and thus completing the preparation of the wide-swing bidirectional amplitude limiting circuit based on the gallium nitride. According to the embodiment of the invention, the PIN diode and the Schottky diode are connected in parallel and then connected with the grid electrode of the GaN-based device, so that the self-protection of the circuit can be realized, the impact of forward and reverse high-power signals on the device can be borne, and the bidirectional protection of the device can be realized.

Description

Wide-swing bidirectional amplitude limiting circuit based on gallium nitride and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a wide-swing bidirectional amplitude limiting circuit based on gallium nitride and a preparation method thereof.
Background
With the continuous progress of semiconductor technology, silicon-based semiconductor technology has been continuously developed for decades and has become the most mature technology in the current semiconductor technology, but in the field of power semiconductors, silicon-based devices are approaching the theoretical limit, first and second-generation semiconductor materials have been unable to meet the requirements of higher-frequency and higher-power electronic devices, and the research on novel semiconductor material devices is particularly important, electronic devices based on nitride semiconductor materials can meet the requirements, and GaN materials have the advantages of larger forbidden bandwidth, higher critical breakdown electric field, higher electron mobility, higher electron saturation speed, capability of working under higher temperature conditions and the like compared with silicon materials, and have great exploration potential.
The front end of a radar receiver often has a high-sensitivity low-noise amplifier, and the low-noise amplifier is a small-signal linear device, which receives very weak signals, but the whole system must be capable of bearing larger power. In order to protect the devices from being burned, a microwave limiter is usually added to the front end of the receiver. When a small signal is input, the amplitude limiter only presents small loss, and when a large signal is input, the amplitude limiter greatly attenuates the small signal.
The PIN diode is a semiconductor diode which is formed by a three-layer structure, namely a P layer formed by heavily doping a P type material, an N layer formed by heavily doping an N type material, and an I layer formed by a high-resistivity lightly doped intrinsic layer sandwiched between the P layer and the N layer.
At present, GaAs MESFET amplitude limiters, GaAs Schottky barrier amplitude limiters and the like are mainly adopted at home and abroad, and the device is required to have low on-state resistance and low off-state capacitance, can bear the impact of high-power signals, and has the characteristics of small area, superior performance and the like compared with a GaAs MESFET amplitude limiter single-chip circuit.
However, the gallium arsenide second-generation semiconductor material cannot meet the requirements of electronic devices with higher frequency and higher power, and the schottky barrier limiter has insufficient capability of bearing the impact of high-power signals in the same area, so that the defect is obvious.
Therefore, how to meet the requirement that the device can bear the impact of forward and reverse high-power signals is important, and the circuit can be protected.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a wide-swing bidirectional amplitude limiting circuit based on gallium nitride and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
the embodiment of the invention provides a preparation method of a wide-swing bidirectional amplitude limiting circuit based on gallium nitride, which comprises the following steps:
s1, photoetching the first AlGaN barrier layer, and etching to remove the first AlGaN barrier layer;
s2, forming a PIN diode manufacturing region and a Schottky diode manufacturing region on the GaN layer;
s3, manufacturing the PIN diode in the PIN diode manufacturing area;
s4, manufacturing the Schottky diode in the Schottky diode manufacturing area;
s5, manufacturing a GaN-based device on the second AlGaN barrier layer;
and S6, connecting the PIN diode and the Schottky diode in parallel and then connecting the PIN diode and the Schottky diode with the GaN-based device through metal interconnection to obtain the wide-swing bidirectional amplitude limiting circuit based on the gallium nitride.
In one embodiment of the present invention, S3 includes:
s31, growing a doped N + layer on the GaN layer, growing an I layer on the N + layer, and growing a doped P + layer on the I layer;
s32, photoetching the P + layer, and evaporating metal to form a P + layer electrode;
s33, photoetching the P + layer to form a groove digging region, and etching the P + layer to the surface of the N + layer;
and S34, photoetching the N + layer, and evaporating metal to form an N + layer electrode to obtain the PIN diode.
In one embodiment of the present invention, S4 includes:
s41, epitaxially growing a doped N + type GaN layer on the GaN layer;
s42, epitaxially growing a doped N-type GaN layer on the N + type GaN layer;
s43, photoetching the N-type GaN layer and evaporating the metal stack layer to form Schottky contact, and finishing the manufacture of the N-type GaN layer electrode;
s44, etching the N + type GaN layer and the N-type GaN layer to form an etching area;
and S45, photoetching the etching area and evaporating ohmic metal to form ohmic contact, and finishing the manufacture of the N + type GaN layer electrode to obtain the Schottky diode.
In one embodiment of the present invention, S5 includes:
s51, evaporating ohmic metal on the second AlGaN barrier layer to form a source electrode and a drain electrode respectively;
s52, growing an SiN medium layer on the source electrode, the drain electrode and the second AlGaN barrier layer;
s53, manufacturing a mask on the SiN medium layer, and etching a groove;
and S54, photoetching a T-shaped gate region on the groove, and evaporating metal in the T-shaped gate region to form a gate to obtain the GaN-based device.
In one embodiment of the present invention, S6 includes:
s61, depositing a first SiN protective layer on the surfaces of the P + layer electrode and the N + layer electrode;
s62, depositing a second SiN protective layer on the surfaces of the N-type GaN layer electrode and the N + type GaN layer electrode;
s63, depositing SiO on the source electrode, the drain electrode and the grid electrode2A protective layer;
s64, photoetching the first SiN protective layer, the second SiN protective layer and the SiO2Forming a metal interconnection layer open hole region on the protective layer, and etching the first SiN protective layer, the second SiN protective layer and the SiO of the metal interconnection layer open hole region2A protective layer;
s65, a first SiN protective layer, a second SiN protective layer and SiO in the metal interconnection layer open hole region2And evaporating interconnection metal on the protective layer, connecting the PIN diode and the Schottky diode in parallel and then connecting the PIN diode and the GaN-based device to form the wide-swing bidirectional amplitude limiting circuit based on the gallium nitride.
In one embodiment of the invention, the doped N + layer has a thickness of 10 μm and a doping concentration of 1 × 1016cm-3～1×1018cm-3The doping element is Si; the thickness of the layer I is 20-70 mu m; the thickness of the doped P + layer is 1-10 μm, and the doping concentration is 1 × 1019cm-3～1×1020cm-3The doping element is Mg.
In one embodiment of the present invention, the thickness of the doped N + type GaN layer is 10 μm to 40 μm, and the doping concentration is 1018～1019cm-3(ii) a The thickness of the doped N-type GaN layer is 20-90 μm, and the doping concentration is 1014～1017cm-3(ii) a The Schottky contact area is 1 multiplied by 10-4cm2～4×10-4cm2。
In one embodiment of the invention, the thickness of the SiN dielectric layer is 60nm to 120nm, and the gate length is 0.2 μm to 0.5 μm.
In an embodiment of the present invention, a thickness of the first SiN protective layer is 150nm to 200nm, and a thickness of the second SiN protective layer is 150nm to 200 nm.
In an embodiment of the present invention, a wide-swing bidirectional amplitude limiting circuit based on gallium nitride is manufactured by the method described in the above embodiment.
Compared with the prior art, the invention has the beneficial effects that:
1. the wide-swing bidirectional amplitude limiting circuit based on gallium nitride can realize the self-protection of the circuit by adopting the circuit which connects the PIN diode and the Schottky diode in parallel and then is connected with the grid layer;
2. the wide-swing bidirectional amplitude limiting circuit based on gallium nitride can meet the requirement that a device can bear the impact of forward and reverse high-power signals, and bidirectional protection of the device is realized.
Drawings
Fig. 1 is a schematic process flow diagram of a method for manufacturing a wide-swing bidirectional amplitude limiting circuit based on gallium nitride according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a wide-swing bidirectional amplitude limiting circuit based on gallium nitride according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic process flow diagram of a method for manufacturing a wide-swing bidirectional amplitude limiting circuit based on gallium nitride according to an embodiment of the present invention. The preparation method specifically comprises the following steps:
s1, photoetching the first AlGaN barrier layer, and etching to remove the first AlGaN barrier layer;
s2, forming a PIN diode manufacturing region and a Schottky diode manufacturing region on the GaN layer;
s3, manufacturing the PIN diode in the PIN diode manufacturing area;
s4, manufacturing the Schottky diode in the Schottky diode manufacturing area;
s5, manufacturing a GaN-based device on the second AlGaN barrier layer;
and S6, connecting the PIN diode and the Schottky diode in parallel and then connecting the PIN diode and the Schottky diode with the GaN-based device through metal interconnection to obtain the wide-swing bidirectional amplitude limiting circuit based on the gallium nitride.
Wherein S3 includes:
s31, growing a doped N + layer on the GaN layer, growing an I layer on the N + layer, and growing a doped P + layer on the I layer;
s32, photoetching the P + layer, and evaporating metal to form a P + layer electrode;
s33, photoetching the P + layer to form a groove digging region, and etching the P + layer to the surface of the N + layer;
and S34, photoetching the N + layer, and evaporating metal to form an N + layer electrode to obtain the PIN diode.
Wherein S4 includes:
s41, epitaxially growing a doped N + type GaN layer on the GaN layer;
s42, epitaxially growing a doped N-type GaN layer on the N + type GaN layer;
s43, photoetching the N-type GaN layer and evaporating the metal stack layer to form Schottky contact, and finishing the manufacture of the N-type GaN layer electrode;
a schottky contact region is lithographed on the N-GaN layer.
Firstly, placing a sample on a hot plate at 200 ℃ for baking for 5 min;
then, coating and spin coating the photoresist at a spin coating speed of 3500rpm, and baking the sample on a hot plate at 90 ℃ for 1 min;
then, the sample is put into a photoetching machine, and the Schottky contact area is defined through established layout photoetching, wherein the Schottky contact area is 1 multiplied by 10-4cm2～4×10-4cm2On the N-GaN layerExposing the photoresist;
finally, the exposed sample is placed into a developing solution to remove the photoresist in the Schottky contact area, and the photoresist is rinsed with ultrapure water and dried with nitrogen.
And (4) evaporating Schottky metal W.
And (3) putting the photoetching-finished sample into magnetron sputtering PVD, and starting coating after the vacuum degree is reached, wherein the coating metal is W.
And stripping the metal.
Soaking the sample wafer after the film coating in acetone for more than 40 minutes and then carrying out ultrasonic treatment; then putting the sample wafer into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min; then, putting the sample wafer into an acetone solution and an ethanol solution in sequence, and ultrasonically cleaning for 3 min; and finally, washing the sample wafer by ultrapure water and drying the sample wafer by nitrogen to form Schottky contact, thereby completing the manufacture of the N-type GaN layer electrode.
S44, etching the N + type GaN layer and the N-type GaN layer to form an etching area;
and S45, photoetching the etching area and evaporating ohmic metal to form ohmic contact, and finishing the manufacture of the N + type GaN layer electrode to obtain the Schottky diode.
And photoetching an N + type GaN layer electrode region on the N + type GaN layer.
Firstly, placing a sample wafer on a hot plate at 200 ℃ for baking for 5 min;
then, throwing the stripping glue on the sample wafer, wherein the thickness of the throwing glue is 0.35 mu m, and drying the sample wafer on a hot plate at the temperature of 200 ℃ for 5 min;
then, throwing photoresist on the sample wafer, wherein the thickness of the photoresist is 0.77 mu m, and drying the sample wafer on a hot plate at 90 ℃ for 1 min;
then, the sample wafer is placed into a photoetching machine to expose the photoresist in the N + type GaN layer electrode area;
and finally, putting the exposed sample wafer into a developing solution to remove the photoresist and the stripping glue in the N + type GaN layer electrode area, and carrying out ultra-pure water washing and nitrogen blow-drying on the sample wafer.
And (4) coating a bottom film.
And removing the photoresist thin layer which is not developed and cleaned in the pattern area of the sample wafer subjected to the N + type GaN layer electrode area photoetching by using a plasma photoresist remover, wherein the processing time is 5min, and the stripping yield is greatly improved by the step.
The ohmic metal is evaporated.
Putting the sample subjected to plasma photoresist removal into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10-6And after the Torr is carried out, evaporating ohmic metal on the N + type GaN layer electrode area in the etching hole, wherein the ohmic metal is a metal stack structure which is formed by four layers of metals of Ti, Al, Ni and Au from bottom to top in sequence.
Stripping metal and annealing.
Firstly, soaking a sample wafer subjected to metal evaporation of the N + type GaN layer electrode in acetone for more than 40 minutes and then carrying out ultrasonic treatment;
then, putting the sample wafer into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min;
then, putting the sample wafer into an acetone solution and an ethanol solution in sequence, and ultrasonically cleaning for 3 min;
then, washing the sample wafer with ultrapure water and drying the sample wafer with nitrogen;
and finally, putting the sample wafer into a rapid annealing furnace, introducing nitrogen into the annealing furnace for 10min, setting the temperature of the annealing furnace at 830 ℃ in the nitrogen atmosphere, and carrying out high-temperature annealing for 30s to enable ohmic metal on the N + type GaN layer electrode area to sink, so that ohmic contact between the ohmic metal and the N + type GaN layer is formed, and the N + type GaN layer electrode is manufactured.
Wherein S5 includes:
s51, evaporating ohmic metal on the second AlGaN barrier layer to form a source electrode and a drain electrode respectively;
source and drain electrode regions are lithographically patterned on the barrier layer.
Firstly, placing a sample wafer subjected to mesa etching on a hot plate at 200 ℃ for baking for 5 min;
then, throwing the stripping glue on the sample wafer, wherein the thickness of the throwing glue is 0.35 mu m, and drying the sample wafer on a hot plate at the temperature of 200 ℃ for 5 min;
then, throwing photoresist on the sample wafer, wherein the thickness of the photoresist is 0.77 mu m, and drying the sample wafer on a hot plate at 90 ℃ for 1 min;
then, the sample wafer is put into a photoetching machine to expose the photoresist in the source electrode area and the drain electrode area;
and finally, putting the exposed sample wafer into a developing solution to remove the photoresist and the stripping glue in the source electrode area and the drain electrode area, and carrying out ultra-pure water washing and nitrogen gas blowing on the sample wafer. (ii) a
And (4) coating a bottom film.
And removing the undeveloped photoresist thin layer in the pattern area of the sample wafer subjected to the photoetching in the source electrode area and the drain electrode area by using a plasma photoresist remover, wherein the processing time is 5min, and the stripping yield is greatly improved by the step.
Evaporating the drain electrode metal.
Putting the sample subjected to plasma photoresist removal into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10-6And after the Torr, evaporating ohmic metal on the barrier layers in the source electrode area and the drain electrode area and the photoresist outside the source electrode area and the drain electrode area, wherein the ohmic metal is a metal stack structure consisting of four layers of metals of Ti, Al, Ni and Au from bottom to top in sequence.
Stripping metal and annealing.
Firstly, soaking a sample wafer subjected to source-drain metal evaporation in acetone for more than 40 minutes and then carrying out ultrasonic treatment;
then, putting the sample wafer into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min;
then, putting the sample wafer into an acetone solution and an ethanol solution in sequence, and ultrasonically cleaning for 3 min;
then, washing the sample wafer with ultrapure water and drying the sample wafer with nitrogen;
and finally, putting the sample wafer into a rapid annealing furnace, introducing nitrogen into the annealing furnace for 10min, setting the temperature of the annealing furnace at 830 ℃ in the nitrogen atmosphere, and performing high-temperature annealing for 30s to ensure that ohmic metal on the source electrode and drain electrode regions sinks to the GaN buffer layer, so that ohmic contact between the ohmic metal and the heterojunction channel is formed, and a source electrode and a drain electrode are formed.
S52, growing an SiN medium layer on the source electrode, the drain electrode and the second AlGaN barrier layer;
s53, manufacturing a mask on the SiN medium layer, and etching a groove;
and S54, photoetching a T-shaped gate region on the groove, and evaporating metal in the T-shaped gate region to form a gate to obtain the GaN-based device.
Wherein S6 includes:
s61, depositing a first SiN protective layer on the surfaces of the P + layer electrode and the N + layer electrode;
s62, depositing a second SiN protective layer on the surfaces of the N-type GaN layer electrode and the N + type GaN layer electrode;
s63, depositing SiO on the source electrode, the drain electrode and the grid electrode2A protective layer;
s64, photoetching the first SiN protective layer, the second SiN protective layer and the SiO2Forming a metal interconnection layer open hole region on the protective layer, and etching the first SiN protective layer, the second SiN protective layer and the SiO of the metal interconnection layer open hole region2A protective layer;
s65, a first SiN protective layer, a second SiN protective layer and SiO in the metal interconnection layer open hole region2And evaporating interconnection metal on the protective layer, connecting the PIN diode and the Schottky diode in parallel and then connecting the PIN diode and the GaN-based device to form the wide-swing bidirectional amplitude limiting circuit based on the gallium nitride.
Firstly, putting a sample with a metal interconnection photoetching pattern into a plasma photoresist remover for carrying out bottom film treatment, wherein the treatment time is 5 min;
then, the sample is put into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10-6Torr；
Then, evaporating interconnection metal on an electrode in the interconnection metal area of the Schottky diode and a gate electrode in the interconnection metal area of the GaN-based high-frequency device, wherein the interconnection metal is a metal stack structure which is sequentially composed of two layers of Ti and Au from bottom to top;
then, stripping the sample after the evaporation of the interconnection metal is completed so as to remove the interconnection metal, the photoresist and the stripping glue outside the metal interconnection layer region;
finally, the sample was rinsed with ultra pure water and blown dry with nitrogen.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a wide-swing bidirectional amplitude limiting circuit based on gallium nitride according to an embodiment of the present invention, where the wide-swing bidirectional amplitude limiting circuit based on gallium nitride includes:
the semiconductor device comprises a substrate 1, a nucleation layer 2, a GaN layer 3, a second AlGaN barrier layer 4, a drain electrode 5, a source electrode 6, a SiN dielectric layer 7, a gate layer 8 and SiO2The structure comprises a protective layer 9, an interconnection electrode 10, an N + layer 11, an I layer 12, a P + layer 13, a P + layer electrode 14, an N-type GaN layer 15, a first SiN protective layer 16, an N + type GaN layer 17, an N + layer electrode 18, an N-type GaN layer electrode 19, an N + type GaN layer electrode 20, a second SiN protective layer 21 and a metal interconnection layer 22.
Wherein the thickness of the doped N + layer is 10 μm, and the doping concentration is 1 × 1016cm-3～1×1018cm-3The doping element is Si; the thickness of the layer I is 20-70 mu m; the thickness of the doped P + layer is 1-10 μm, and the doping concentration is 1 × 1019cm-3～1×1020cm-3The doping element is Mg; the thickness of the doped N + type GaN layer is 10-40 μm, and the doping concentration is 1018～1019cm-3(ii) a The thickness of the doped N-type GaN layer is 20-90 μm, and the doping concentration is 1014～1017cm-3(ii) a The Schottky contact area is 1 multiplied by 10-4cm2～4×10-4cm2(ii) a The thickness of the SiN dielectric layer is 60 nm-120 nm, and the gate length of the gate is 0.2 μm-0.5 μm; the thickness of the first SiN protective layer is 150 nm-200 nm, and the thickness of the second SiN protective layer is 150 nm-200 nm.
Example two
In this embodiment, on the basis of the above embodiments, the detailed description is focused on the method for manufacturing the wide-swing bidirectional amplitude limiting circuit based on gallium nitride according to the present invention. Specifically, the method may include:
step 1, obtaining and cleaning an AlGaN/GaN heterojunction material, and removing an AlGaN barrier layer in a Schottky diode area by utilizing ICP dry etching:
1a) firstly, placing a wafer in acetone for 2 minutes in an ultrasonic mode, then boiling the wafer in positive photoresist stripping liquid heated in a water bath at 60 ℃ for 10 minutes, then sequentially placing a sample in acetone and ethanol for 3 minutes in an ultrasonic mode respectively, cleaning away residual acetone and ethanol in deionized water, and then using HF (the proportion can be adjusted according to actual scenes, and the preferred proportion is HF: h2O is 1: 5) cleaning the wafer for 30s by using the solution, finally cleaning the wafer by using deionized water, and drying the wafer by using ultra-pure nitrogen;
1b) photoetching a Schottky diode region on the AlGaN barrier layer:
firstly, placing a sample wafer on which an AlGaN barrier layer grows on a hot plate of 200 and baking for 5 min;
then, throwing photoresist to the sample wafer at the rotation speed of 3500rpm, and drying the sample wafer on a hot plate at the temperature of 90 ℃ for 1min after the photoresist throwing is finished;
then, the sample wafer is put into a photoetching machine to expose the photoresist in the electric isolation area;
finally, the sample wafer after exposure is placed into a developing solution to remove the photoresist in the electric isolation area, and the sample wafer is washed by ultrapure water and dried by nitrogen;
1c) and removing the AlGaN barrier layer in the Schottky diode region by utilizing ICP dry etching:
etching the barrier layer by ICP dry method to realize mesa isolation of active region, and etching with gas Cl2/BCl3The pressure is 5mTorr, the power of an upper electrode is 100w, the power of a lower electrode is 10w, and the etching time is 40 s;
1d) removing the residual glue after etching:
sequentially putting the sample wafer subjected to active area isolation into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the electrical isolation area, cleaning with deionized water and drying with nitrogen;
and 2, etching the table top to the barrier layer by adopting ICP equipment to realize active area isolation:
2a) lithographically isolating regions on the barrier layer:
firstly, placing a sample wafer on which a barrier layer grows on a hot plate at 200 ℃ for baking for 5 min;
then, throwing photoresist on the sample wafer by using a photoresist spinner, wherein the rotating speed of the photoresist spinner is 3500rpm, drying the sample wafer on a hot plate at 90 ℃ for 1min after the photoresist throwing is finished, and then putting the sample wafer into a photoetching machine to expose the photoresist in the electric isolation area;
finally, the sample wafer after exposure is placed into a developing solution to remove the photoresist in the electric isolation area, and the sample wafer is washed by ultrapure water and dried by nitrogen;
2b) etching electrically isolated regions on the barrier layer:
for the sample wafer after photoetching, etching the barrier layer by ICP dry method with Cl gas as the etching gas2/BCl3The pressure is 5mTorr, the power of an upper electrode is 100w, the power of a lower electrode is 10w, and the etching time is 40 s;
2c) removing the etched mask:
sequentially putting the sample wafer subjected to active area isolation into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the electrical isolation area, cleaning with deionized water and drying with nitrogen;
step 3, coating photoresist on the etched barrier layer of the table top and photoetching source electrode and drain electrode patterns, and evaporating ohmic contact metal in the source electrode and drain electrode pattern areas by adopting an electron beam evaporation process:
3a) and photoetching a source electrode area and a drain electrode area on the barrier layer:
firstly, placing a sample wafer subjected to mesa etching on a hot plate at 200 ℃ for baking for 5 min;
then, throwing the stripping glue on the sample wafer, wherein the thickness of the throwing glue is 0.35 mu m, and drying the sample wafer on a hot plate at the temperature of 200 ℃ for 5 min;
then, throwing photoresist on the sample wafer, wherein the thickness of the photoresist is 0.77 mu m, and drying the sample wafer on a hot plate at 90 ℃ for 1 min;
then, the sample wafer is put into a photoetching machine to expose the photoresist in the source electrode area and the drain electrode area;
finally, putting the exposed sample wafer into a developing solution to remove the photoresist and the stripping glue in the source electrode area and the drain electrode area, and carrying out ultra-pure water washing and nitrogen blow-drying on the sample wafer;
3b) and (3) coating a bottom film:
removing the undeveloped photoresist thin layer in the pattern area of the sample wafer subjected to the photoetching in the source electrode area and the drain electrode area by using a plasma photoresist remover, wherein the processing time is 5min, and the stripping yield is greatly improved by the step;
3c) evaporation source drain electrode metal:
putting the sample subjected to plasma photoresist removal into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10-6After the Torr, evaporating ohmic metal on the barrier layers in the source electrode area and the drain electrode area and the photoresist outside the source electrode area and the drain electrode area, wherein the ohmic metal is a metal stack structure which is composed of four layers of metals of Ti, Al, Ni and Au from bottom to top in sequence;
3d) stripping metal and annealing:
firstly, soaking a sample wafer subjected to source-drain metal evaporation in acetone for more than 40 minutes and then carrying out ultrasonic treatment;
then, putting the sample wafer into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min;
then, putting the sample wafer into an acetone solution and an ethanol solution in sequence, and ultrasonically cleaning for 3 min;
then, washing the sample wafer with ultrapure water and drying the sample wafer with nitrogen;
finally, putting the sample wafer into a rapid annealing furnace, introducing nitrogen into the annealing furnace for 10min, setting the temperature of the annealing furnace at 830 ℃ in the nitrogen atmosphere, and performing high-temperature annealing for 30s to enable ohmic metal on the source electrode and drain electrode regions to sink to the GaN buffer layer, so that ohmic contact between the ohmic metal and the heterojunction channel is formed, and the source electrode and the drain electrode are formed;
and 4, growing a 60nm SiN dielectric layer on the source electrode, the drain electrode and the AlGaN barrier layer by using a PECVD process:
4a) and (3) performing surface cleaning on the sample subjected to active area electrical isolation:
firstly, putting a sample into an acetone solution for ultrasonic cleaning for 3min, wherein the ultrasonic intensity is 3.0;
then, putting the sample into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min;
then, the sample is sequentially placed into an acetone solution and an ethanol solution for ultrasonic cleaning for 3min, and the ultrasonic intensity is 3.0;
finally, washing the sample with ultrapure water and drying the sample with nitrogen;
4b) an SiN medium layer with the thickness of 60nm is grown on a source electrode, a drain electrode and an AlGaN barrier layer by utilizing a PECVD process, and the growth process conditions are as follows: by NH3And SiH4As a reaction gas, the substrate temperature was 250 ℃, the reaction chamber pressure was 600mTorr, and the RF power was 22W;
step 5, a groove area is etched on the SiN medium layer, and the SiN medium layer and a part of the AlGaN barrier layer in the etching area are etched by utilizing an ICP (inductively coupled plasma) process:
5a) etching a groove region on the SiN dielectric layer:
firstly, placing a sample on a hot plate at 200 ℃ for baking for 5 min;
then, coating and spin coating the photoresist at a spin coating speed of 3500rpm, and baking the sample on a hot plate at 90 ℃ for 1 min;
then, putting the sample into a photoetching machine, and exposing the photoresist in the groove region through the groove layout;
finally, putting the exposed sample into a developing solution to remove the photoresist in the groove area, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist;
5b) removing the SiN medium layer in the groove region by utilizing an ICP (inductively coupled plasma) etching process, wherein the etching conditions are as follows: the reaction gas being CF4And O2The pressure of the reaction chamber is 10mTorr, the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectively, and the etching depth is 60nm to the AlGaN barrier layer;
5c) etching process by utilizing ICPRemoving a part of AlGaN barrier layer in the groove region, etching off the AlGaN barrier layer by 5nm, wherein the etching conditions are as follows: the reaction gas is Cl2The pressure of the reaction chamber is 5mTorr, and the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectively;
step 6, etching a gate area on the dielectric layer, evaporating a gate electrode metal layer in the gate area by adopting an electron beam evaporation process, removing the photoresist, and finishing the manufacture of a gate electrode with the gate length of 0.6 mu m and the gate width of 100 mu m:
6a) photoetching a T-shaped gate region on the SiN dielectric layer:
firstly, placing a sample on a hot plate at 200 ℃ for baking for 5 min;
then, coating and spin coating the photoresist at a spin coating speed of 3500rpm, and baking the sample on a hot plate at 90 ℃ for 1 min;
then, putting the sample into a photoetching machine, and exposing the photoresist in the gate region through the established gate layout;
finally, putting the exposed sample into a developing solution to remove the photoresist in the gate region, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist;
6b) evaporation of gate electrode metal:
putting the sample with the etched grid region into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10-6After the Torr, evaporating gate metal on the photoresist outside the gate electrode area, wherein the gate metal is a metal stack structure consisting of three layers of Ni, Au and Ni from bottom to top in sequence;
6c) stripping metal:
soaking the sample wafer subjected to gate electrode evaporation in acetone for more than 40 minutes and then carrying out ultrasonic treatment; then putting the sample wafer into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min; then, putting the sample wafer into an acetone solution and an ethanol solution in sequence, and ultrasonically cleaning for 3 min; finally, washing the sample wafer with ultrapure water and drying the sample wafer with nitrogen to finish the manufacture of the gate electrode;
step 7, depositing SiO of 200nm on the surfaces of the source, drain and gate electrodes by PECVD2Protective layer:
7a) and (3) carrying out surface cleaning on the sample subjected to the gate electrode manufacturing:
firstly, putting a sample into an acetone solution for ultrasonic cleaning for 3min, wherein the ultrasonic intensity is 3.0;
then, putting the sample into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min;
then, the sample is sequentially placed into an acetone solution and an ethanol solution for ultrasonic cleaning for 3min, and the ultrasonic intensity is 3.0;
finally, washing the sample with ultrapure water and drying the sample with nitrogen;
7b) growing SiO with thickness of 200nm by PECVD process2The protective layer is deposited under the following process conditions: gas is 2% SiH4、He、N2O, the gas flow is respectively 100sccm, 100sccm and 90sccm, the deposition temperature is 300 ℃, the pressure of the reaction chamber is 900mTorr, the RF power is 70W, the direct current bias voltage is 24V, and the reaction time is 6 min;
step 8, growing a high-concentration doped N + layer, an undoped I layer and a high-concentration doped P + layer on the undoped gallium nitride wafer by using Molecular Beam Epitaxy (MBE) equipment respectively, wherein the N + layer is a diffusion element of boron, and the P + layer is a diffusion element of phosphorus;
step 9, photoetching an electrode area on the P + layer, evaporating a metal electrode by using electron beam evaporation E-beam, and finishing the manufacturing of the P + layer electrode:
9a) lithograph electrode area on P + layer:
firstly, placing a sample wafer on a hot plate at 200 ℃ for baking for 5 min;
then, throwing the stripping glue on the sample wafer, wherein the thickness of the throwing glue is 0.35 mu m, and drying the sample wafer on a hot plate at the temperature of 200 ℃ for 5 min;
then, throwing photoresist on the sample wafer, wherein the thickness of the photoresist is 0.77 mu m, and drying the sample wafer on a hot plate at 90 ℃ for 1 min;
then, the sample wafer is placed into a photoetching machine to expose the photoresist in the electrode area on the P + layer;
finally, putting the exposed sample wafer into a developing solution to remove the photoresist and the stripping glue in the electrode area of the P + layer, and carrying out ultra-pure water washing and nitrogen blow-drying on the sample wafer;
9b) and (3) coating a bottom film:
removing the undeveloped photoresist thin layer in the pattern area of the sample wafer subjected to the photoetching of the P + layer electrode area by using a plasma photoresist remover, wherein the processing time is 5min, and the stripping yield is greatly improved by the step;
9c) evaporation source drain electrode metal:
putting the sample subjected to plasma photoresist removal into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10-6After the Torr is carried out, evaporating ohmic metal on the P + layer of the electrode area and the photoresist outside the electrode area of the P + layer, wherein the ohmic metal is a metal stack structure which is composed of four layers of metals of Ti, Al, Ni and Au from bottom to top in sequence;
9d) stripping metal and annealing:
firstly, soaking a sample wafer subjected to source-drain metal evaporation in acetone for more than 40 minutes and then carrying out ultrasonic treatment;
then, putting the sample wafer into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min;
then, putting the sample wafer into an acetone solution and an ethanol solution in sequence, and ultrasonically cleaning for 3 min;
then, washing the sample wafer with ultrapure water and drying the sample wafer with nitrogen;
finally, putting the sample wafer into a rapid annealing furnace, introducing nitrogen into the annealing furnace for 10min, setting the temperature of the annealing furnace at 830 ℃ in the nitrogen atmosphere, and carrying out high-temperature annealing for 30s to enable ohmic metal on the P + layer electrode area to sink, so that ohmic contact between the ohmic metal and the P + layer is formed, and the P + layer electrode is manufactured;
step 10, photoetching a groove digging region on the P + layer, and etching the P + layer of the groove digging region to an N + layer by utilizing ICP (inductively coupled plasma):
10a) etching a groove region on the P + layer:
firstly, placing a sample on a hot plate at 200 ℃ for baking for 5 min;
then, coating and spin coating the photoresist at a spin coating speed of 3500rpm, and baking the sample on a hot plate at 90 ℃ for 1 min;
then, putting the sample into a photoetching machine, and exposing the photoresist in the groove digging area through the prepared layout;
finally, putting the exposed sample into a developing solution to remove the photoresist in the groove digging area, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist;
10b) removing the P + layer and the I layer in the groove digging region by utilizing an ICP (inductively coupled plasma) etching process, wherein the etching conditions are as follows: the reaction gas is Cl2The pressure of the reaction chamber is 5mTorr, and the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectively;
step 11, photoetching an electrode area on the N + layer, and evaporating a metal electrode by using E-beam to finish the manufacture of the N + layer electrode:
11a) lithograph electrode area on N + layer:
firstly, placing a sample wafer on a hot plate at 200 ℃ for baking for 5 min;
then, throwing the stripping glue on the sample wafer, wherein the thickness of the throwing glue is 0.35 mu m, and drying the sample wafer on a hot plate at the temperature of 200 ℃ for 5 min;
then, throwing photoresist on the sample wafer, wherein the thickness of the photoresist is 0.77 mu m, and drying the sample wafer on a hot plate at 90 ℃ for 1 min;
then, the sample wafer is put into a photoetching machine to expose the photoresist in the electrode area on the N + layer;
finally, putting the exposed sample wafer into a developing solution to remove the photoresist and the stripping glue in the N + layer electrode area, and carrying out ultra-pure water washing and nitrogen blow-drying on the sample wafer;
11b) and (3) coating a bottom film:
removing the undeveloped photoresist thin layer in the pattern area of the sample wafer subjected to the photoetching of the N + layer electrode area by using a plasma photoresist remover, wherein the processing time is 5min, and the stripping yield is greatly improved by the step;
11c) evaporating N + layer electrode metal:
putting the sample subjected to plasma photoresist removal into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10-6After Torr, a photoresist is applied on the N + layer of the electrode region and outside the electrode region of the N + layerEvaporating ohmic metal, wherein the ohmic metal is a metal stack structure which is sequentially composed of four layers of metals of Ti, Al, Ni and Au from bottom to top;
11d) stripping metal and annealing:
firstly, soaking a sample wafer subjected to source-drain metal evaporation in acetone for more than 40 minutes and then carrying out ultrasonic treatment;
then, putting the sample wafer into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min;
then, putting the sample wafer into an acetone solution and an ethanol solution in sequence, and ultrasonically cleaning for 3 min;
then, washing the sample wafer with ultrapure water and drying the sample wafer with nitrogen;
finally, putting the sample wafer into a rapid annealing furnace, introducing nitrogen into the annealing furnace for 10min, setting the temperature of the annealing furnace at 830 ℃ in the nitrogen atmosphere, and carrying out high-temperature annealing for 30s to enable ohmic metal on the N + layer electrode area to sink, so that ohmic contact between the ohmic metal and the N + layer is formed, and the N + layer electrode is manufactured;
step 12, depositing 150 nm-200 nm SiN protective layers on the surfaces of the P + layer electrode and the N + layer electrode by PECVD:
12a) and (3) carrying out surface cleaning on the metal sample subjected to the N + layer electrode:
firstly, putting a sample into an acetone solution for ultrasonic cleaning for 3min, wherein the ultrasonic intensity is 3.0;
then, putting the sample into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min;
then, the sample is sequentially placed into an acetone solution and an ethanol solution for ultrasonic cleaning for 3min, and the ultrasonic intensity is 3.0;
finally, washing the sample with ultrapure water and drying the sample with nitrogen;
12b) the SiN protective layer with the thickness of 200nm is grown by utilizing a PECVD process, and the process conditions for depositing the protective layer are as follows: gas is 2% SiH4/N2、NH3、N2And He, the gas flow rates are 200sccm, 2sccm, 0sccm, 200sccm, respectively. The pressure is 600mTorr, the temperature is 250 ℃, and the power is 22W;
step 13, epitaxial growth on the GaN buffer layer by MOCVDA high-concentration doped N + type GaN layer with a doping concentration of 1017cm-3；
Step 14, extending an N-type GaN layer on the N + type GaN layer with the doping concentration of 1015cm-3；
Step 15, photoetching a Schottky contact area on the N-GaN layer, and evaporating metal W to form Schottky contact to finish N-Manufacturing a GaN layer electrode:
15a) photoetching a Schottky contact area on the N-GaN layer:
firstly, placing a sample on a hot plate at 200 ℃ for baking for 5 min;
then, coating and spin coating the photoresist at a spin coating speed of 3500rpm, and baking the sample on a hot plate at 90 ℃ for 1 min;
then, the sample is put into a photoetching machine, and the Schottky contact area is defined through established layout photoetching, wherein the Schottky contact area is 1 multiplied by 10-4cm2～4×10-4cm2Exposing the photoresist on the N-GaN layer;
finally, putting the exposed sample into a developing solution to remove the photoresist in the Schottky contact area, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist;
15b) vapor deposition of schottky metal W:
putting the photoetching-finished sample into magnetron sputtering PVD, and starting coating after the vacuum degree is reached, wherein the coating metal is W;
15c) stripping metal:
soaking the sample wafer after the film coating in acetone for more than 40 minutes and then carrying out ultrasonic treatment; then putting the sample wafer into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min; then, putting the sample wafer into an acetone solution and an ethanol solution in sequence, and ultrasonically cleaning for 3 min; finally, the sample wafer is washed by ultrapure water and dried by nitrogen to form Schottky contact, and N is completed-Manufacturing a GaN layer electrode;
step 16, photoetching an N + type GaN layer electrode area on the N-type GaN layer, and etching the substrate to the N + type GaN layer:
16a) photoetching an N + type GaN layer electrode region on the N-type GaN layer:
firstly, placing a sample on a hot plate at 200 ℃ for baking for 5 min;
then, coating and spin coating the photoresist at a spin coating speed of 3500rpm, and baking the sample on a hot plate at 90 ℃ for 1 min;
then, putting the sample into a photoetching machine, and exposing the photoresist in the region through the N + type GaN layer electrode layout N + type GaN layer electrode;
finally, putting the exposed sample into a developing solution to remove the photoresist in the electrode area of the N + type GaN layer, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist;
16b) removing the N-type GaN in the electrode area of the N + type GaN layer by utilizing an ICP (inductively coupled plasma) etching process, and etching to the N + type GaN layer;
and step 17, completing the manufacture of the N + type GaN layer electrode of the Schottky diode in the N + type GaN layer electrode area:
17a) photoetching an electrode region of the N + type GaN layer on the N + type GaN layer:
firstly, placing a sample wafer on a hot plate at 200 ℃ for baking for 5 min;
then, throwing the stripping glue on the sample wafer, wherein the thickness of the throwing glue is 0.35 mu m, and drying the sample wafer on a hot plate at the temperature of 200 ℃ for 5 min;
then, throwing photoresist on the sample wafer, wherein the thickness of the photoresist is 0.77 mu m, and drying the sample wafer on a hot plate at 90 ℃ for 1 min;
then, the sample wafer is placed into a photoetching machine to expose the photoresist in the N + type GaN layer electrode area;
finally, putting the exposed sample wafer into a developing solution to remove the photoresist and the stripping glue in the N + type GaN layer electrode area, and carrying out ultra-pure water washing and nitrogen blow-drying on the sample wafer;
17b) and (3) coating a bottom film:
removing an undeveloped clean photoresist thin layer in a pattern area of a sample wafer subjected to the N + type GaN layer electrode area photoetching by using a plasma photoresist remover, wherein the processing time is 5min, and the stripping yield is greatly improved by the step;
17c) evaporating ohmic metal:
sample to be plasma strippedPutting the product into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 × 10-6After the Torr is carried out, evaporating ohmic metal on the N + type GaN layer electrode area in the etching hole, wherein the ohmic metal is a metal stack structure which is formed by four layers of metals of Ti, Al, Ni and Au from bottom to top in sequence;
17d) stripping metal and annealing:
firstly, soaking a sample wafer subjected to metal evaporation of the N + type GaN layer electrode in acetone for more than 40 minutes and then carrying out ultrasonic treatment;
then, putting the sample wafer into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min;
then, putting the sample wafer into an acetone solution and an ethanol solution in sequence, and ultrasonically cleaning for 3 min;
then, washing the sample wafer with ultrapure water and drying the sample wafer with nitrogen;
finally, putting the sample wafer into a rapid annealing furnace, introducing nitrogen into the annealing furnace for 10min, setting the temperature of the annealing furnace at 830 ℃ in the nitrogen atmosphere, and carrying out high-temperature annealing for 30s to enable ohmic metal on the N + type GaN layer electrode area to sink, so that ohmic contact between the ohmic metal and the N + type GaN layer is formed, and the N + type GaN layer electrode is manufactured;
step 18, depositing 150 nm-200 nm SiN protective layers on the N-type gallium nitride layer electrode and the N + gallium nitride layer electrode by PECVD:
18a) and (3) cleaning the surface of the sample subjected to the manufacture of the Schottky diode electrode:
firstly, putting a sample into an acetone solution for ultrasonic cleaning for 3min, wherein the ultrasonic intensity is 3.0;
then, putting the sample into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min;
then, the sample is sequentially placed into an acetone solution and an ethanol solution for ultrasonic cleaning for 3min, and the ultrasonic intensity is 3.0;
finally, washing the sample with ultrapure water and drying the sample with nitrogen;
18b) the SiN protective layer with the thickness of 200nm is grown by utilizing a PECVD process, and the process conditions for depositing the protective layer are as follows: 2% SiH4/N2、NH3、N2And He, the gas flow rates are 200sccm, 2sccm, 0sccm, 200sccm, respectively. The pressure is 600mTorr, the temperature is 250 ℃, and the power is 22W;
19, forming a protective layer on the PIN diode, the Schottky diode SiN and the GaN device SiO2Photoetching a metal interconnection layer open hole region on the protective layer, and sequentially etching off SiO in the interconnection open hole region by utilizing an ICP (inductively coupled plasma) process2Protective layer and SiN protective layer:
19a) in SiO2And photoetching a metal interconnection layer opening area on the SiN protective layer:
firstly, placing a sample on a hot plate at 200 ℃ for baking for 5 min;
then, coating and spin coating the photoresist at a spin coating speed of 3500rpm, and baking the sample on a hot plate at 90 ℃ for 1 min;
then, putting the sample into a photoetching machine, and exposing the photoresist in the open hole region of the metal interconnection layer through the interconnection open hole layout;
finally, putting the exposed sample into a developing solution to remove the photoresist in the interconnected opening region, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist;
19b) removing 200nm thick SiN protective layer in interconnection hole region of PIN diode and Schottky diode by ICP etching process, and etching 200nm thick SiO of GaN-based low-frequency device2A protective layer;
step 20, evaporating metal interconnection on the electrodes in the metal interconnection region, so that the PIN diode and the Schottky diode are connected in parallel and interconnected with the GaN-based low-frequency device grid:
firstly, putting a sample with a metal interconnection photoetching pattern into a plasma photoresist remover for carrying out bottom film treatment, wherein the treatment time is 5 min;
then, the sample is put into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10-6Torr；
Then, evaporating interconnection metal on an electrode in the interconnection metal area of the Schottky diode and a gate electrode in the interconnection metal area of the GaN-based high-frequency device, wherein the interconnection metal is a metal stack structure which is sequentially composed of two layers of Ti and Au from bottom to top;
then, stripping the sample after the evaporation of the interconnection metal is completed so as to remove the interconnection metal, the photoresist and the stripping glue outside the metal interconnection layer region;
finally, the sample was rinsed with ultra pure water and blown dry with nitrogen.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (10)

1. A preparation method of a wide-swing bidirectional amplitude limiting circuit based on gallium nitride is characterized by being applied to an AlGaN/GaN heterojunction, wherein the AlGaN/GaN heterojunction comprises a substrate layer, a nucleation layer, a GaN layer and a first AlGaN barrier layer, and the method comprises the following steps:
s1, photoetching the first AlGaN barrier layer, and etching to remove part of the first AlGaN barrier layer so as to expose the GaN layer, wherein the rest first AlGaN barrier layer is a second AlGaN barrier layer;
s2, forming a PIN diode manufacturing region and a Schottky diode manufacturing region on the GaN layer;
s3, manufacturing the PIN diode in the PIN diode manufacturing area;
s4, manufacturing the Schottky diode in the Schottky diode manufacturing area;
s5, manufacturing a GaN-based device on the second AlGaN barrier layer of the GaN-based device region;
and S6, connecting the PIN diode and the Schottky diode in parallel and then connecting the PIN diode and the Schottky diode with the grid electrode of the GaN-based device through metal interconnection to obtain the wide-swing-amplitude bidirectional amplitude limiting circuit based on the gallium nitride.
2. The method according to claim 1, wherein S3 comprises:
s31, growing a doped N + layer on the GaN layer, growing an I layer on the N + layer, and growing a doped P + layer on the I layer;
s32, photoetching the P + layer, and evaporating metal to form a P + layer electrode;
s33, photoetching the P + layer and the I layer to form a groove digging region, and etching the P + layer and the I layer to the surface of the N + layer;
and S34, photoetching the N + layer, and evaporating metal to form an N + layer electrode to obtain the PIN diode.
3. The method according to claim 2, wherein S4 comprises:
s41, epitaxially growing a doped N + type GaN layer on the GaN layer;
s42, epitaxially growing a doped N-type GaN layer on the N + type GaN layer;
s43, photoetching the N-type GaN layer and evaporating the metal stack layer to form Schottky contact, and finishing the manufacture of the N-type GaN layer electrode;
s44, etching the N + type GaN layer and the N-type GaN layer to form an etching area;
and S45, photoetching the etching area and evaporating ohmic metal to form ohmic contact, and finishing the manufacture of the N + type GaN layer electrode to obtain the Schottky diode.
4. The method according to claim 3, wherein S5 comprises:
s51, evaporating ohmic metal on the second AlGaN barrier layer to form a source electrode and a drain electrode respectively;
s52, growing an SiN medium layer on the source electrode, the drain electrode and the second AlGaN barrier layer;
s53, manufacturing a mask on the SiN medium layer, and etching a groove;
and S54, photoetching a T-shaped gate region on the groove, and evaporating metal in the T-shaped gate region to form a gate to obtain the GaN-based device.
5. The method according to claim 4, wherein S6 comprises:
s61, depositing a first SiN protective layer on the surfaces of the P + layer electrode and the N + layer electrode;
s62, depositing a second SiN protective layer on the surfaces of the N-type GaN layer electrode and the N + type GaN layer electrode;
s63, depositing SiO on the source electrode, the drain electrode and the grid electrode2A protective layer;
s64, photoetching the first SiN protective layer, the second SiN protective layer and the SiO2Forming a metal interconnection layer open hole region on the protective layer, and etching the first SiN protective layer, the second SiN protective layer and the SiO of the metal interconnection layer open hole region2A protective layer;
s65, a first SiN protective layer, a second SiN protective layer and SiO in the metal interconnection layer open hole region2And evaporating interconnection metal on the protective layer, connecting the PIN diode and the Schottky diode in parallel and then connecting the PIN diode and the GaN-based device to form the wide-swing bidirectional amplitude limiting circuit based on the gallium nitride.
6. The method according to claim 2, wherein the doped N + layer has a thickness of 10 μm and a doping concentration of 1 × 1016cm-3～1×1018cm-3The doping element is Si; the thickness of the layer I is 20-70 mu m; the thickness of the doped P + layer is 1-10 μm, and the doping concentration is 1 × 1019cm-3～1×1020cm-3The doping element is Mg.
7. The method according to claim 3, wherein the doped N + GaN layer has a thickness of 10 μm to 40 μm and a doping concentration of 1018～1019cm-3(ii) a The doped N-type GaNThe thickness of the layer is 20-90 μm, and the doping concentration is 1014～1017cm-3(ii) a The Schottky contact area is 1 multiplied by 10-4cm2～4×10-4cm2。
8. The method according to claim 4, wherein the thickness of the SiN dielectric layer is 60nm to 120nm, and the gate length is 0.2 μm to 0.5 μm.
9. The method according to claim 5, wherein the first SiN protection layer is 150-200 nm thick, and the second SiN protection layer is 150-200 nm thick.
10. A wide swing bidirectional limiting circuit based on gan, produced by the method of any of claims 1-9.
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