CN114446892B - N-face GaN-based CMOS device and preparation method thereof - Google Patents

N-face GaN-based CMOS device and preparation method thereof Download PDF

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CN114446892B
CN114446892B CN202210013572.8A CN202210013572A CN114446892B CN 114446892 B CN114446892 B CN 114446892B CN 202210013572 A CN202210013572 A CN 202210013572A CN 114446892 B CN114446892 B CN 114446892B
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photoresist
layer
gan
placing
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CN114446892A (en
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武玫
牛雪锐
侯斌
杨凌
张濛
朱青
王冲
马晓华
郝跃
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Xidian University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

According to the N-face GaN-based CMOS device and the preparation method thereof, the GaN buffer layer and the p-GaN/AlGaN/GaN heterojunction are epitaxially grown on the Si substrate, the p-GaN layer of the fixed area is etched through photoetching selective area, and then the p-GaN etched groove area is filled with the insulating medium. After the above-mentioned treatment is completed, the insulating medium is chemically and mechanically polished and then bonded to the Si (100) substrate. The epitaxial layer is inverted, an n-channel device is fabricated on the region leaving the p-GaN layer, and the gate region and the p-GaN region are aligned. And meanwhile, preparing a p-channel device, and finally interconnecting drain electrodes of the n-channel device and the p-channel device to realize the CMOS device. Compared with the traditional Ga-surface p-channel device preparation process, the method can enable the p-channel device to have higher hole mobility, and the prepared CMOS structure is more optimized in characteristics.

Description

N-face GaN-based CMOS device and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to an N-face GaN-based CMOS device and a preparation method thereof.
Background
GaN, a wide bandgap semiconductor, has an excellent material quality factor, which makes it an indiscriminate choice for next generation high efficiency power devices and power electronics. Currently, gaN-based power switching devices and the like are mainly driven by Si-based CMOS, and because they are driven by CMOS prepared from different semiconductor materials, parasitic effects exist between them, so that GaN-based devices cannot fully exert their advantages, and thus research on GaN-based CMOS structures is of great importance.
The p-channel device is an important component in the CMOS structure, and the p-channel device is in the following structureThe mobility of holes in the GaN material is extremely low compared with the mobility of electrons, and the range is 5-30 cm 2 Vs. In addition, during the process of manufacturing the device, since the grooves are etched under the gate and the insulating layer is deposited, additional fixed charges and interface charges are introduced, which further reduces the mobility of holes, so that the performance of the p-channel GaN device is further reduced.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides an N-face GaN-based CMOS device and a preparation method thereof. The technical problems to be solved by the invention are realized by the following technical scheme:
in a first aspect, the present invention provides a method for manufacturing an N-face GaN-based CMOS device, including:
step 1: obtaining a Si substrate;
step 2: sequentially epitaxially growing a GaN buffer layer, a GaN layer, an AlGaN barrier layer and a p-GaN layer on the Si substrate from bottom to top by adopting an MOCVD method;
step 3: etching the n-channel device part and the p-channel device part of the p-GaN layer, so that the p-GaN layer at the n-channel device part only remains at the lower part of the n-channel gate, and etching the p-GaN layer at the p-channel to form a groove at the p-channel device part;
Step 4: depositing SiN on the sample formed in step 3 to form a SiN layer;
step 5: polishing the sample formed in the step 4, and bonding a layer of Si (100) substrate on the SiN layer;
step 6: reversing the bonded sample, and etching away the Si substrate and the GaN buffer layer;
step 7: spin-coating photoresist on a sample etched with the Si substrate and the GaN buffer layer, exposing, and etching an electric isolation region between the n-channel and the p-channel;
step 8: evaporating the first ohmic metal in a source electrode region on the sample after etching the electric isolation region to form a source electrode, and evaporating the first ohmic metal in a drain electrode region to form a drain electrode;
the first ohmic metal is formed by metals with stacked structures of four layers of Ti/Al/Ni/Au from bottom to top;
step 9: etching the GaN layer of the developing area until the AlGaN layer;
step 10: evaporating a second ohmic metal on the AlGaN layer in the source electrode region and the drain electrode region outside the AlGaN layer;
the second ohmic metal is formed by two layers of Ni and Au which are in a stacked structure from bottom to top;
step 11: depositing 20nm of Al on the sample completed in step 10 2 O 3 A layer;
step 12: etching away Al except for the n-channel portion 2 O 3 A layer exposing AlGaN of the p-channel portion, all source electrodes, and all drain electrodes;
step 13: etching a gate groove on the p-channel part gate so that the etched gate groove is aligned with the groove of the p-GaN;
step 14: evaporating gate metal in the gate groove;
the grid metal is formed by sequentially forming two layers of Ni and Au into a stacked structure from bottom to top;
step 15: growing a SiN protective layer on the sample formed in the step 14, and determining an open pore area of the metal interconnection layer on the SiN protective layer;
step 16: etching to remove the SiN protective layer in the interconnection opening area, and evaporating interconnection metal in the interconnection opening area to form an N-face GaN-based CMOS device;
the interconnection metal is formed by sequentially forming two layers of Ti and Au into a stacked structure from bottom to top.
Optionally, step 3 includes:
step 31: baking the epitaxially grown sample at 200 ℃, then placing the sample on a spin coater and dripping EPI621 photoresist on the surface of the sample substrate;
step 32: the spin conditions of the spin coater are as follows: spin speed 500rpm spin for 5 seconds; spin speed is switched to 3500rpm, spin is carried out for 40 seconds, baking is carried out at 90 ℃, and development is carried out;
step 33: after development, the film was rinsed with ultra pure water for 2 minutes and dried with nitrogen;
Step 34: performing partial etching on the p-GaN layer by using chlorine-based ICP to etch an n-channel device and a p-channel device part of the p-GaN layer, so that the p-GaN layer at the n-channel device part only remains the lower part of the n-channel and the p-GaN layer at the p-channel is etched to only more than 20nm, and forming a groove at the p-channel device part;
wherein, the etching conditions are as follows: the power of the upper electrode is 40-60W, the power of the lower electrode is 10-20W, the pressure is 5mTorr, cl 2 /BCl 3 The flow rate was 8/20sccm.
Optionally, step 4 includes:
step 41: carrying out ultrasonic cleaning on the sample formed in the step 3 for 3min with ultrasonic intensity of 2.0;
step 42: ultrasonically cleaning the sample by using ethanol for 2min, wherein the ultrasonic intensity is 2.0;
step 43: rinsing the sample with ultrapure water for 2min, and rinsing with N 2 Drying the sample;
step 44: siH with 200sccm deposition flow rate of sample after blow-drying 4 /N 2 Mixed gas, NH with flow rate of 2sccm 3 Setting deposition pressure of 600mT, deposition temperature of 250 ℃, power of about 20W and deposition time of 40min at the flow rate of 200sccm of He to form a SiN layer;
wherein, siH in the mixed gas 4 The ratio is 2%.
Optionally, the etching conditions for etching the Si substrate in step 6 are:
The power of the upper electrode is 250-350W, the power of the lower electrode is 20-40W, the pressure is 5mTorr, SF during etching 6 The flow rate is 50sccm;
the etching conditions for etching the GaN buffer layer are as follows:
etching under ICP chlorine-based condition, wherein the power of the upper electrode is 40-60W, the power of the lower electrode is 20-30W, the pressure is 5 mM, and Cl is used 2 Flow 8sccm, BCl 3 The flow rate was 20sccm.
Optionally, step 7 includes:
step 71: baking the sample formed in the step 6 on a hot plate at 200 ℃;
step 72: photoresist coating and photoresist throwing are carried out on the baked sample;
wherein, the spin coating rotating speed is 3500 revolutions per minute;
step 73: placing the sample after the spin coating on a hot plate at 90 ℃ for baking;
step 74: placing the sample baked in the step 73 into a photoetching machine to expose the photoresist in the electric isolation area;
step 75: placing the exposed sample into a developing solution to remove photoresist in the electric isolation area, and flushing the electric isolation area with ultrapure water and blowing nitrogen to dry;
step 76: sequentially etching GaN, alGaN, UID-GaN of the electric isolation region by utilizing an ICP (inductively coupled plasma) process to realize mesa isolation of the active region;
wherein the total etching depth of the electric isolation region is 200-300 nm;
step 77: sequentially placing the sample etched with the electric isolation area into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove photoresist outside the electric isolation area;
Step 78: the sample was rinsed with ultrapure water and dried with nitrogen.
Optionally, step 8 includes:
step 81: baking the sample formed in the step 7 on a hot plate at 200 ℃;
step 82: coating the stripping adhesive and throwing the adhesive on the GaN layer;
the SF6 adhesive is used in the adhesive coating and throwing process of the stripping adhesive, the rotating speed of the throwing adhesive is 2000 r/min, the duration is 40sec, and the adhesive coating and throwing adhesive thickness is 0.35 mu m;
step 83: photoresist is glued and whirl-coated on the stripping glue;
wherein, the glue spreading and throwing of the photoresist is EPI621, the throwing rotation speed is 5000 r/min, the time length is 30sec, and the glue spreading and throwing thickness is 0.77 mu m;
step 84: placing the samples subjected to glue spreading and whirl coating into a photoetching machine to expose photoresist in a source electrode area and a drain electrode area;
step 85: placing the exposed sample into a developing solution to remove photoresist and stripping glue in a source electrode area and a drain electrode area, and performing ultrapure water flushing and nitrogen blow-drying on the sample;
step 86: placing the sample of the photoetching patterns of the active electrode and the drain electrode into a plasma photoresist remover for performing bottom film treatment;
wherein the vacuumizing time of the plasma photoresist remover is 2min, O 2 The flow is 100-150 sccm, the power is 150-250W, and the treatment time of the bottom film is 5-10 min;
step 87: placing the sample processed by the bottom film into an electron beam evaporation table, and waiting for the vacuum degree of a reaction chamber of the electron beam evaporation table to reach 2 multiplied by 10 -6 Evaporating the first ohmic metal after Torr;
step 88: stripping the sample subjected to the first ohmic metal evaporation to remove the first ohmic metal, the photoresist and the stripping glue outside the source electrode region and the drain electrode region so as to form a source electrode and a drain electrode;
step 89: sequentially flushing a sample by using ultrapure water, drying by using nitrogen, and annealing;
wherein the annealing atmosphere is N 2 The annealing temperature is 800-860 ℃ and the annealing time is 30-60 s.
Optionally, step 9 includes:
step 91: placing the sample evaporated with the first ohmic metal on a hot plate at 200 ℃ for baking;
step 92: photoresist coating and photoresist throwing are carried out on a first ohmic metal sample, and then the sample is put on a hot plate at 90 ℃ for baking;
wherein, the spin coating rotating speed is 3500 revolutions per minute;
step 93: placing a sample of the first ohmic metal into a photoetching machine to expose photoresist in the partial area of the p-channel device;
step 94: placing the exposed sample into a developing solution to remove photoresist in the electrically isolated area, and performing ultrapure water flushing and nitrogen blow-drying on the sample;
Step 95: sequentially etching GaN in the development area by utilizing an ICP process until the AlGaN layer;
the etching conditions are as follows: the power of the upper electrode is 15-25W, the power of the lower electrode is 3-5W, the pressure is 5 mM, and Cl 2 Flow rate of 4sccm, BCl 3 The flow rate is 10sccm;
step 96: sequentially placing the sample into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove photoresist outside the electric isolation area;
step 97: the sample was rinsed with ultrapure water and dried with nitrogen.
Optionally, step 10 includes:
step 101: baking the sample formed in the step 9 on a hot plate at 200 ℃, and performing glue spreading and spin coating of the stripping glue;
step 102: photoresist is glued and whirl-coated on the stripping glue;
wherein, the spin coating rotating speed is 3500 revolutions per minute;
step 103: placing the sample after the spin coating on a hot plate at 90 ℃ for baking;
step 104: placing the baked sample into a photoetching machine to expose photoresist in a source electrode area and a drain electrode area of the p-channel device;
step 105: placing the exposed sample into a developing solution to remove photoresist in a source electrode area and a drain electrode area, and performing ultrapure water flushing and nitrogen blow-drying on the photoresist;
step 106: placing the sample of the photoetching patterns of the active electrode and the drain electrode into a plasma photoresist remover for performing bottom film treatment;
Wherein the vacuumizing time of the plasma photoresist remover is 2min, O 2 The flow is 100sccm, the power is 150-250W, and the treatment time of the bottom film is 5min;
step 107: placing the sample processed by the bottom film into an electron beam evaporation table, and waiting for the vacuum degree of a reaction chamber of the electron beam evaporation table to reach 2 multiplied by 10 -6 Evaporating a second ohmic metal on the AlGaN layer in the source electrode region and the drain electrode region of the p-channel device and on the photoresist outside the source electrode region and the drain electrode region after Torr;
step 108: stripping the sample subjected to the second ohmic metal evaporation to remove the second ohmic metal, the photoresist and the stripping glue outside the source electrode area and the drain electrode area to form a source electrode and a drain electrode;
step 109: sequentially flushing a sample by using ultrapure water, drying by using nitrogen, and annealing;
wherein the annealing atmosphere is O 2 The annealing temperature is 500-550 ℃, and the annealing time is 5-10 min.
Optionally, step 16 includes:
step 161: baking the sample formed in the step 15 on a hot plate at 200 ℃, and performing photoresist coating and spin coating;
wherein, the spin coating rotating speed is 3500 revolutions per minute;
step 161: placing the sample after the spin coating on a hot plate at 90 ℃ for baking;
Step 162: placing the baked sample into a photoetching machine to expose photoresist in an opening area of the metal interconnection layer;
step 163: placing the exposed sample into a developing solution to remove photoresist in an opening area of the metal interconnection layer, and flushing the exposed sample with ultrapure water and blowing the exposed sample with nitrogen;
step 164: removing the 200nm thick SiN protective layer in the opening area of the metal interconnection layer by utilizing ICP etching;
the etching conditions for removing the SiN protection layer in the metal interconnection layer open hole area are as follows: in the presence of CF as the reaction gas 4 And O 2 The pressure of the reaction chamber is l0mTorr, and the radio frequency power of the upper electrode and the lower electrode is about 100W and about l0W respectively;
step 165: baking the sample with the open area of the metal interconnection layer removed on a hot plate at 200 ℃, and then performing stripping glue spreading and spin coating on a source electrode, a drain electrode and a SiN protective layer which are not etched by the open area of the metal interconnection layer;
wherein, the thickness of the spin coating is 0.35 mu m;
step 166: placing the sample after the spin coating on a hot plate at 200 ℃ for baking;
step 167: placing the sample with the metal interconnection photoetching patterns into a plasma photoresist remover for bottom film treatment;
wherein the vacuumizing time of the plasma photoresist remover is 2min, O 2 The flow is 100-150 sccm, the power is 150-250W, and the treatment time of the bottom film is 5-10 min;
step 168: placing the sample processed by the bottom film into an electron beam evaporation table, and waiting for the vacuum degree of a reaction chamber of the electron beam evaporation table to reach 2 multiplied by 10 -6 Evaporating the interconnect metal after Torr;
step 169: and stripping the sample after the evaporation of the interconnection metal to remove the interconnection metal, photoresist and stripping adhesive outside the opening area of the metal interconnection layer, and flushing the sample with ultrapure water and drying with nitrogen.
In a second aspect, the present invention provides an N-face GaN-based CMOS device fabricated using the fabrication method of the first aspect.
According to the N-face GaN-based CMOS device and the preparation method thereof, the GaN Buffer layer and the p-GaN/AlGaN/GaN heterojunction are epitaxially grown on the Si substrate, the p-GaN layer of the fixed area is etched through photoetching selective area, and then the p-GaN etched groove area is filled with the insulating medium. After the above-mentioned treatment is completed, the insulating medium is chemically and mechanically polished and then bonded to the Si (100) substrate. The epitaxial layer is inverted, an n-channel device is fabricated on the region leaving the p-GaN layer, and the gate region and the p-GaN region are aligned. And meanwhile, preparing a p-channel device, and finally interconnecting drain electrodes of the n-channel device and the p-channel device to realize the CMOS device. Compared with the traditional Ga-surface p-channel device preparation process, the preparation method avoids the deposition of the gate dielectric layer of the p-channel device, so that extra fixed charges and interface charges introduced by the gate dielectric layer are avoided, the p-channel device has higher hole mobility, and the characteristics of the prepared CMOS structure are more optimized.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a flow chart of a method for fabricating an N-face GaN-based CMOS device according to the present invention;
FIG. 2a is a schematic diagram of a sample formed after epitaxial growth in step 2 according to the present invention;
FIG. 2b is a schematic diagram of the sample formed after the completion of step 3 according to the present invention;
FIG. 2c is a schematic diagram of the sample formed after the completion of step 4 according to the present invention;
FIG. 2d is a schematic diagram of a sample formed by bonding in step 5 according to the present invention;
FIG. 2e is a schematic diagram of the inverted FIG. 2d according to the present invention;
FIG. 2f is a schematic diagram of the sample formed after the completion of step 6 according to the present invention;
FIG. 2g is a schematic diagram of the sample formed after step 8 according to the present invention;
FIG. 2h is a schematic diagram of the sample formed after the completion of step 10 according to the present invention;
FIG. 2i is a schematic diagram of the sample formed after the completion of step 11 according to the present invention;
FIG. 2j is a schematic diagram of the sample formed after the completion of step 12 according to the present invention;
FIG. 2k is a schematic diagram of the sample formed after step 13 according to the present invention;
FIG. 2l is a schematic diagram of the sample formed after the completion of step 14 according to the present invention;
fig. 2m is a schematic structural diagram of an N-plane GaN-based CMOS device finally formed according to the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
As shown in fig. 1, the preparation method of the N-face GaN-based CMOS device provided by the invention comprises the following steps:
step 1: obtaining a Si substrate;
among them, si (111) -based substrates can be used as Si substrates.
Step 2: sequentially epitaxially growing a GaN buffer layer, a GaN layer, an AlGaN barrier layer and a p-GaN layer on the Si substrate from bottom to top by adopting an MOCVD method;
as shown in FIG. 2, the epitaxial growth of the invention sequentially comprises a Si (111) substrate, a GaN buffer layer, a GaN layer, an AlGaN barrier layer and a p-GaN layer from bottom to top.
Step 3: etching the n-channel device part and the p-channel device part of the p-GaN layer, so that the p-GaN layer at the n-channel device part only remains at the lower part of the n-channel gate, and etching the p-GaN layer at the p-channel to form a groove at the p-channel device part;
as shown in fig. 2b, this step is divided into n-channel device portion p-GaN etching and p-channel device portion p-GaN recess etching.
In the p-GaN etching process of the n-channel device part, firstly, a sample is placed at 200 ℃ for baking, then is placed on a spin coater, EPI621 photoresist is dripped on the surface of a sample substrate, and a spin coater piece is arranged: 500rpm,5 seconds, 3500rpm,40 seconds, baked at 90℃and developed. The solution was rinsed with ultrapure water for 2 minutes and dried with nitrogen. Chlorine based ICP etching was used. Etching conditions: the power of the upper electrode is 40-60W, the power of the lower electrode is 10-20W, the pressure is 5mTorr, cl 2 /BCl 3 The flow rate was 8/20sccm. The p-GaN is etched such that the p-GaN remains only in the lower portion of the n-channel.
In the etching process of the p-GaN groove of the p-channel device part, firstly, a sample is placed at 200 ℃ for baking, then is placed on a spin coater, EPI621 photoresist is dripped on the surface of a sample substrate, and a spin coater piece is arranged: 500rpm,5 seconds, 3500rpm,40 seconds, baked at 90℃and developed. The solution was rinsed with ultrapure water for 2 minutes and dried with nitrogen. Chlorine based ICP etching was used. Etching conditions: the power of the upper electrode is 40-60W, the power of the lower electrode is 10-20W, the pressure is 5mTorr, cl 2 /BCl 3 The flow rate was 8/20sccm. The p-GaN is etched to a remaining about 20nm.
Step 4: depositing SiN on the sample formed in step 3 to form a SiN layer;
as shown in fig. 2c, the present step process includes: cleaning, acetone, and ultrasonic treatment for 3min, wherein the ultrasonic intensity is 2.0; ethanol, ultrasonic treatment for 2min, and ultrasonic intensity of 2.0; washing with ultrapure water for 2min; n (N) 2 And (5) blow-drying. Deposition of (2% SiH) 4 /N 2 )＝200sccm，NH 3 2sccm, he=200 sccm, a pressure of about 600mT, a temperature of 250 degrees celsius, a power of about 20W, and a deposition time of about 40 min.
Step 5: polishing the sample formed in the step 4, and bonding a layer of Si (100) substrate on the SiN layer;
as shown in fig. 2d, this step bonds a layer of Si (100) substrate on the basis of fig. 2 c.
Step 6: reversing the bonded sample, and etching away the Si substrate and the GaN buffer layer;
after the product of fig. 2d is turned over, as shown in fig. 2e, the etching conditions for etching the Si substrate and the GaN buffer layer in this step are: the power of the upper electrode is 250-350W, the power of the lower electrode is 20-40W, the pressure is 5mTorr, SF 6 The flow rate was 50sccm. Etching the upper GaN buffer layer by using ICP chlorine-based condition etching, wherein the etching conditions are as follows: the power of the upper electrode is 40-60W, the power of the lower electrode is 20-30W, the pressure is 5 mM, the Cl2 flow is 8sccm, and the BCl3 flow is 20sccm.
Step 7: spin-coating photoresist on a sample etched with the Si substrate and the GaN buffer layer, exposing, and etching an electric isolation region between the n-channel and the p-channel;
firstly, placing a sample on a hot plate at 200 ℃ for baking; performing photoresist coating and spin coating, wherein the spin coating rotating speed is 3500 rpm, and placing the sample on a hot plate at 90 ℃ for baking; placing the sample into a photoetching machine to expose the photoresist in the electric isolation area; and placing the exposed sample into a developing solution to remove the photoresist in the electrically isolated area, and flushing the sample with ultrapure water and blowing the sample with nitrogen. As shown in fig. 2f, the mesa isolation of the active region is realized by sequentially etching GaN, alGaN, UID-GaN of the electrically isolated region by ICP process, and the total etching depth is about 200-300 nm. Then, sequentially placing the sample into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove photoresist outside the electric isolation area; finally, the sample was rinsed with ultrapure water and dried with nitrogen.
Step 8: evaporating the first ohmic metal in a source electrode region on the sample after etching the electric isolation region to form a source electrode, and evaporating the first ohmic metal in a drain electrode region to form a drain electrode;
the first ohmic metal is composed of metals with stacked structures of four layers of Ti/Al/Ni/Au from bottom to top.
The step comprises first bonding an epitaxial substrate(sample after etching isolation region) baking on hot plate at 200deg.C; then, the coating and the spin coating of the stripping adhesive are carried out on the GaN layer, and SF is used 6 The glue was formed at a spin rate of 2000 rpm for 40sec and a thickness of 0.35 μm. The hot plate was then applied at 200℃to the resist on a stripper, followed by spreading and throwing of the resist, EPI621, 5000 rpm for 30sec to give a resist thickness of 0.77. Mu.m. After baking by a hot plate, placing the samples subjected to glue spreading and whirling into a photoetching machine to expose photoresist in a source electrode area and a drain electrode area; and finally, placing the exposed sample into a developing solution to remove photoresist and stripping glue in the source electrode area and the drain electrode area, and performing ultrapure water flushing and nitrogen blow-drying on the sample. Then the process of evaporating source electrode and drain electrode is carried out: putting the sample of the photoetching patterns of the active electrode and the drain electrode into a plasma photoresist remover for performing bottom film treatment, vacuumizing the alpha-plasma photoresist remover for 2min, and performing O 2 The flow is 100-150 sccm, the power is 150-250W, and the flow is 5-10 min; then, the sample is put into an electron beam evaporation table, and the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10 -6 Evaporating ohmic metal after Torr, wherein the ohmic metal is a metal stack structure which is formed by four layers of metals of Ti/Al/Ni/Au from bottom to top in sequence; then, stripping the sample subjected to ohmic metal evaporation to remove ohmic metal, photoresist and stripping glue outside the source electrode area and the drain electrode area; finally, the sample was rinsed with ultrapure water and blown dry with nitrogen and annealed. The annealing atmosphere is N 2 The annealing temperature is 800-860 ℃ and the annealing time is 30-60 s, and the formed sample is shown in figure 2 g.
Step 9: etching the GaN layer of the developing area until the AlGaN layer;
firstly, placing a sample on a hot plate at 200 ℃ for baking; then, photoresist is coated and spun, the spin speed of the photoresist is 3500 rpm, and the sample is baked on a hot plate at 90 ℃; then, placing the sample into a photoetching machine to expose photoresist in the partial region of the p-channel device; then, the exposed sample was put into a developing solution to remove the photoresist in the electrically isolated region, and subjected to ultra-pure water rinsing and nitrogen blow-dry. Then GaN in the developed region is etched sequentially by ICP process until AlGaN layer. Conditions are as follows: the power of the upper electrode is 15-25W, the power of the lower electrode is 3-5W, the pressure is 5 mM, cl 2 Flow rate 4sccm, BCl 3 The flow rate is 10sccm; then, sequentially placing the sample into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove photoresist outside the electric isolation area; finally, the sample was rinsed with ultrapure water and dried with nitrogen.
Step 10: evaporating a second ohmic metal on the AlGaN layer in the source electrode region and the drain electrode region outside the AlGaN layer;
the second ohmic metal is formed by two layers of Ni and Au which are in a stacked structure from bottom to top;
firstly, placing a sample on a hot plate at 200 ℃ for baking; then, photoresist is coated and spun, the spin speed of the photoresist is 3500 rpm, and the sample is baked on a hot plate at 90 ℃; then, placing the sample into a photoetching machine to expose photoresist in the source-drain part area of the p-channel device; then, the exposed sample was put into a developing solution to remove the photoresist in the electrically isolated region, and subjected to ultra-pure water rinsing and nitrogen blow-dry. Then, the AlGaN layer of the development region is etched by ICP process until it reaches the p-GaN layer. Conditions are as follows: the power of the upper electrode is 15-25W, the power of the lower electrode is 3-5W, the pressure is 5 mM, cl 2 Flow rate 4sccm, BCl 3 The flow rate is 10sccm; then, sequentially placing the sample into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove photoresist outside the electric isolation area; finally, the sample was rinsed with ultrapure water and dried with nitrogen. Continuing the process of photoetching the source-drain electrode region: placing the sample on a hot plate at 200 ℃ for baking; then, the samples were subjected to spreading and spin coating with a spin coating thickness of 0.35 μm, and baked on a hot plate at 200deg.C using SF 6 The glue was formed at a speed of 2000 rpm for 40sec to a thickness of 0.35 μm. Baking by a hot plate; next, photoresist coating and spin coating were performed on the resist, and EPI621 was used at 5000 rpm for 30sec to form a thickness of 0.77. Mu.m. Baking by a hot plate at 90 degrees; then, putting the sample with the glue coating and the spin coating into a photoetching machineExposing the photoresist in the source electrode region and the drain electrode region; and finally, placing the exposed sample into a developing solution to remove photoresist and stripping glue in the source electrode area and the drain electrode area, and performing ultrapure water flushing and nitrogen blow-drying on the sample. And continuing the process of evaporating the source electrode and the drain electrode: putting the sample of the photoetching patterns of the active electrode and the drain electrode into a plasma photoresist remover for performing bottom film treatment, vacuumizing the alpha-plasma photoresist remover for 2min, and performing O 2 The flow is 100sccm, the power is 150-250W, and the time is 5min; then, the sample is put into an electron beam evaporation table, and the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10 -6 Evaporating ohmic metal on the AlGaN layer in the source electrode region and the drain electrode region and on the photoresist outside the source electrode region and the drain electrode region after Torr, wherein the ohmic metal is a metal laminated structure consisting of two layers of Ni and Au in sequence from bottom to top; then, stripping the sample subjected to ohmic metal evaporation to remove ohmic metal, photoresist and stripping glue outside the source electrode area and the drain electrode area; finally, the sample was rinsed with ultrapure water and blown dry with nitrogen and annealed. The annealing atmosphere is O 2 The annealing temperature is 500-550 ℃, the annealing time is 5-10 min, and the formed sample is shown in figure 2 h.
Step 11: depositing 20nm of Al on the sample completed in step 10 2 O 3 A layer;
the sample formed by this step of deposition is shown in figure 2 i.
Step 12: etching away Al except for the n-channel portion 2 O 3 A layer exposing AlGaN of the p-channel portion, all source electrodes, and all drain electrodes;
in the step, aluminum oxide except for an n-channel part is etched to expose AlGaN of a p-channel device part and all source and drain electrodes, wherein the etching conditions are F-based etching, and the conditions are as follows: the power of the upper electrode is 100-200W, the power of the lower electrode is 30-40W, the pressure is 10mT, CF 4 The flow rate was 45sccm and the sample formed is shown in FIG. 2 j.
Step 13: etching a gate groove on the p-channel part gate so that the etched gate groove is aligned with the groove of the p-GaN;
the gate recess of this step is aligned with the recess of p-GaN. And etching the AlGaN layer by chlorine-based ICP for 5-15 nm. The conditions are as follows: the power of the upper electrode is 15-25W, the power of the lower electrode is 3-5W, the pressure is 5 mM, cl 2 Flow rate 4sccm, BCl 3 The flow rate was 10sccm and the sample formed is shown in FIG. 2 k.
Step 14: evaporating gate metal in the gate groove;
the grid metal is formed by sequentially forming two layers of Ni and Au into a stacked structure from bottom to top;
firstly, placing a sample with a grid electrode photoetching pattern into a plasma photoresist remover for bottom film treatment, vacuumizing the alpha-plasma photoresist remover for 2min, and performing O 2 The flow is 100sccm, the power is 150-250W, and the time is 5min; then, the sample is put into an electron beam evaporation table, and the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10 -6 Evaporating gate metal on the photoresist inside and outside the gate electrode region after Torr, wherein the gate metal is of a metal laminated structure which is formed by Ni and Au layers of metal sequentially from bottom to top; then, stripping the sample subjected to the evaporation of the gate metal to remove the gate metal, the photoresist and the stripping adhesive outside the gate electrode area; finally, the sample was rinsed with ultrapure water and dried with nitrogen, and the resulting sample was as shown in FIG. 2 l.
Step 15: growing a SiN protective layer on the sample formed in the step 14, and determining an open pore area of the metal interconnection layer on the SiN protective layer;
the step of growing SiN protective layer with 200nm thickness by PECVD process comprises NH 3 And SiH 4 As a reaction gas, the temperature of the substrate is about 250 ℃, the pressure of the reaction chamber is 600mTorr, and the radio frequency power is 20-25W.
Step 16: etching to remove the SiN protective layer in the interconnection opening area, and evaporating interconnection metal in the interconnection opening area to form an N-face GaN-based CMOS device;
the interconnection metal is formed by sequentially forming two layers of Ti and Au into a stacked structure from bottom to top.
Photoetching a metal interconnection layer open pore area on a SiN protective layer, and firstly, placing a sample on a hot plate at 200 ℃ for baking; thenPerforming photoresist coating and spin coating, using EPI621, spin coating at 3500 rpm, and baking the sample on a hot plate at 90deg.C; then, placing the sample into a photoetching machine to expose photoresist in the opening area of the metal interconnection layer; and finally, placing the exposed sample into a developing solution to remove the photoresist in the interconnection opening area, and flushing the exposed sample with ultrapure water and drying the exposed sample with nitrogen. ICP etching is used. In the presence of CF as the reaction gas 4 And O 2 And removing the 200nm thick SiN protective layer in the interconnection open hole area under the conditions that the pressure of the reaction chamber is l0mTorr and the radio frequency power of the upper electrode and the lower electrode is about 100W and about l0W respectively. Continuing to photoetching an opening area of the metal interconnection layer on the SiN protective layer:
firstly, placing a sample subjected to hole etching of a metal interconnection layer on a hot plate at 200 ℃ for baking; then, the source electrode and the drain electrode of the open area of the metal interconnection layer and the SiN protective layer which is not etched by the open area are subjected to glue spreading and spin coating of stripping glue, the spin coating thickness is 0.35 mu m, and a sample is placed on a hot plate at 200 ℃ for baking; then, photoresist is coated and spun on the stripping adhesive, the thickness of the spun photoresist is 0.77 mu m, and the sample is put on a hot plate at 90 ℃ for baking; then, placing the sample with the glue spreading and the spin coating into a photoetching machine to expose the photoresist in the metal interconnection area; and finally, placing the exposed sample into a developing solution to remove photoresist and stripping adhesive in the opening area of the metal interconnection layer, and performing ultrapure water flushing and nitrogen blow-drying on the photoresist and the stripping adhesive. Continuing to evaporate the metal interconnection, wherein the steps are as follows: firstly, placing a sample with a metal interconnection photoetching pattern into a plasma photoresist remover for performing bottom film treatment, vacuumizing the alpha-plasma photoresist remover for 2min, and performing O 2 The flow is 100-150 sccm, the power is 150-250W, and the flow is 5-10 min; then, the sample is put into an electron beam evaporation table, and the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10 -6 Evaporating interconnection metal after Torr, wherein the interconnection metal is a metal stack structure composed of two layers of metals of Ti and Au from bottom to top in sequence; then, stripping the sample after the interconnection metal evaporation is completed to remove interconnection metal, photoresist and stripping glue outside the opening area of the metal interconnection layer; finally, usingThe sample was rinsed with ultrapure water and dried with nitrogen gas, and an N-face GaN-based CMOS device was formed as shown in fig. 2 m.
According to the preparation method of the N-face GaN-based CMOS device, the GaN Buffer layer and the p-GaN/AlGaN/GaN heterojunction are epitaxially grown on the Si substrate, the p-GaN layer of the fixed area is etched through photoetching selective area, and then the p-GaN etched groove area is filled with the insulating medium. After the above-mentioned treatment is completed, the insulating medium is chemically and mechanically polished and then bonded to the Si (100) substrate. The epitaxial layer is inverted, an n-channel device is fabricated on the region leaving the p-GaN layer, and the gate region and the p-GaN region are aligned. And meanwhile, preparing a p-channel device, and finally interconnecting drain electrodes of the n-channel device and the p-channel device to realize the CMOS device. Compared with the traditional Ga-surface p-channel device preparation process, the preparation method avoids the deposition of the gate dielectric layer of the p-channel device, so that extra fixed charges and interface charges introduced by the gate dielectric layer are avoided, the p-channel device has higher hole mobility, and the characteristics of the prepared CMOS structure are more optimized.
As an alternative embodiment of the present invention, step 3 includes:
step 31: baking the epitaxially grown sample at 200 ℃, then placing the sample on a spin coater and dripping EPI621 photoresist on the surface of the sample substrate;
step 32: the spin conditions of the spin coater are as follows: spin speed 500rpm spin for 5 seconds; spin speed is switched to 3500rpm, spin is carried out for 40 seconds, baking is carried out at 90 ℃, and development is carried out;
step 33: after development, the film was rinsed with ultra pure water for 2 minutes and dried with nitrogen;
step 34: performing partial etching on the p-GaN layer by using chlorine-based ICP (inductively coupled plasma) to etch an n-channel device part and a p-channel device part of the p-GaN layer so as to enable the p-GaN layer on the n-channel device part to only remain the lower part of the n-channel and the p-GaN layer etched to only more than 20nm on the p-channel so as to form a groove on the p-channel device part;
wherein, the etching conditions are as follows: the power of the upper electrode is 40-60W, the power of the lower electrode is 10-20W, the pressure is 5mTorr, cl 2 /BCl 3 The flow rate was 8/20sccm.
As an alternative embodiment of the present invention, step 4 includes:
step 41: carrying out ultrasonic cleaning on the sample formed in the step 3 for 3min with ultrasonic intensity of 2.0;
step 42: ultrasonically cleaning the sample by using ethanol for 2min, wherein the ultrasonic intensity is 2.0;
Step 43: rinsing the sample with ultrapure water for 2min, and rinsing with N 2 Drying the sample;
step 44: siH with 200sccm deposition flow rate of sample after blow-drying 4 /N 2 Mixed gas, NH with flow rate of 2sccm 3 N2 with the flow of 0sccm and He with the flow of 200sccm are arranged, the deposition pressure is set to be 600mT, the temperature is set to be 250 ℃, the power is about 20W, and the deposition time is set to be 40min, so that a SiN layer is formed;
wherein, siH in the mixed gas 4 The ratio is 2%.
As an alternative embodiment of the present invention, the etching conditions for etching the Si substrate in step 6 are:
the power of the upper electrode is 250-350W, the power of the lower electrode is 20-40W, the pressure is 5mTorr, SF during etching 6 The flow rate is 50sccm;
the etching conditions for etching the GaN buffer layer are as follows:
etching under ICP chlorine-based condition, wherein the power of the upper electrode is 40-60W, the power of the lower electrode is 20-30W, the pressure is 5 mM, and Cl is used 2 Flow 8sccm, BCl 3 The flow rate was 20sccm.
As an alternative embodiment of the present invention, step 7 includes:
step 71: baking the sample formed in the step 6 on a hot plate at 200 ℃;
step 72: photoresist coating and photoresist throwing are carried out on the baked sample;
wherein, the spin coating rotating speed is 3500 revolutions per minute;
Step 73: placing the sample after the spin coating on a hot plate at 90 ℃ for baking;
step 74: placing the sample baked in the step 73 into a photoetching machine to expose the photoresist in the electric isolation area;
step 75: placing the exposed sample into a developing solution to remove photoresist in the electric isolation area, and flushing the electric isolation area with ultrapure water and blowing nitrogen to dry;
step 76: sequentially etching GaN, alGaN, UID-GaN of the electric isolation region by utilizing an ICP (inductively coupled plasma) process to realize mesa isolation of the active region;
wherein the total etching depth of the electric isolation region is 200-300 nm;
step 77: sequentially placing the sample etched with the electric isolation area into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove photoresist outside the electric isolation area;
step 78: the sample was rinsed with ultrapure water and dried with nitrogen.
As an alternative embodiment of the present invention, step 8 includes:
step 81: baking the sample formed in the step 7 on a hot plate at 200 ℃;
step 82: coating the stripping adhesive and throwing the adhesive on the GaN layer;
wherein, the glue spreading and throwing glue of the stripping glue is as follows: SF (sulfur hexafluoride) 6 The spin coating rotating speed is 2000 rpm, the duration is 40sec, and the glue coating and spin coating thickness is 0.35 mu m;
Step 83: photoresist is glued and whirl-coated on the stripping glue;
wherein, the glue spreading and throwing of the photoresist is EPI621, the throwing rotation speed is 5000 r/min, the time length is 30sec, and the glue spreading and throwing thickness is 0.77 mu m;
step 84: placing the samples subjected to glue spreading and whirl coating into a photoetching machine to expose photoresist in a source electrode area and a drain electrode area;
step 85: placing the exposed sample into a developing solution to remove photoresist and stripping glue in a source electrode area and a drain electrode area, and performing ultrapure water flushing and nitrogen blow-drying on the sample;
step 86: placing the sample of the photoetching patterns of the active electrode and the drain electrode into a plasma photoresist remover for performing bottom film treatment;
wherein the vacuumizing time of the plasma photoresist remover is 2min, O 2 The flow is 100-150 sccm, the power is 150-250W, and the treatment time of the bottom film is 5-10 min;
step 87: placing the sample processed by the bottom film into an electron beam evaporation table, and waiting for the vacuum degree of a reaction chamber of the electron beam evaporation table to reach 2 multiplied by 10 -6 Evaporating the first ohmic metal after Torr;
step 88: stripping the sample subjected to the first ohmic metal evaporation to remove the first ohmic metal, the photoresist and the stripping glue outside the source electrode region and the drain electrode region so as to form a source electrode and a drain electrode;
Step 89: sequentially flushing a sample by using ultrapure water, drying by using nitrogen, and annealing;
wherein the annealing atmosphere is N 2 The annealing temperature is 800-860 ℃ and the annealing time is 30-60 s.
As an alternative embodiment of the present invention, step 9 includes:
step 91: placing the sample evaporated with the first ohmic metal on a hot plate at 200 ℃ for baking;
step 92: photoresist coating and photoresist throwing are carried out on a first ohmic metal sample, and then the sample is put on a hot plate at 90 ℃ for baking;
wherein, the spin coating rotating speed is 3500 revolutions per minute;
step 93: placing a sample of the first ohmic metal into a photoetching machine to expose photoresist in the partial area of the p-channel device;
step 94: placing the exposed sample into a developing solution to remove photoresist in the electrically isolated area, and performing ultrapure water flushing and nitrogen blow-drying on the sample;
step 95: sequentially etching GaN in the development area by utilizing an ICP process until the AlGaN layer;
the etching conditions are as follows: the power of the upper electrode is 15-25W, the power of the lower electrode is 3-5W, the pressure is 5 mM, and Cl 2 Flow rate of 4sccm, BCl 3 The flow rate is 10sccm;
step 96: sequentially placing the sample into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove photoresist outside the electric isolation area;
Step 97: the sample was rinsed with ultrapure water and dried with nitrogen.
As an alternative embodiment of the present invention, step 10 includes:
step 101: baking the sample formed in the step 9 on a hot plate at 200 ℃, and performing glue spreading and spin coating of the stripping glue;
step 102: photoresist is glued and whirl-coated on the stripping glue;
wherein, the spin coating rotating speed is 3500 revolutions per minute;
step 103: placing the sample after the spin coating on a hot plate at 90 ℃ for baking;
step 104: placing the baked sample into a photoetching machine to expose photoresist in a source electrode area and a drain electrode area of the p-channel device;
step 105: placing the exposed sample into a developing solution to remove photoresist in a source electrode area and a drain electrode area, and performing ultrapure water flushing and nitrogen blow-drying on the photoresist;
step 106: placing the sample of the photoetching patterns of the active electrode and the drain electrode into a plasma photoresist remover for performing bottom film treatment;
wherein the vacuumizing time of the plasma photoresist remover is 2min, O 2 The flow is 100sccm, the power is 150-250W, and the treatment time of the bottom film is 5min;
step 107: placing the sample processed by the bottom film into an electron beam evaporation table, and waiting for the vacuum degree of a reaction chamber of the electron beam evaporation table to reach 2 multiplied by 10 -6 Evaporating a second ohmic metal on the AlGaN layer in the source electrode region and the drain electrode region of the p-channel device and on the photoresist outside the source electrode region and the drain electrode region after Torr;
step 108: stripping the sample subjected to the second ohmic metal evaporation to remove the second ohmic metal, the photoresist and the stripping glue outside the source electrode area and the drain electrode area to form a source electrode and a drain electrode;
step 109: sequentially flushing a sample by using ultrapure water, drying by using nitrogen, and annealing;
wherein the annealing atmosphere is O 2 The annealing temperature is 500-550 ℃, and the annealing time is 5-10 min.
As an alternative embodiment of the present invention, step 16 includes:
step 161: baking the sample formed in the step 15 on a hot plate at 200 ℃, and performing photoresist coating and spin coating;
wherein, the spin coating rotating speed is 3500 revolutions per minute;
step 161: placing the sample after the spin coating on a hot plate at 90 ℃ for baking;
step 162: placing the baked sample into a photoetching machine to expose photoresist in an opening area of the metal interconnection layer;
step 163: placing the exposed sample into a developing solution to remove photoresist in an opening area of the metal interconnection layer, and flushing the exposed sample with ultrapure water and blowing the exposed sample with nitrogen;
Step 164: removing the 200nm thick SiN protective layer in the opening area of the metal interconnection layer by utilizing ICP etching;
the etching conditions for removing the SiN protection layer in the metal interconnection layer open hole area are as follows: the reaction gas is CF4 and O2, the pressure of the reaction chamber is l0mTorr, and the radio frequency power of the upper electrode and the lower electrode is about 100W and about l0W respectively;
step 165: baking the sample with the open area of the metal interconnection layer removed on a hot plate at 200 ℃, and then performing stripping glue spreading and spin coating on a source electrode, a drain electrode and a SiN protective layer which are not etched by the open area of the metal interconnection layer;
wherein, the thickness of the spin coating is 0.35 mu m;
step 166: placing the sample after the spin coating on a hot plate at 200 ℃ for baking;
step 167: placing the sample with the metal interconnection photoetching patterns into a plasma photoresist remover for bottom film treatment;
wherein the vacuumizing time of the plasma photoresist remover is 2min, O 2 The flow is 100-150 sccm, the power is 150-250W, and the bottom film is processedThe length is 5-10 min;
step 168: placing the sample processed by the bottom film into an electron beam evaporation table, and waiting for the vacuum degree of a reaction chamber of the electron beam evaporation table to reach 2 multiplied by 10 -6 Evaporating the interconnect metal after Torr;
Step 169: and stripping the sample after the evaporation of the interconnection metal to remove the interconnection metal, photoresist and stripping adhesive outside the opening area of the metal interconnection layer, and flushing the sample with ultrapure water and drying with nitrogen.
As shown in FIG. 2m, the N-face GaN-based CMOS device provided by the invention is prepared by using the preparation method of the N-face GaN-based CMOS device.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (10)

1. The preparation method of the N-face GaN-based CMOS device is characterized by comprising the following steps:
step 1: obtaining a Si substrate;
step 2: sequentially epitaxially growing a GaN buffer layer, a GaN layer, an AlGaN barrier layer and a p-GaN layer on the Si substrate from bottom to top by adopting an MOCVD method;
step 3: etching the n-channel device part and the p-channel device part of the p-GaN layer, so that the p-GaN layer in the n-channel device part only remains the lower part of the n-channel gate, and etching the p-GaN layer in the p-channel to form a groove in the p-channel device part;
Step 4: depositing SiN on the sample formed in step 3 to form a SiN layer;
step 5: polishing the sample formed in the step 4, and bonding a layer of Si (100) substrate on the SiN layer; wherein 100 in Si (100) represents a lattice orientation;
step 6: reversing the bonded sample, and etching away the Si substrate and the GaN buffer layer;
step 7: spin-coating photoresist on a sample etched with the Si substrate and the GaN buffer layer, exposing, and etching an electric isolation region between the n-channel and the p-channel;
step 8: evaporating the first ohmic metal in a source electrode region on the sample after etching the electric isolation region to form a source electrode, and evaporating the first ohmic metal in a drain electrode region to form a drain electrode;
the first ohmic metal is formed by metals with stacked structures of four layers of Ti/Al/Ni/Au from bottom to top;
step 9: etching the GaN layer of the developing area until the AlGaN layer;
step 10: evaporating a second ohmic metal on the AlGaN layer in the source electrode region and the drain electrode region outside the AlGaN layer;
the second ohmic metal is formed by two layers of Ni and Au which are in a stacked structure from bottom to top;
step 11: depositing 20nm of Al on the sample completed in step 10 2 O 3 A layer;
step 12: etching away Al except for the n-channel portion 2 O 3 A layer exposing AlGaN of the p-channel portion, all source electrodes, and all drain electrodes;
step 13: etching a gate groove on the p-channel part gate so that the etched gate groove is aligned with the groove of the p-GaN;
step 14: evaporating gate metal in the gate groove;
the grid metal is formed by sequentially forming two layers of Ni and Au into a stacked structure from bottom to top;
step 15: growing a SiN protective layer on the sample formed in the step 14, and determining an open pore area of the metal interconnection layer on the SiN protective layer;
step 16: etching to remove the SiN protective layer in the interconnection opening area, and evaporating interconnection metal in the interconnection opening area to form an N-face GaN-based CMOS device;
the interconnection metal is formed by sequentially forming two layers of Ti and Au into a stacked structure from bottom to top.
2. The method for fabricating an N-plane GaN-based CMOS device of claim 1, wherein step 3 comprises:
step 31: baking the epitaxially grown sample at 200 ℃, then placing the sample on a spin coater and dripping EPI621 photoresist on the surface of the sample substrate;
step 32: the spin conditions of the spin coater are as follows: spin speed 500rpm spin for 5 seconds; spin speed is switched to 3500rpm, spin is carried out for 40 seconds, baking is carried out at 90 ℃, and development is carried out;
Step 33: after development, the film was rinsed with ultra pure water for 2 minutes and dried with nitrogen;
step 34: performing partial etching on the p-GaN layer by using chlorine-based ICP to etch an n-channel device and a p-channel device part of the p-GaN layer, so that the p-GaN layer of the n-channel device part only remains a lower part of an n-channel and the p-GaN layer is etched to only 20nm in the p-channel, and forming a groove in the p-channel device part;
wherein, the etching conditions are as follows: the power of the upper electrode is 40-60W, the power of the lower electrode is 10-20W, the pressure is 5mTorr, cl 2 /BCl 3 The flow rate was 8/20sccm.
3. The method for fabricating an N-plane GaN-based CMOS device of claim 1, wherein step 4 comprises:
step 41: carrying out ultrasonic cleaning on the sample formed in the step 3 for 3min with ultrasonic intensity of 2.0;
step 42: ultrasonically cleaning the sample by using ethanol for 2min, wherein the ultrasonic intensity is 2.0;
step 43: rinsing the sample with ultrapure water for 2min, and rinsing with N 2 Drying the sample;
step 44: siH with 200sccm deposition flow rate of sample after blow-drying 4 /N 2 Mixed gas, NH with flow rate of 2sccm 3 Setting deposition pressure of 600mT, deposition temperature of 250 ℃, power of 20W and deposition time of 40min at the flow rate of 200sccm of He to form a SiN layer;
Wherein, siH in the mixed gas 4 The ratio is 2%.
4. The method for fabricating an N-plane GaN-based CMOS device of claim 1, wherein the etching conditions for etching away the Si substrate in step 6 are:
the power of the upper electrode is 250-350W, the power of the lower electrode is 20-40W, the pressure is 5mTorr, SF during etching 6 The flow rate is 50sccm;
the etching conditions for etching the GaN buffer layer are as follows:
etching under ICP chlorine-based condition, wherein the power of the upper electrode is 40-60W, the power of the lower electrode is 20-30W, the pressure is 5 mM, and Cl is used 2 Flow 8sccm, BCl 3 The flow rate was 20sccm.
5. The method for fabricating an N-plane GaN-based CMOS device of claim 1, wherein said step 7 comprises:
step 71: baking the sample formed in the step 6 on a hot plate at 200 ℃;
step 72: photoresist coating and photoresist throwing are carried out on the baked sample;
wherein, the spin coating rotating speed is 3500 revolutions per minute;
step 73: placing the sample after the spin coating on a hot plate at 90 ℃ for baking;
step 74: placing the sample baked in the step 73 into a photoetching machine to expose the photoresist in the electric isolation area;
step 75: placing the exposed sample into a developing solution to remove photoresist in the electric isolation area, and flushing the electric isolation area with ultrapure water and blowing nitrogen to dry;
Step 76: sequentially etching GaN, alGaN, UID-GaN of the electric isolation region by utilizing an ICP (inductively coupled plasma) process to realize mesa isolation of the active region;
wherein the total etching depth of the electric isolation region is 200-300 nm;
step 77: sequentially placing the sample etched with the electric isolation area into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove photoresist outside the electric isolation area;
step 78: the sample was rinsed with ultrapure water and dried with nitrogen.
6. The method for fabricating an N-plane GaN-based CMOS device of claim 1, wherein step 8 comprises:
step 81: baking the sample formed in the step 7 on a hot plate at 200 ℃;
step 82: coating the stripping adhesive and throwing the adhesive on the GaN layer;
wherein SF is used in the processes of gluing and spin-coating of the stripping adhesive 6 The spin-coating speed is 2000 rpm, the duration is 40sec, and the thickness of the glue coating and spin-coating is 0.35 mu m;
step 83: photoresist is glued and whirl-coated on the stripping glue;
wherein, the glue spreading and throwing of the photoresist is EPI621, the throwing rotation speed is 5000 r/min, the time length is 30sec, and the glue spreading and throwing thickness is 0.77 mu m;
step 84: placing the samples subjected to glue spreading and whirl coating into a photoetching machine to expose photoresist in a source electrode area and a drain electrode area;
Step 85: placing the exposed sample into a developing solution to remove photoresist and stripping glue in a source electrode area and a drain electrode area, and performing ultrapure water flushing and nitrogen blow-drying on the sample;
step 86: placing the sample of the photoetching patterns of the active electrode and the drain electrode into a plasma photoresist remover for performing bottom film treatment;
wherein the vacuumizing time of the plasma photoresist remover is 2min, O 2 The flow is 100-150 sccm, the power is 150-250W, and the treatment time of the bottom film is 5-10 min;
step 87: placing the sample processed by the bottom film into an electron beam evaporation table, and waiting for the vacuum degree of a reaction chamber of the electron beam evaporation table to reach 2 multiplied by 10 -6 Evaporating the first ohmic metal after Torr;
step 88: stripping the sample subjected to the first ohmic metal evaporation to remove the first ohmic metal, the photoresist and the stripping glue outside the source electrode region and the drain electrode region so as to form a source electrode and a drain electrode;
step 89: sequentially flushing a sample by using ultrapure water, drying by using nitrogen, and annealing;
wherein the annealing atmosphere is N 2 The annealing temperature is 800-860 ℃ and the annealing time is 30-60 s.
7. The method for fabricating an N-plane GaN-based CMOS device of claim 1, wherein step 9 comprises:
Step 91: placing the sample evaporated with the first ohmic metal on a hot plate at 200 ℃ for baking;
step 92: photoresist coating and photoresist throwing are carried out on a first ohmic metal sample, and then the sample is put on a hot plate at 90 ℃ for baking;
wherein, the spin coating rotating speed is 3500 revolutions per minute;
step 93: placing a sample of the first ohmic metal into a photoetching machine to expose photoresist in the partial area of the p-channel device;
step 94: placing the exposed sample into a developing solution to remove photoresist in the electrically isolated area, and performing ultrapure water flushing and nitrogen blow-drying on the sample;
step 95: sequentially etching GaN in the development area by utilizing an ICP process until the AlGaN layer;
the etching conditions are as follows: the power of the upper electrode is 15-25W, the power of the lower electrode is 3-5W, the pressure is 5 mM, and Cl 2 Flow rate of 4sccm, BCl 3 The flow rate is 10sccm;
step 96: sequentially placing the sample into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove photoresist outside the electric isolation area;
step 97: the sample was rinsed with ultrapure water and dried with nitrogen.
8. The method for fabricating an N-plane GaN-based CMOS device of claim 1, wherein said step 10 comprises:
step 101: baking the sample formed in the step 9 on a hot plate at 200 ℃, and performing glue spreading and spin coating of the stripping glue;
Step 102: photoresist is glued and whirl-coated on the stripping glue;
wherein, the spin coating rotating speed is 3500 revolutions per minute;
step 103: placing the sample after the spin coating on a hot plate at 90 ℃ for baking;
step 104: placing the baked sample into a photoetching machine to expose photoresist in a source electrode area and a drain electrode area of the p-channel device;
step 105: placing the exposed sample into a developing solution to remove photoresist in a source electrode area and a drain electrode area, and performing ultrapure water flushing and nitrogen blow-drying on the photoresist;
step 106: placing the sample of the photoetching patterns of the active electrode and the drain electrode into a plasma photoresist remover for performing bottom film treatment;
wherein the vacuumizing time of the plasma photoresist remover is 2min, O 2 The flow is 100sccm, the power is 150-250W, and the treatment time of the bottom film is 5min;
step 107: placing the sample processed by the bottom film into an electron beam evaporation table, and waiting for the vacuum degree of a reaction chamber of the electron beam evaporation table to reach 2 multiplied by 10 -6 Evaporating a second ohmic metal on the AlGaN layer in the source electrode region and the drain electrode region of the p-channel device and on the photoresist outside the source electrode region and the drain electrode region after Torr;
step 108: stripping the sample subjected to the second ohmic metal evaporation to remove the second ohmic metal, the photoresist and the stripping glue outside the source electrode area and the drain electrode area to form a source electrode and a drain electrode;
Step 109: sequentially flushing a sample by using ultrapure water, drying by using nitrogen, and annealing;
wherein the annealing atmosphere is O 2 The annealing temperature is 500-550 ℃, and the annealing time is 5-10 min.
9. The method of fabricating an N-plane GaN-based CMOS device of claim 1, wherein step 16 comprises:
step 161: baking the sample formed in the step 15 on a hot plate at 200 ℃, and performing photoresist coating and spin coating;
wherein, the spin coating rotating speed is 3500 revolutions per minute;
step 161: placing the sample after the spin coating on a hot plate at 90 ℃ for baking;
step 162: placing the baked sample into a photoetching machine to expose photoresist in an opening area of the metal interconnection layer;
step 163: placing the exposed sample into a developing solution to remove photoresist in an opening area of the metal interconnection layer, and flushing the exposed sample with ultrapure water and blowing the exposed sample with nitrogen;
step 164: removing the 200nm thick SiN protective layer in the opening area of the metal interconnection layer by utilizing ICP etching;
the etching conditions for removing the SiN protection layer in the metal interconnection layer open hole area are as follows: in the presence of CF as the reaction gas 4 And O 2 The pressure of the reaction chamber is l0mTorr, and the radio frequency power of the upper electrode and the lower electrode is 100W and l0W respectively;
Step 165: baking the sample with the open area of the metal interconnection layer removed on a hot plate at 200 ℃, and then performing stripping glue spreading and spin coating on a source electrode, a drain electrode and a SiN protective layer which are not etched by the open area of the metal interconnection layer;
wherein, the thickness of the spin coating is 0.35 mu m;
step 166: placing the sample after the spin coating on a hot plate at 200 ℃ for baking;
step 167: placing the sample with the metal interconnection photoetching patterns into a plasma photoresist remover for bottom film treatment;
wherein the vacuumizing time of the plasma photoresist remover is 2min, O 2 The flow is 100-150 sccm, the power is 150-250W, and the treatment time of the bottom film is 5-10 min;
step 168: placing the sample processed by the bottom film into an electron beam evaporation table, and waiting for the vacuum degree of a reaction chamber of the electron beam evaporation table to reach 2 multiplied by 10 -6 Evaporating the interconnect metal after Torr;
step 169: and stripping the sample after the evaporation of the interconnection metal to remove the interconnection metal, photoresist and stripping adhesive outside the opening area of the metal interconnection layer, and flushing the sample with ultrapure water and drying with nitrogen.
10. An N-plane GaN-based CMOS device fabricated using the fabrication method of any one of claims 1 to 9.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106887454A (en) * 2017-03-14 2017-06-23 西安电子科技大学 GaN base fin grid enhancement device and preparation method thereof
CN112993030A (en) * 2021-02-04 2021-06-18 宁波海特创电控有限公司 Method for improving reliability of groove grid GaN MIS FET device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106887454A (en) * 2017-03-14 2017-06-23 西安电子科技大学 GaN base fin grid enhancement device and preparation method thereof
CN112993030A (en) * 2021-02-04 2021-06-18 宁波海特创电控有限公司 Method for improving reliability of groove grid GaN MIS FET device

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