CN114530496A - N-surface GaN-based p-channel device for improving ohmic contact resistance and preparation method thereof - Google Patents
N-surface GaN-based p-channel device for improving ohmic contact resistance and preparation method thereof Download PDFInfo
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Abstract
The invention discloses an N-surface GaN-based P-channel device for improving ohmic contact resistance and a preparation method thereof, wherein the preparation method comprises the following steps: a first Si substrate layer, a first protective layer, a P-GaN layer and a P-In layer which are arranged from bottom to top In sequencexGaN layer, AlyA GaN barrier layer and a second protective layer; al (aluminum)yGaN barrier layer, P-InxThe GaN layer and the P-GaN layer form a heterojunction structure with an N surface; P-InxThe thickness of the GaN layer is 10 nm-20 nm; wherein x is more than or equal to 0.05 and less than or equal to 0.1; al (Al)yA second groove opposite to the first groove is formed in the GaN barrier layer; al (Al)yDepositing an active electrode and a drain electrode on two sides of the GaN barrier layer respectively; wherein y is more than or equal to 0.2 and less than or equal to 0.3; a gate electrode is arranged on the second groove; interconnection metals penetrating through the second protective layer are respectively deposited above the source electrode, the drain electrode and the gate electrode. The P-channel device prepared by using the heterojunction material with the N surface can avoid the influence of interface charges introduced by depositing insulating media under a gate under the condition of the Ga surface on the hole mobility, avoid the reduction of the hole mobility and improve the ohmic contact characteristic of the device, thereby improving the performance of the device.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to an N-surface GaN-based P-channel device for improving ohmic contact resistance and a preparation method thereof.
Background
GaN is the first choice for the next generation of high frequency high power devices and power electronic devices due to its excellent material properties. With the increasing application requirements of devices such as power switches, the performance of the devices is affected by additional parasitic effects brought by the use of Si-based CMOS devices to drive GaN power switches and other devices. Therefore, it becomes especially important to fabricate GaN-based CMOS devices on the same wafer as GaN-based power switches and other devices. GaN-based P-channel devices are currently being valued and have begun a great deal of research as an important component in GaN-based CMOS devices. Wherein the Mg-doped P-GaN layer (30) has a lower actual hole concentration in the grown P-GaN layer (30) due to the higher activation energy of the Mg acceptor impurities. The lower hole concentration makes the ohmic contact prepared on the P-GaN have poor characteristics, which in turn affects the characteristics of the P-channel device. In addition, hole mobility in GaN is further reduced due to additional interface charges and the like caused by deposition of the insulating layer dielectric under the gate, and these problems greatly deteriorate the electrical characteristics of the P-channel device.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides an N-surface GaN-based P channel device for improving ohmic contact resistance and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
a first aspect of an embodiment of the present invention provides an N-plane GaN-based P-channel device for improving ohmic contact resistance, including: a first Si substrate layer, a first protective layer, a P-GaN layer and a P-In layer which are arranged from bottom to top In sequencexGaN layer, AlyA GaN barrier layer and a second protective layer;
the Al isyGaN barrier layer and the P-InxThe GaN layer and the P-GaN layer form a heterojunction structure with an N surface;
a first groove is formed in the P-GaN layer;
the notch of the first groove faces the first protective layer and is filled with the first protective layer;
the P-InxGaN layer doped with Mg, the P-InxThe thickness of the GaN layer is 10 nm-20 nm; wherein x is more than or equal to 0.05 and less than or equal to 0.1;
the Al isyA second groove opposite to the first groove is formed in the GaN barrier layer; the Al isyDepositing an active electrode and a drain electrode on two sides of the GaN barrier layer respectively; wherein y is more than or equal to 0.2 and less than or equal to 0.3;
the source electrode and the drain electrode both extend into the second protective layer;
the direction of the notch of the second groove is opposite to that of the notch of the first groove; a gate electrode is arranged on the second groove;
the gate electrode extends into the second protective layer;
and interconnection metals penetrating through the second protective layer are respectively deposited above the source electrode, the drain electrode and the gate electrode.
In one embodiment of the present invention, the maximum thickness of the P-GaN layer is 30nm to 50 nm; the thickness between the inner bottom of the first groove and the bottom of the P-GaN layer is 10 nm-20 nm; the depth of the second groove is 5 nm-15 nm;
the Al isyThe thickness of the GaN barrier layer is 15 nm-25 nm;
the thickness of the first protective layer is 200 nm-300 nm;
the thickness of the second protective layer is 180 nm-220 nm;
the P-InxThe doping concentration of Mg of the GaN layer is 2e19/cm3～3e19/cm3。
A second aspect of the embodiments of the present invention provides a method for manufacturing an N-plane GaN-based P-channel device with improved ohmic contact resistance, including:
step one, epitaxially growing materials on a second Si substrate layer, wherein the epitaxial layers are a GaN buffer layer, a GaN layer and Al from bottom to top respectivelyyGaN barrier layer, P-InxA GaN layer and a P-GaN layer; wherein, the P-InxThe doping concentration of Mg of the GaN layer is 2e19/cm3～3e19/cm3The thickness is 10nm to 20 nm; wherein x is more than or equal to 0.05 and less than or equal to 0.1, and y is more than or equal to 0.2 and less than or equal to 0.3;
step two, etching a first groove on the P-GaN layer;
depositing a first protective layer on the surface of the P-GaN layer, and filling the first groove;
bonding a first Si substrate layer on the surface of the first protective layer;
step five, turning over the product prepared in the step four to realize the AlyA GaN barrier layer (50), the P-InxAn N-face heterojunction structure formed by the GaN layer (40) and the P-GaN layer (30), and etching away the second Si substrate layer;
sixthly, completely etching the GaN buffer layer and the GaN layer;
seventhly, manufacturing a source electrode and a drain electrode on the product obtained in the sixth step, wherein the source electrode and the drain electrode are respectively positioned on the AlyBoth sides of the GaN barrier layer;
step eight, adding AlyEtching a second groove on the GaN barrier layer, wherein the second groove is opposite to the first groove;
step nine, preparing a gate electrode on the product prepared in the step eight;
step ten, growing a second protective layer on the surface of the product prepared in the step nine;
step eleven, photoetching an opening area of the metal interconnection layer on the second protective layer; the open region corresponds to the source electrode, the drain electrode and the gate electrode;
step twelve, evaporating interconnection metal in the opening area, and leading out an electrode to prepare the device of the first aspect of the embodiment of the invention.
In one embodiment of the present invention, the thickness of the GaN buffer layer is 2 μm to 5 μm;
the thickness of the GaN layer is 100 nm-200 nm; the Al isyThe thickness of the GaN barrier layer is 15 nm-25 nm; the thickness of the P-GaN layer is 30-50 nm, and the doping concentration of Mg of the P-GaN layer is 2e19/cm3～3e19/cm3。
In an embodiment of the present invention, the specific steps of the second step are:
baking the product prepared in the first step, placing the product on a spin coater, dripping EPI621 photoresist on the substrate of the P-GaN layer for spin coating, developing, rinsing with ultra-pure water, and drying with nitrogen;
and etching the first groove on the P-GaN layer by using an etching machine until the residual thickness is 10 nm-20 nm.
In an embodiment of the present invention, the specific steps of step three are as follows:
ultrasonically cleaning the product prepared in the second step by using acetone, ultrasonically cleaning by using ethanol, and then washing by using ultrapure water to obtain N2Drying;
introducing 2% SiH by vapor deposition4And N2Mixed gas of (2), NH3And depositing a first protective layer on the surface of the P-GaN layer by He gas and filling the first groove with the first protective layer, wherein the first protective layer is an SiN layer.
In an embodiment of the present invention, the specific steps of the step seven include:
baking the product prepared in the sixth step on a hot plate, then coating and throwing photoresist, baking the product on the hot plate, and then putting the product into a photoetching machine to expose the photoresist in the source drain region of the P-channel device; then, the photoresist in the electric isolation area is removed by putting the photoresist in a developing solution, and the photoresist is washed by ultrapure water and dried by nitrogen;
etching of Al in the developed regionyGaN barrier layer up to the P-InxA GaN layer;
sequentially putting the product prepared in the last step into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the electric isolation area, flushing the product with ultrapure water and drying the product with nitrogen;
baking the product prepared in the last step on a hot plate; then, coating and spinning the stripping glue, placing the product on a hot plate for baking, then coating and spinning the photoresist on the stripping glue, placing the product on the hot plate for baking, then placing the product subjected to coating and spinning into a photoetching machine for exposing the photoresist in the source electrode area and the drain electrode area, then placing the product subjected to exposure into a developing solution for removing the photoresist and the stripping glue in the source electrode area and the drain electrode area, and carrying out ultra-pure water washing and nitrogen blow-drying on the product;
evaporation source electrode and drain electrode: placing the product with the photoetching patterns of the active electrode and the drain electrode into a plasma photoresist remover for carrying out basement membrane treatment;
putting the metal into an electron beam evaporation table, and evaporating ohmic metal which is a metal laminated structure sequentially consisting of Pd and Ni from bottom to top;
stripping the product subjected to ohmic metal evaporation to remove ohmic metal, photoresist and stripping glue outside the source electrode area and the drain electrode area, flushing the product with ultrapure water and drying the product with nitrogen;
and carrying out annealing treatment.
In an embodiment of the present invention, the specific steps of step nine include:
placing the product with the second groove photoetching pattern into a plasma photoresist remover for bottom film treatment;
putting the grid metal into an electron beam evaporation table to evaporate grid metal, wherein the grid metal is a metal laminated structure sequentially consisting of two layers of Ni and Au from bottom to top;
and stripping the product subjected to gate metal evaporation to remove the gate metal, the photoresist and the stripping glue outside the gate electrode area, then flushing the product with ultrapure water and drying the product with nitrogen to form the product with the gate electrode.
In an embodiment of the present invention, the specific steps of step eleven include:
baking the product prepared in the step ten on a hot plate, then coating and throwing photoresist, baking the product on the hot plate, then putting the product into a photoetching machine to expose the photoresist in the open pore area of the metal interconnection layer, finally putting the exposed product into a developing solution to remove the photoresist in the open pore area, and carrying out ultra-pure water washing and nitrogen blow-drying on the exposed product; the opening region is positioned above the source electrode, the drain electrode and the gate electrode;
in the presence of a reaction gas of CF4And O2Etching the second protective layer in the open region under the condition of (1); the etching depth is to penetrate the second protective layer.
In an embodiment of the present invention, the specific steps of the step twelve include:
baking the product subjected to the opening etching of the metal interconnection layer on a hot plate, then performing glue coating and spin coating of a stripping glue on the source electrode and the drain electrode of the opening region and the second protection layer which is not subjected to the opening etching, and baking the product on the hot plate; then, coating and throwing photoresist on the stripper, baking the product on a hot plate, and then putting the product subjected to coating and throwing into a photoetching machine to expose the photoresist in the open hole area; finally, putting the exposed product into a developing solution to remove the photoresist and the stripping glue in the open hole area, and carrying out ultra-pure water washing and nitrogen blow-drying on the product;
placing the product with the photoetching pattern of the open area into a plasma photoresist remover for carrying out basement membrane treatment;
putting the metal into an electron beam evaporation table to evaporate interconnection metal, wherein the interconnection metal is a metal laminated structure sequentially consisting of Ti and Au layers from bottom to top;
and stripping the product subjected to interconnection metal evaporation to remove the interconnection metal, the photoresist and the stripping glue outside the metal interconnection layer area, flushing the product with ultrapure water and drying the product with nitrogen to finish preparation, thereby obtaining the device of the first aspect of the embodiment of the invention.
The invention has the beneficial effects that:
the P-channel device prepared by using the heterojunction material with the N surface can avoid the influence of interface charges introduced by depositing insulating media under a gate under the condition of the Ga surface on the hole mobility, avoid the reduction of the hole mobility and improve the ohmic contact characteristic of the device, thereby improving the performance of the device. Meanwhile, the thickness of the P-In is relatively thinxThe GaN layer is used as a contact layer between ohmic metal and the P-GaN layer, so that the thickness of a carrier tunneling barrier can be reduced, and the ohmic contact resistivity is reduced, thereby further improving the ohmic contact characteristics and the device performance. In addition, InxThe polarization electric field generated by the polarization characteristic of GaN/GaN can further improve the activation rate of Mg impurities, thereby further increasing the hole tunneling probability and improving the ohmic contact characteristic.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic structural diagram of an N-plane GaN-based P-channel device with improved ohmic contact resistance according to an embodiment of the present invention:
fig. 2a to fig. 2j are process diagrams of a method for manufacturing an N-plane GaN-based P-channel device with improved ohmic contact resistance according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, an embodiment of the invention provides an N-plane GaN-based P-channel device with improved ohmic contact resistance, including: a first Si substrate arranged from bottom to topLayer 10, first protective layer 20, P-GaN layer 30, P-InxGaN layer 40, AlyA GaN barrier layer 50 and a second protective layer 60.
Aly GaN barrier layer 50, P-InxThe GaN layer 40 and the P-GaN layer 30 form an N-plane heterojunction structure. The P-GaN layer 30 is formed with a first groove 31. The notch of the first groove 31 faces the first protection layer 20, and the first groove 31 is filled with the first protection layer 20.
P-InxThe doping concentration of Mg of the GaN layer 40 was 2e19/cm3～3e19/cm3The thickness is 10nm to 20 nm. Wherein x is more than or equal to 0.05 and less than or equal to 0.1.
AlyThe GaN barrier layer 50 is provided with a second groove 51 facing the first groove 31. Al (Al)yAn active electrode 81 and a drain electrode 82 are deposited on both sides of the GaN barrier layer 50, respectively. Wherein y is more than or equal to 0.2 and less than or equal to 0.3. The source electrode 81 and the drain electrode 82 each extend into the second protective layer 60. The notch orientation of the second groove 51 is opposite to the notch orientation of the first groove 31. The second groove 51 is provided with a gate electrode 70. The gate electrode 70 extends into the second protective layer 60. Interconnection metals 90 penetrating the second protective layer 60 are deposited over the source electrode 81, the drain electrode 82, and the gate electrode 70, respectively.
Further, the maximum thickness of the P-GaN layer 30 is 30nm to 50nm, the thickness between the inner bottom of the first groove 31 and the bottom of the P-GaN layer 30 is 10nm to 20nm, and the depth of the first groove 31 is 10nm to 40 nm. The depth of the second grooves 51 is 5nm to 15 nm. Al (Al)yThe thickness of the GaN barrier layer 50 is 15nm to 25 nm. The thickness of the first protective layer 20 is 200nm to 300 nm. The thickness of the second protective layer 60 is 180nm to 220 nm.
In this embodiment, the P-channel device prepared by using the N-plane heterojunction material can avoid the influence of interface charges introduced by depositing an insulating medium under a gate on the hole mobility under the Ga-plane condition, avoid the reduction of the hole mobility, and improve the ohmic contact characteristic of the device, thereby improving the performance of the device. Meanwhile, the thickness of the P-In is relatively thinxThe GaN layer 40 is used as a contact layer between the ohmic metal and the P-GaN layer 30, and can reduce the thickness of a carrier tunneling barrier and the ohmic contact resistivity, thereby further improving the ohmic contactCharacteristics and device performance. In addition, InxThe polarization electric field generated by the polarization characteristic of GaN/GaN can further improve the activation rate of Mg impurities, thereby further increasing the hole tunneling probability and improving the ohmic contact characteristic.
Note that, P-InxIf the thickness of the GaN layer 40 is greater than 20nm, the ohmic contact characteristics of the device become poor, and P-InxIf the thickness of the GaN layer 40 is less than 5nm, the current characteristics of the device are deteriorated, and the device cannot be used. Preferably, the thickness is 10 nm. P-InxIf the In composition x In the GaN layer 40 is less than 0.05, the current characteristics of the device are deteriorated, and if it is more than 0.1, In is precipitated, and the growth requirement cannot be met, which results In poor quality of the device and failure of the device. Preferably, x is 0.05.
AlyIf the composition y of Al in the GaN barrier layer 50 is less than 0.2, the current characteristics of the device are deteriorated, and if it is greater than 0.3, the growth requirement cannot be met, which results in poor quality of the device and failure of the device. Preferably, y is 0.25.
In one possible implementation, the material of the first protective layer 20 and the second protective layer 60 is SiN. Preferably, the thickness of the second protective layer 60 is 200 nm. Wherein the doping concentration of Mg in the P-GaN layer 30 is 2e 19-3 e19/cm3。
In one possible implementation, the source electrode 81 and the drain electrode 82 are both of a metal stacked structure, and are two metal layers of Pd with a thickness of 20nm and Ni with a thickness of 20nm from bottom to top in sequence. The gate electrode 70 has a metal laminated structure consisting of two metals, i.e., 40nm thick Ni and 200nm thick Au, in this order from bottom to top. The interconnection metal 90 is a metal laminated structure consisting of two layers of metal, namely Ti with the thickness of 40nm and Au with the thickness of 200nm from bottom to top in sequence.
Example two
The second aspect of the embodiments of the present invention provides a method for manufacturing an N-plane GaN-based P-channel device with improved ohmic contact resistance, which is used for manufacturing the device in the first embodiment, and includes the following steps:
step one, epitaxially growing materials on a second Si substrate layer 11, wherein the epitaxial layers are a GaN buffer layer 12, a GaN layer 13 and Al from bottom to top respectivelyy GaN barrier layer 50, P-Inx A GaN layer 40 and a P-GaN layer 30; wherein, P-InxThe doping concentration of Mg of the GaN layer 40 was 2e19/cm3～3e19/cm3The thickness is 10nm to 20 nm.
And step two, etching the first groove 31 on the P-GaN layer 30.
And step three, depositing a first protective layer 20 on the surface of the P-GaN layer 30, and filling the first groove 31.
And fourthly, bonding the first Si substrate layer 10 on the surface of the first protective layer 20.
Step five, turning over the product prepared in the step four to realize the AlyA GaN barrier layer (50), the P-InxAnd an N-face heterojunction structure formed by the GaN layer (40) and the P-GaN layer (30), and etching away the second Si substrate layer 11.
And sixthly, completely etching the GaN buffer layer 12 and the GaN layer 13.
Step seven, manufacturing a source electrode 81 and a drain electrode 82 on the product obtained in the step six, wherein the source electrode 81 and the drain electrode 82 are respectively positioned on AlyOn either side of the GaN barrier layer 50.
Step eight, adding AlyA second groove 51 is etched in the GaN barrier layer 50, the second groove 51 being opposite to the first groove 31.
Step nine, preparing a gate electrode 70 on the product prepared in step eight.
Step ten, growing a second protective layer 60 on the surface of the product prepared in the step nine.
Step eleven, photoetching an opening area of the metal interconnection layer on the second protective layer 60; the open region corresponds to the source electrode 81, the drain electrode 82, and the gate electrode 70.
Step twelve, evaporating the interconnection metal 90 in the opening area, and leading out an electrode to prepare the device of the first embodiment.
Further, the thickness of the GaN buffer layer 12 is 2 μm to 5 μm. The thickness of the GaN layer 13 is 100nm to 200 nm. Al (Al)yThe thickness of the GaN barrier layer 50 is 15nm to 25 nm. The thickness of the P-GaN layer 30 is 30nm to 50nm, and the Mg doping concentration of the P-GaN layer 30 is 2e19/cm3～3e19/cm3。
EXAMPLE III
The embodiment of the invention provides a preparation method of an N-surface GaN-based P channel device for improving ohmic contact resistance, which is used for preparing the device in the first embodiment and comprises the following steps:
step 301, carrying out epitaxial growth on materials on the second Si substrate layer 11 by adopting an MOCVD method, wherein the epitaxial layers are a GaN buffer layer 12, a GaN layer 13 and Al respectively from bottom to topy GaN barrier layer 50, P-Inx A GaN layer 40 and a P-GaN layer 30; wherein, P-InxThe doping concentration of Mg of the GaN layer 40 was 2e19/cm3～3e19/cm3The thickness is 10nm to 20 nm. As shown in fig. 2 a.
Wherein the thickness of the GaN buffer layer 12 is 2 μm to 5 μm. The thickness of the GaN layer 13 is 100nm to 200 nm. Al (Al)yThe thickness of the GaN barrier layer 50 is 15nm to 25 nm. The thickness of the P-GaN layer 30 is 30-50 nm. The doping concentration of Mg of the P-GaN layer 30 is 2e19/cm3～3e19/cm3。
Note that, P-InxIf the thickness of the GaN layer 40 is greater than 20nm, the ohmic contact characteristics of the device become poor, and P-InxIf the thickness of the GaN layer 40 is less than 5nm, the current characteristics of the device are deteriorated, and the device cannot be used. Preferably, the thickness is 10 nm. P-InxIf the In composition x In the GaN layer 40 is less than 0.05, the current characteristics of the device are deteriorated, and if it is more than 0.1, In is precipitated, and the growth requirement cannot be met, which results In poor quality of the device and failure of the device. Preferably, x is 0.05.
AlyIf the composition y of Al in the GaN barrier layer 50 is less than 0.2, the current characteristics of the device are deteriorated, and if it is greater than 0.3, the growth requirement cannot be met, which results in poor quality of the device and failure of the device. Preferably, y is 0.25.
And step 302, etching the P channel GaN groove. Baking the product prepared in the step 301 at 200 ℃, then placing the product on a spin coater, and dripping EPI621 photoresist on the surface of the P-GaN layer 30 for spin coating; and (3) homogenizing conditions: running at 500rpm for 5 seconds, then running at 3500rpm for 40 seconds, baking at 90 ℃, developing in a developing solution, rinsing with ultrapure water for 2 minutes after completion, and blowing by nitrogen.
Step 303, performing a first etching on the P-GaN layer 30 by using a chlorine-based ICP etcherEtching of the groove 31, etching conditions: the power of the upper electrode is 40W-60W, the power of the lower electrode is 10W-20W, the pressure is 5mTorr, Cl2And BCl3The P-GaN layer 30 is etched to leave about 10nm to 20nm at a flow ratio of 8/20sccm to form a first groove 31. The etching depth is 10 nm-40 nm. As shown in fig. 2 b.
Step 304, depositing 200nm to 300nm thick SiN by PECVD, and filling the first groove 31. Ultrasonically cleaning with acetone for 3min at ultrasonic intensity of 2.0, ultrasonically cleaning with ethanol for 2min at ultrasonic intensity of 2.0, washing with ultrapure water for 2min, and blowing with nitrogen.
Step 305, SiH is introduced4And N2Mixed gas of (2), NH3And He gas deposits a first protective layer 20 on the surface of the P-GaN layer 30 and in the first groove 31, wherein the first protective layer 20 is a SiN layer. The thickness of the first protective layer 20 on the surface of the P-GaN layer 30 is 200nm to 300 nm. The flow ratio of the mixed gas was 200sccm, SiH4The proportion of NH in the mixed gas is 2%3The flow rate of (1) is 2sccm, the flow rate of He is 200sccm, the pressure is about 600mT, the temperature is 250 ℃, and the power is about 20W. As shown in fig. 2 c.
And step 306, bonding the first Si substrate layer 10 with the thickness of 500-700 μm on the surface of the first protective layer 20 by using chemical mechanical polishing. As shown in fig. 2 d.
307, overturning the product prepared in the step 306 to realize Aly GaN barrier layer 50, P-InxThe GaN layer (40) and the P-GaN layer 30 form an N-plane heterojunction structure as shown in fig. 2e, and the second Si substrate layer 11 is completely etched away. Etching conditions are as follows: the power of the upper electrode is 250W-350W, the power of the lower electrode is 20W-40W, the pressure is 5mTorr, SF6The flow rate was 50 sccm.
Step 308, completely etching the GaN buffer layer 12 and the GaN layer 13 to AlyThe GaN barrier layer 50 is etched using an ICP-chlorine-based condition: the power of the upper electrode is 40W-60W, the power of the lower electrode is 20W-30W, the pressure is 5mT, Cl2Flow 8sccm, BCl3The flow rate was 20 sccm. As shown in fig. 2 f.
P-channel device fabrication source electrode 81 and drain electrode 82:
al of source and drain regionsyGaN etching:
309, baking the product prepared in the step 308 on a hot plate at 200 ℃, then coating and spin coating photoresist at a spin coating speed of 3500rpm, baking the product on a hot plate at 90 ℃, and then putting the product into a photoetching machine to expose the photoresist in the source and drain regions of the P-channel device; then, the photoresist in the electrically isolated region was removed by placing in a developing solution, and subjected to ultra-pure water rinsing and nitrogen blow-drying.
Step 310, etching the Al in the developing area by utilizing ICP processy GaN barrier layer 50 up to P-InxA GaN layer 40. Etching conditions, upper electrode power 15W-25W, lower electrode power 3W-5W, pressure 5mT, Cl2Flow 4sccm, BCl3The flow rate was 10 sccm.
And 311, sequentially putting the product prepared in the step 310 into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the electric isolation area, flushing the product with ultrapure water and drying the product with nitrogen.
Photoetching a source electrode region and a drain electrode region:
step 312, baking the product prepared in step 311 on a hot plate at 200 ℃; then, carrying out glue coating and spin coating of the stripping glue, wherein the spin coating conditions are as follows: SF6, 2000 rpm, 40sec, thickness 0.35 μm and baking the product on a hot plate at 200 ℃; then, gluing and spinning photoresist on the stripper rubber, wherein the spinning conditions are as follows: EPI621 is carried out at 5000 revolutions per minute for 30 seconds, the thickness is 0.77 mu m, the mixture is baked on a hot plate at the temperature of 90 ℃, then a product which is subjected to gluing and whirl coating is put into a photoetching machine to expose the photoresist in the source electrode area and the drain electrode area, then the product which is subjected to exposure is put into a developing solution to remove the photoresist and the stripping glue in the source electrode area and the drain electrode area, and the photoresist and the stripping glue are washed by ultrapure water and dried by nitrogen.
step 313, evaporating source electrode 81 and drain electrode 82: and placing the product with the photoetching patterns of the active electrode and the drain electrode into a plasma photoresist remover for carrying out basement membrane treatment. The treatment conditions are as follows: an alpha-plasma degumming machine is adopted, vacuum pumping is carried out for 2min,then, O2The flow rate is 100 sccm-150 sccm, the power is 150W-250W, and the treatment time is 5 min-10 min.
Step 314, putting the reaction chamber into an electron beam evaporation table until the vacuum degree of the reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10- 6After the Torr, ohmic metal which is a metal laminated structure sequentially consisting of two layers of Pd with the thickness of 20nm and Ni with the thickness of 20nm from bottom to top is evaporated.
And 315, stripping the product subjected to ohmic metal evaporation to remove the ohmic metal, the photoresist and the stripping glue outside the source electrode 81 area and the drain electrode 82 area, flushing the product with ultrapure water and drying the product with nitrogen. As shown in fig. 2 g.
And step 316, annealing treatment is carried out. Annealing atmosphere of O2The annealing temperature is 400-550 ℃, and the annealing time is 5-10 min.
And 317, etching the P-channel device grid electrode groove. The second grooves 51 are aligned with the first grooves 31 of the P-GaN layer 30, and chlorine-based ICP etches AlyThe GaN barrier layer is 5 nm-15 nm. Etching conditions are as follows: the power of the upper electrode is 15W-25W, the power of the lower electrode is 3W-5W, the pressure is 5mT, Cl2Flow 4sccm, BCl3The flow rate was 10 sccm. As shown in fig. 2 h.
P-channel device gate electrode 70 fabrication:
step 318, placing the product with the second groove 51 photoetching pattern into a plasma photoresist remover for bottom film treatment; the treatment conditions are as follows: removing the photoresist from the alpha-plasma, vacuumizing for 2min, and then O2The flow rate is 100 sccm-150 sccm, the power is 150W-250W, and the treatment time is 5 min-10 min.
319, placing the reaction product into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10- 6Evaporating gate metal after Torr, wherein the gate metal is a metal laminated structure consisting of Ni with the thickness of 40nm and Au with the thickness of 200nm from bottom to top in sequence.
And 320, stripping the product subjected to gate metal evaporation to remove the gate metal, the photoresist and the stripping glue outside the gate electrode 70 area, and then washing the product with ultrapure water and drying the product with nitrogen to form the product with the gate electrode 70. As shown in fig. 2 i.
Step 321, growing a SiN second protection layer 60. The second protective layer 60 of SiN with a thickness of 200nm is grown by using a PECVD process under the following growth conditions: by NH3And SiH4As the reaction gas, the substrate temperature is about 250 ℃, the pressure of the reaction chamber is 600mTorr, and the radio frequency power is 20W-25W.
Opening a hole of the photoetching electrode:
step 322, baking the product prepared in the step 321 on a hot plate at 200 ℃, then coating and spin-coating the photoresist at a spin-coating speed of 3500rpm, baking the product on a hot plate at 90 ℃, then placing the product into a photoetching machine to expose the photoresist in the open pore region of the metal interconnection layer, finally placing the exposed product into a developing solution to remove the photoresist in the open pore region, and carrying out ultra-pure water washing and nitrogen blow-drying on the exposed product. The open region is located above the source electrode 81, the drain electrode 82, and the gate electrode 70.
Step 323, etching with ICP. In the presence of a reaction gas of CF4And O2Under the conditions of (1), the second protective layer 60 having a thickness of 200nm in the opening region was etched. The etch depth penetrates the second protective layer 60.
Leading out an electrode, and finishing the manufacture of a device:
step 324, baking the product subjected to the metal interconnection layer opening etching on a hot plate at 200 ℃, then performing glue coating and whirl coating of the stripping glue on the source electrode 81 and the drain electrode 82 in the opening area and the second protective layer 60 which is not subjected to the opening etching, wherein the whirl coating thickness is 0.35 mu m, and baking the product on the hot plate at 200 ℃; then, coating and spinning the photoresist on the stripper with the thickness of 0.77 μm, baking the product on a hot plate at 90 ℃, and then putting the product subjected to coating and spinning into a photoetching machine to expose the photoresist in the open hole region; and finally, putting the exposed product into a developing solution to remove the photoresist and the stripping glue in the open hole region, and carrying out ultra-pure water washing and nitrogen blow-drying on the product.
Evaporation of the interconnection metal 90:
step 325, forming a hole areaAnd (4) placing the product with the carved pattern into a plasma degumming machine for carrying out basement membrane treatment. The treatment conditions are as follows: removing the photoresist from the alpha-plasma, vacuumizing for 2min, and then O2The flow rate is 100 sccm-150 sccm, the power is 150W-250W, and the treatment time is 5 min-10 min.
Step 326, putting the reaction chamber into an electron beam evaporation table until the vacuum degree of the reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10- 6Evaporating the interconnection metal 90 after the Torr, wherein the interconnection metal 90 is a metal laminated structure consisting of two layers of metal of Ti with the thickness of 40nm and Au with the thickness of 200nm from bottom to top in sequence.
Step 327, stripping the product after the evaporation of the interconnection metal 90 is completed to remove the interconnection metal, the photoresist and the stripping glue outside the metal interconnection layer region, rinsing the product with ultrapure water and drying the product with nitrogen gas to complete the preparation, so as to obtain the device in the first embodiment, as shown in fig. 2 j.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. An N-plane GaN-based P-channel device for improving ohmic contact resistance, comprising: a first Si substrate layer (10), a first protective layer (20), a P-GaN layer (30) and a P-In layer which are arranged from bottom to top In sequencexGaN layer (40), AlyA GaN barrier layer (50) and a second protective layer (60);
the Al isyA GaN barrier layer (50), the P-InxThe GaN layer (40) and the P-GaN layer (30) form a heterojunction structure with an N surface;
a first groove (31) is formed in the P-GaN layer (30);
the first groove (31), the notch facing the first protective layer (20), is filled with the first protective layer (20);
the P-InxThe GaN layer (40) is doped with Mg, and the P-InxThe thickness of the GaN layer is 10 nm-20 nm; wherein x is more than or equal to 0.05 and less than or equal to 0.1;
the Al isyA second groove (51) opposite to the first groove (31) is formed in the GaN barrier layer (50); the Al isyAn active electrode (81) and a drain electrode (82) are respectively deposited on two sides of the GaN barrier layer (50); wherein y is more than or equal to 0.2 and less than or equal to 0.3;
the source electrode (81) and the drain electrode (82) each extending into the second protective layer (60);
the second groove (51) has a notch facing in the opposite direction to the notch facing the first groove (31); a gate electrode (70) is arranged on the second groove (51);
the gate electrode (70) extends into the second protective layer (60);
and interconnection metals (90) penetrating through the second protective layer (60) are respectively deposited above the source electrode (81), the drain electrode (82) and the gate electrode (70).
2. The N-plane GaN-based P-channel device for improving ohmic contact resistance according to claim 1, wherein the maximum thickness of the P-GaN layer (30) is 30nm to 50 nm; the thickness between the inner bottom of the first groove (31) and the bottom of the P-GaN layer (30) is 10 nm-20 nm; the depth of the second groove (51) is 5 nm-15 nm;
the Al isyThe thickness of the GaN barrier layer (50) is 15 nm-25 nm;
the thickness of the first protective layer (20) is 200 nm-300 nm;
the thickness of the second protective layer (60) is 180 nm-220 nm;
the P-InxThe GaN layer (40) has a Mg doping concentration of 2e19/cm3～3e19/cm3。
3. A preparation method of an N-surface GaN-based P channel device for improving ohmic contact resistance is characterized by comprising the following steps:
step one, epitaxially growing materials on a second Si substrate layer (11), wherein the epitaxial layers are a GaN buffer layer (12), a GaN layer (13) and Al from bottom to top respectivelyyGaN barrier layer (50), P-InxA GaN layer (40) and a P-GaN layer (30); wherein, the P-InxThe GaN layer (40) has a Mg doping concentration of 2e19/cm3～3e19/cm3The thickness is 10nm to 20 nm; wherein x is more than or equal to 0.05 and less than or equal to 0.1, and y is more than or equal to 0.2 and less than or equal to 0.3;
secondly, etching a first groove (31) on the P-GaN layer (30);
thirdly, depositing a first protective layer (20) on the surface of the P-GaN layer (30), and filling the first groove (31);
bonding a first Si substrate layer (10) on the surface of the first protective layer (20);
step five, turning over the product prepared in the step four to realize the AlyA GaN barrier layer (50), the P-InxAn N-face heterojunction structure formed by the GaN layer (40) and the P-GaN layer (30), and etching away the second Si substrate layer (11);
sixthly, completely etching the GaN buffer layer (12) and the GaN layer (13);
step seven, manufacturing a source electrode (81) and a drain electrode (82) on the product prepared in the step six, wherein the source electrode (81) and the drain electrode (82)82) Are respectively positioned at the AlyBoth sides of the GaN barrier layer (50);
step eight, adding AlyEtching a second groove (51) on the GaN barrier layer (50), wherein the second groove (51) is opposite to the first groove (31);
step nine, preparing a gate electrode (70) on the product prepared in the step eight;
step ten, growing a second protective layer (60) on the surface of the product prepared in the step nine;
step eleven, photoetching an opening area of the metal interconnection layer on the second protective layer (60); the open region corresponds to the source electrode (81), the drain electrode (82), and the gate electrode (70);
step twelve, evaporating interconnection metal (90) in the opening area, and leading out an electrode to prepare the device according to claim 1 or 2.
4. The method for preparing an N-face GaN-based P-channel device for improving ohmic contact resistance according to claim 3, wherein the thickness of the GaN buffer layer (12) is 2 μm to 5 μm;
the thickness of the GaN layer (13) is 100 nm-200 nm; the Al isyThe thickness of the GaN barrier layer (50) is 15 nm-25 nm; the thickness of the P-GaN layer (30) is 30 nm-50 nm, and the doping concentration of Mg of the P-GaN layer (30) is 2e19/cm3～3e19/cm3。
5. The method for preparing an N-surface GaN-based P-channel device for improving ohmic contact resistance according to claim 4, wherein the specific steps of the second step are as follows:
baking the product prepared in the first step, placing the product on a spin coater, dripping EPI621 photoresist on the surface of the P-GaN layer (30) for spin coating, then developing and rinsing with ultra-pure water, and drying with nitrogen;
and etching the first groove (31) on the P-GaN layer (30) by using an etching machine until the residual thickness is 10 nm-20 nm.
6. The method for preparing an N-surface GaN-based P-channel device for improving ohmic contact resistance according to claim 5, wherein the specific steps of the third step are as follows:
ultrasonically cleaning the product prepared in the second step by using acetone, ultrasonically cleaning by using ethanol, and then washing by using ultrapure water to obtain N2Drying;
introducing 2% SiH by vapor deposition4And N2Mixed gas of (2), NH3And He gas deposits a first protective layer (20) on the surface of the P-GaN layer (30) and fills the first groove (31), wherein the first protective layer (20) is an SiN layer.
7. The method for preparing an N-plane GaN-based P-channel device with improved ohmic contact resistance according to claim 6, wherein the specific steps of the seventh step include:
baking the product prepared in the sixth step on a hot plate, then coating and throwing photoresist, baking the product on the hot plate, and then putting the product into a photoetching machine to expose the photoresist in the source drain region of the P-channel device; then, the photoresist in the electric isolation area is removed by putting the photoresist in a developing solution, and the photoresist is washed by ultrapure water and dried by nitrogen;
etching of Al in the developed regionyA GaN barrier layer (50) up to the P-InxA GaN layer (40);
sequentially putting the product prepared in the last step into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the electric isolation area, flushing the product with ultrapure water and drying the product with nitrogen;
baking the product prepared in the last step on a hot plate; then, coating and spinning the stripping glue, placing the product on a hot plate for baking, then coating and spinning the photoresist on the stripping glue, placing the product on the hot plate for baking, then placing the product subjected to coating and spinning into a photoetching machine for exposing the photoresist in the source electrode area and the drain electrode area, then placing the product subjected to exposure into a developing solution for removing the photoresist and the stripping glue in the source electrode area and the drain electrode area, and carrying out ultra-pure water washing and nitrogen blow-drying on the product;
evaporation source electrode (81) and drain electrode (82): placing the product with the photoetching patterns of the active electrode (81) and the drain electrode (82) into a plasma photoresist remover for carrying out basement membrane treatment;
putting the metal into an electron beam evaporation table, and evaporating ohmic metal which is a metal laminated structure sequentially consisting of Pd and Ni from bottom to top;
stripping the product subjected to ohmic metal evaporation to remove ohmic metal, photoresist and stripping glue outside the source electrode (81) area and the drain electrode (82) area, flushing the product with ultrapure water and drying the product with nitrogen;
and carrying out annealing treatment.
8. The method according to claim 7, wherein the specific steps of step nine include:
putting the product with the photoetching pattern of the second groove (51) into a plasma photoresist remover to carry out basement membrane treatment;
putting the grid metal into an electron beam evaporation table to evaporate grid metal, wherein the grid metal is a metal laminated structure sequentially consisting of two layers of Ni and Au from bottom to top;
and stripping the product after the gate metal evaporation is finished so as to remove the gate metal, the photoresist and the stripping glue outside the gate electrode (70), and then rinsing the product with ultrapure water and drying the product with nitrogen to form the product with the gate electrode (70).
9. The method for preparing an N-plane GaN-based P-channel device with improved ohmic contact resistance according to claim 8, wherein the detailed step of the eleventh step comprises:
baking the product prepared in the step ten on a hot plate, then coating and throwing photoresist, baking the product on the hot plate, then putting the product into a photoetching machine to expose the photoresist in the open pore area of the metal interconnection layer, finally putting the exposed product into a developing solution to remove the photoresist in the open pore area, and carrying out ultra-pure water washing and nitrogen blow-drying on the exposed product; the opening region is located above the source electrode (81), the drain electrode (82), and the gate electrode (70);
in the presence of a reaction gas of CF4And O2Etching the second protective layer (60) in the open area; the etching depth is such as to penetrate the second protective layer (60).
10. The method for preparing an N-plane GaN-based P-channel device with improved ohmic contact resistance according to claim 9, wherein the specific step of the twelfth step comprises:
baking the product subjected to the opening etching of the metal interconnection layer on a hot plate, then performing glue coating and spin coating of a stripping glue on the source electrode (81) and the drain electrode (82) in the opening area and the second protective layer (60) which is not subjected to the opening etching, and baking the product on the hot plate; then, coating and throwing photoresist on the stripper, baking the product on a hot plate, and then putting the product subjected to coating and throwing into a photoetching machine to expose the photoresist in the open hole area; finally, putting the exposed product into a developing solution to remove the photoresist and the stripping glue in the open hole area, and carrying out ultra-pure water washing and nitrogen blow-drying on the product;
placing the product with the photoetching pattern of the open area into a plasma photoresist remover for carrying out basement membrane treatment;
putting the metal into an electron beam evaporation table to evaporate interconnection metal (90), wherein the interconnection metal (90) is a metal laminated structure consisting of two layers of Ti and Au from bottom to top in sequence;
stripping the product of the completed interconnection metal (90) to remove the interconnection metal (90), the photoresist and the stripper outside the metal interconnection layer area, rinsing the product with ultrapure water and blow-drying with nitrogen gas to complete the preparation, obtaining the device according to claim 1 or 2.
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