CN109300974B - Nonpolar InAlN/GaN high electron mobility transistor and preparation method thereof - Google Patents
Nonpolar InAlN/GaN high electron mobility transistor and preparation method thereof Download PDFInfo
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
Abstract
The invention relates to a nonpolar InAlN/GaN high electron mobility transistor and a preparation method thereof, wherein the preparation method comprises the following steps: growing a nucleation layer material on the substrate to form a nucleation layer; growing GaN on the nucleation layer under a first condition to form a nonpolar buffer layer; growing GaN on the nonpolar buffer layer under a second condition to form a nonpolar channel layer; growing InAlN on the nonpolar channel layer to form a nonpolar barrier layer; and manufacturing a source electrode and a drain electrode in the nonpolar channel layer and the nonpolar barrier layer, and manufacturing a grid electrode on the nonpolar barrier layer to obtain the nonpolar InAlN/GaN high electron mobility transistor. According to the preparation method of the nonpolar InAlN/GaN high-electron-mobility transistor, the nonpolar channel layer and the nonpolar barrier layer are formed, so that the nonpolar heterostructure is formed, the nonpolar heterostructure can modulate spontaneous polarization and piezoelectric polarization, generation of high-density polarization charges in the channel is restrained, and an enhancement effect is achieved.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a nonpolar InAlN/GaN high-electron-mobility transistor and a preparation method thereof.
Background
Because the channel of the GaN-based heterostructure has high-mobility two-dimensional electron gas, GaN becomes the most ideal material for preparing high-performance electronic devices. Since the first proposal by k.han et al of the concept of GaN-based heterostructures, heterostructures represented by AlGaN/GaN, InAlN/GaN, AlN/GaN, etc. have achieved significant research results in the fabrication of high electron mobility transistors. Up to now, the cut-off frequency of a High Electron Mobility Transistor (HEMT) based on a conventional AlGaN/GaN heterostructure has broken through 200GHz, and the maximum oscillation frequency has broken through 300 GHz.
Transistor devices based on conventional polar c-plane III-nitride heterostructures are depletion mode devices, i.e., the devices exhibit an on-state at zero bias, requiring an applied bias voltage to reach an off-state. This property not only causes the device to lose power in the non-operating state, but also causes the device to have a safety hazard in power electronic applications. In addition, in a digital circuit system, the realization of various logic functions cannot be completed only by means of depletion devices. Therefore, the fabrication of high performance enhancement mode (normally-off) devices is a hot spot and focus of current GaN-based electronic device research.
At present, the technology for realizing the enhancement device mainly comprises a p-GaN cap layer structure preparation technology, a concave gate structure preparation technology, a fluorine ion implantation technology and the like.
For the p-GaN cap layer preparation technology: the working principle of the p-GaN cap layer technology is similar to that of a pn junction, and p-type GaN and an n-type AlGaN barrier layer can generate a pn junction electric field to generate depletion effect on two-dimensional electron gas at an AlGaN/GaN heterojunction interface. However, in the p-GaN cap layer structure, the deposition of the cap layer can not only increase the parasitic capacitance of the device, but also weaken the gate control capability of the device; in addition, the growth of p-type GaN has high requirements on doping technology, the difficulty of GaN epitaxy process which is not overcome yet is present, and the process is difficult to control accurately.
For the recessed gate structure preparation technology: the preparation technology of the concave gate structure is to etch the AlGaN barrier layer, when the thickness of the AlGaN barrier layer is smaller than a critical value, a two-dimensional electron gas is not generated at an AlGaN/GaN heterojunction interface, at the moment, no electrons are accumulated below a gate, and a device is in a normally-off state. However, for the recessed gate structure, the too thin barrier layer can cause the depth of a channel potential well to be shallow, so that the confinement property of a carrier is reduced; moreover, the dry etching process can damage the material structure, and the stability and the repeatability of the process are poor, so that the process is not beneficial to large-scale production; in addition, the threshold voltage of the device with the concave gate structure can only reach a level slightly larger than 0V, and higher threshold voltage cannot be obtained.
For the fluorine ion implantation technique: the principle of the fluorine ion implantation technology is that fluorine plasma treatment is carried out on an AlGaN barrier layer in a gate region through plasma equipment, partial fluorine ions enter the AlGaN barrier layer to form a negative electric center, and a potential field formed around the negative electric center generates a depletion effect on channel electrons so as to form an enhancement type device. However, the fluorine ion implantation process may cause an increase in trap states and defect damage in the barrier layer, affecting device performance, especially affecting the stability of the device under high temperature conditions;
in addition, although the traditional process method can achieve the purpose of depleting current carriers in a channel, polarization charges at the interface of the heterostructure still exist; the prior art shows that when device processes such as gate dielectric deposition are carried out, negative drift of the threshold voltage of the device can be caused by polarization charges, and potential hazards exist in reliability.
In summary, the existing technology for realizing the enhancement-mode device has the problems of poor process repeatability, damage to materials and devices caused by the process, and influence on the stability of the devices caused by the process, thereby influencing the performance and reliability of the enhancement-mode device.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a nonpolar InAlN/GaN high electron mobility transistor and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
the embodiment of the invention provides a preparation method of a nonpolar InAlN/GaN high electron mobility transistor, which comprises the following steps:
s1, growing a nucleation layer material on the substrate to form a nucleation layer;
s2, growing GaN on the nucleation layer under a first condition to form a nonpolar buffer layer;
s3, growing GaN on the nonpolar buffer layer under a second condition to form a nonpolar channel layer;
s4, growing InAlN on the nonpolar channel layer to form a nonpolar barrier layer;
s5, manufacturing a source electrode and a drain electrode in the nonpolar channel layer and the nonpolar barrier layer, and manufacturing a grid electrode on the nonpolar barrier layer to obtain the nonpolar InAlN/GaN high electron mobility transistor.
In an embodiment of the present invention, step S1 is preceded by:
and carrying out nitridation treatment on the substrate, wherein the temperature of the nitridation treatment is 828-1012 ℃.
In one embodiment of the present invention, the first condition is: the temperature range of the base is 900-1100 ℃, the pressure range of the reaction chamber is 9-11 Torr, the ratio of the first flow of the N source to the first flow of the Ga source is 9: 1-11: 1.
in one embodiment of the present invention, the second condition is: the temperature range of the base is 900-1100 ℃, the pressure range of the reaction chamber is 9-11 Torr, the ratio range of the second flow of the N source to the second flow of the Ga source is 9: 1-11: 1, wherein the ratio of the second Ga source flow to the first Ga source flow is 1: 9-1: 11, and the ratio of the second N source flow to the first Ga source flow is 1: 9-1: 11.
In one embodiment of the present invention, step S4 includes:
s41, growing AlN on the nonpolar channel layer to form an insertion layer;
and S42, growing InAlN on the insertion layer to form the nonpolar barrier layer.
In one embodiment of the invention, the growth conditions of the non-polar barrier layer are: the temperature range of the base is 650-800 ℃, the pressure range of the reaction chamber is 180-220 Torr, the flow ratio of the third flow of the N source to the Al source is 75-92, and the flow ratio of the third flow of the N source to the In source is 11-14.
In one embodiment of the invention, the material of the non-polar barrier layer is In1-xAlxN, wherein x ranges from 80% to 85%.
In one embodiment of the present invention, step S5 includes:
s51, depositing a first metal on the nonpolar barrier layer by using a metal evaporation method, and annealing the first metal to enable the first metal to sink to the nonpolar channel layer to form a source electrode and a drain electrode;
s52, etching the nonpolar barrier layer, the nonpolar channel layer and the nonpolar buffer layer to form an isolation groove;
and S53, depositing a second metal on the nonpolar barrier layer by using a metal evaporation method to form a grid electrode.
In one embodiment of the present invention, after the source, the drain and the gate are fabricated on the non-polar barrier layer, the method further comprises:
s6, depositing SiN on the nonpolar barrier layer, the source electrode, the drain electrode and the grid electrode by using a plasma enhanced chemical vapor deposition method to form a protective layer;
and S7, photoetching an interconnection opening region on the protective layer, and manufacturing a metal interconnection layer in the interconnection opening region.
The embodiment of the invention also provides a nonpolar InAlN/GaN high electron mobility transistor which is prepared by the preparation method.
Compared with the prior art, the invention has the beneficial effects that:
1. according to the preparation method of the nonpolar InAlN/GaN high electron mobility transistor, the nonpolar buffer layer, the channel layer and the barrier layer are formed under certain process conditions, the nonpolar channel layer and the nonpolar barrier layer form a nonpolar heterostructure, and the nonpolar heterostructure can modulate spontaneous polarization and piezoelectric polarization, so that the generation of high-density polarization charges in the channel is inhibited, and the enhancement effect is realized.
2. The preparation method only depends on the growth control of the in-situ material, avoids the damage of the processes such as etching, ion implantation and the like to the material device, greatly improves the repeatability and stability of the process, ensures the performance and reliability of the enhancement device and can realize the large-scale preparation of the enhancement device.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a nonpolar InAlN/GaN high electron mobility transistor according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a nonpolar InAlN/GaN high electron mobility transistor according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a c-axis direction and a gate direction of a nonpolar InAlN/GaN high electron mobility transistor according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of another non-polar InAlN/GaN HEMT structure according to an embodiment of the present invention;
fig. 5 is a schematic view of another structure of a nonpolar InAlN/GaN high electron mobility transistor according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a flowchart of a method for manufacturing a nonpolar InAlN/GaN high electron mobility transistor according to an embodiment of the present invention, where the method includes the following steps:
s1, growing a nucleation layer material on the substrate to form a nucleation layer;
s2, growing GaN on the nucleation layer under a first condition to form a nonpolar buffer layer;
s3, growing GaN on the nonpolar buffer layer under a second condition to form a nonpolar channel layer;
s4, growing InAlN on the nonpolar channel layer to form a nonpolar barrier layer;
s5, manufacturing a source electrode and a drain electrode in the nonpolar channel layer and the nonpolar barrier layer, and manufacturing a grid electrode on the nonpolar barrier layer to obtain the nonpolar InAlN/GaN high electron mobility transistor.
Specifically, step S1 is preceded by:
nitriding the substrate at 828-1012 ℃; preferably, the treatment temperature is 920 ℃.
Specifically, the first condition is as follows: the temperature range of the base is 900-1100 ℃, the pressure range of the reaction chamber is 9-11 Torr, and the ratio range of the first flow of the N source to the first flow of the Ga source is 9: 1-11: 1; preferably, the temperature of the base is 1000 ℃, the pressure range of the reaction chamber is 10Torr, and the ratio of the first flow of the N source to the first flow of the Ga source is 10; further, it is preferable that the N source first flow rate be 1000sccm and the Ga source first flow rate be 100 sccm.
Specifically, the second condition is: the temperature range of the base is 900-1100 ℃, the pressure range of the reaction chamber is 9-11 Torr, the ratio range of the second flow of the N source to the second flow of the Ga source is 9: 1-11: 1, the ratio of the second flow rate of the Ga source to the first flow rate of the Ga source is 1: 9-1: 11, and the ratio of the second flow rate of the N source to the first flow rate of the N source is 1: 9-1: 11; preferably, the temperature of the base is 1000 ℃, the pressure range of the reaction chamber is 10Torr, the ratio of the second flow of the N source to the second flow of the Ga source is 10, the ratio of the second flow of the Ga source to the first flow of the Ga source is 10, and the ratio of the second flow of the N source to the first flow of the N source is 10; further, it is preferable that the second flow rate of the N source is 100sccm, and the second flow rate of the Ga source is 10 sccm.
Specifically, step S4 includes:
s41, growing AlN on the nonpolar channel layer to form an insertion layer;
and S42, growing InAlN on the insertion layer to form a nonpolar barrier layer.
Specifically, the growth conditions of the nonpolar barrier layer are as follows: the temperature range of the base is 648-792 ℃, the pressure range of the reaction chamber is 180-220 Torr, the flow ratio of the third flow of the N source to the Al source is 75-92, and the flow ratio of the third flow of the N source to the In source is 11-14;
preferably, the growth temperature of the susceptor is 720 ℃, the pressure of the reaction chamber is 200Torr, the ratio of the third flow of the N source to the flow of the Al source is 83, and the ratio of the third flow of the N source to the flow of the In source is 12.5;
preferably, the flow rate of the Al source is 12sccm, the third flow rate of the N source is 1000sccm, and the flow rate of the In source is 80 sccm.
Specifically, the nonpolar barrier layer is made of In1-xAlxN, wherein x ranges from 80% to 85%; preferably, x is 82%.
Specifically, step S5 includes:
s51, depositing a first metal on the nonpolar barrier layer by using a metal evaporation method, and annealing the first metal to enable the first metal to sink to the nonpolar channel layer to form a source electrode and a drain electrode;
s52, etching the nonpolar barrier layer, the nonpolar channel layer and the nonpolar buffer layer to form an isolation groove;
and S53, depositing a second metal on the nonpolar barrier layer by using a metal evaporation method to form a grid electrode.
Specifically, after the source electrode, the drain electrode and the gate electrode are fabricated on the non-polar barrier layer, the method further comprises the following steps:
s6, depositing SiN on the nonpolar barrier layer, the source electrode, the drain electrode and the grid electrode by using a plasma enhanced chemical vapor deposition method to form a protective layer;
and S7, photoetching an interconnection opening region on the protective layer, and manufacturing a metal interconnection layer in the interconnection opening region.
The preparation method of the nonpolar InAlN/GaN high electron mobility transistor provided by the embodiment of the invention can form the nonpolar buffer layer, the channel layer and the barrier layer, the nonpolar channel layer and the nonpolar barrier layer form the nonpolar heterostructure, and the nonpolar heterostructure can modulate spontaneous polarization and piezoelectric polarization, so that the generation of high-density polarization charges in the channel is inhibited, and the effect of enhancing the device is realized.
The preparation method provided by the embodiment of the invention only depends on growth control of the in-situ material, avoids damage of processes such as etching and ion implantation to a material device, greatly improves the process repeatability and stability, ensures the performance and reliability of an enhancement device, and can realize large-scale preparation of the enhancement device.
Example two
Referring to fig. 2, fig. 2 is a schematic structural diagram of a nonpolar InAlN/GaN high electron mobility transistor according to an embodiment of the present invention, which is described in detail by taking an insulating m-plane sapphire as a substrate 101 and fabricating a nonpolar smectic lattice matching InAlN/GaN high electron mobility transistor with a gate direction parallel to a c-axis direction as an example, and includes the following specific steps:
s1, the insulating sapphire substrate 101 is subjected to a high-temperature nitriding process.
Placing pure insulating sapphire above the graphite base to ensure the normal floating of the substrate, and then putting the graphite base into a reaction chamber to ensure the capability of the baseNormal rotation and revolution can be realized; opening a vacuum pump of the reaction chamber to vacuumize the reaction chamber, so that the vacuum degree of the reaction chamber is lower than 1 x 10-2Torr; introducing a mixed gas of high-purity ammonia gas and hydrogen gas into a reaction chamber, and simultaneously continuing to work by a vacuum pump of the reaction chamber to ensure that the pressure of the high-purity ammonia gas in the reaction chamber is 40 Torr; heating the graphite base by a radio frequency source, raising the temperature of the graphite base to 920 ℃ within 7min, and keeping the temperature for 5 min.
The high-temperature nitridation process of the sapphire substrate can eliminate the adverse factors such as dangling bonds attached to the surface of the sapphire substrate, and can simultaneously nitride Al atoms on the surface of the sapphire substrate to form an AlN pre-reaction layer, thereby providing a good substrate for subsequent reaction.
S2, growing nucleation layer material on the substrate 101 to form a nucleation layer, wherein the nucleation layer includes a low temperature AlN nucleation layer 1021 and a high temperature AlN nucleation layer 1022. The method comprises the following steps:
s21, growing AlN on the substrate 101 to form a low-temperature AlN nucleating layer 1021;
controlling the temperature of the graphite base (the temperature of the graphite base is the growth temperature of each layer of material) to gradually reduce the temperature to 620 ℃, taking hydrogen as carrier gas to carry Al source trimethyl aluminum, simultaneously introducing ammonia gas as N source, and keeping the pressure in the reaction chamber in a dynamic balance of 40 Torr; wherein, the hydrogen flow is 800sccm, the ammonia flow is 1500sccm, and the trimethylaluminum flow is 6 sccm; grown under these conditions for 5 minutes, corresponding to a 30nm thick low temperature AlN nucleation layer 1021.
The low temperature AlN nucleation layer 1021 may be effective to relieve stress between the sapphire substrate and the epitaxial material.
S22, growing AlN on the low-temperature AlN nucleating layer 1021 to form a high-temperature AlN nucleating layer 1022;
controlling the temperature of the graphite base to gradually rise to 1070 ℃, taking hydrogen as carrier gas to carry Al source trimethylaluminum, introducing ammonia gas as N source, and keeping the pressure in the reaction chamber in a dynamic balance of 40 Torr; wherein, the hydrogen flow is 800sccm, the ammonia flow is 3000sccm, and the trimethylaluminum flow is 12 sccm; under the condition, the reaction growth time of ammonia gas and trimethylaluminum is 20 minutes, and the growth thickness of the correspondingly formed high-temperature AlN is 200 nm.
The high-temperature AlN nucleating layer can improve the lateral growth rate of AlN and prepare for subsequent two-dimensional growth.
The low-temperature AlN nucleation layer 1021 and the high-temperature AlN nucleation layer 1022 together form a nucleation layer, and the total thickness of the nucleation layer is 230 nm.
S3, growing GaN on the nucleation layer to form a nonpolar buffer layer 103;
controlling the temperature of the graphite base to gradually reduce the temperature to 1000 ℃, simultaneously introducing a reaction source Ga source and an N source into the reaction chamber, enabling the flow ratio of the N source to the Ga source to be 10, and keeping the pressure in the reaction chamber in dynamic balance of 10 Torr; wherein, the Ga source is trimethyl gallium, and the flow rate is 100 sccm; the Ga source is carried into the reaction chamber by taking hydrogen as carrier gas, and the flow of the carrier gas and the hydrogen is 800 sccm; the N source is ammonia gas, and the flow rate of the ammonia gas is 1000 sccm; under the condition, the reaction growth time of trimethyl gallium and ammonia gas is 60 minutes, and the thickness of the correspondingly formed nonpolar buffer layer 103 is 1500 nm.
Further, the requirements for forming the non-polar structure are as follows: higher growth temperature, lower reaction chamber pressure, and lower flow ratio of group V to group III sources; in this embodiment, the growth temperature of the nonpolar buffer layer 103 is 1000 ℃, the pressure of the reaction chamber is 10Torr, and the flow ratio of the N source to the Ga source is 10, all of which conform to the growth conditions of the nonpolar structure, and the buffer layer formed under these conditions is nonpolar.
S4, growing GaN on the nonpolar buffer layer to form a nonpolar channel layer 104;
maintaining the temperature of the graphite base at 1000 ℃ and the pressure of the reaction chamber at 10Torr, reducing the flow of carrier gas hydrogen to 80sccm, reducing the flow of N source, namely ammonia gas, to 100sccm, and reducing the flow of Ga source, namely trimethyl gallium, to 10 sccm; under the condition, the reaction growth time of trimethyl gallium and ammonia gas is 40 minutes, and the thickness of the non-polar channel layer 104 formed correspondingly is 200 nm.
Furthermore, the N source flow and the Ga source flow for growing the non-polar channel layer 104 are all one tenth of the N source flow and the Ga source flow for growing the non-polar buffer layer 103, so that the growth rate of the non-polar channel layer 104 is also one tenth of the growth rate of the non-polar buffer layer 103, and the material crystal quality of the non-polar channel layer can be ensured to be high, thereby ensuring the drift rate of electrons in the non-polar channel layer.
Further, the growth temperature for growing the nonpolar channel layer 104 was 1000 ℃, the pressure of the reaction chamber was 10Torr, and the flow ratio of the N source to the Ga source was 10, which was in accordance with the growth conditions of the nonpolar structure, under which the channel layer formed was nonpolar.
S5, InAlN is grown on the nonpolar channel layer 104 to form the nonpolar barrier layer 105. The method comprises the following steps:
s51, growing AlN on the nonpolar channel layer 104 to form an insertion layer 1041;
maintaining the temperature of the graphite base at 1000 ℃ and the pressure of the reaction chamber at 10Torr, and introducing an N source and an Al source into the reaction chamber; wherein, the Al source is trimethylaluminum with the flow rate of 5 sccm; the Al source is carried into the reaction chamber by taking hydrogen as carrier gas, and the flow of the carrier gas and the hydrogen is 200 sccm; the N source is ammonia gas, and the flow rate of the ammonia gas is 100 sccm; under this condition, trimethylaluminum reacts with ammonia gas for a growth time of 0.5 minutes, and the thickness of the corresponding insertion layer 1041 formed is 2 nm.
S52, growing InAlN on the insertion layer 1041 to form the nonpolar barrier layer 105;
gradually reducing the temperature of the graphite base to 720 ℃, simultaneously introducing a reaction source Al source, an In source and an N source into the reaction chamber, enabling the flow ratio of the N source to the Al source to be 10 and the flow ratio of the N source to the In source to be 12.5, and keeping the pressure In the reaction chamber In a dynamic balance of 200 Torr; wherein, the Al source is trimethylaluminum, and the flow rate is 12 sccm; the Al source is carried into the reaction chamber by taking hydrogen as carrier gas, and the flow of the carrier gas and the hydrogen is 800 sccm; the N source is ammonia gas, and the flow rate of the ammonia gas is 1000 sccm; the In source is trimethyl indium, and the flow rate of the In source is 80 sccm; the In source is taken into the reaction chamber by taking nitrogen as carrier gas; under these conditions, the growth time was 5 minutes, and the thickness of the non-polar barrier layer 105 correspondingly formed was 12nm, and the Al composition in the non-polar barrier layer 105 was 82%.
Further, In this example, the growth temperature was 720 ℃, the pressure In the reaction chamber was 200Torr, the flow ratio of the N source to the Al source was 83, and the flow ratio of the N source to the In source was 12.5, which met the growth conditions of the nonpolar structure, and the barrier layer formed under these conditions was nonpolar.
Further, the flow rate of the In source is higher than that of the Al source, because the bonding energy between the indium atoms and the nitrogen atoms is low, and therefore, the indium-rich environment In the reaction chamber should be maintained when the nonpolar InAlN is grown.
Furthermore, 82% of Al in the nonpolar barrier layer 105 can realize smectic lattice matching between the barrier layer and the channel layer, and under the condition of the components, the heterostructure keeps a larger energy band offset between the barrier layer and the channel layer on the basis of ensuring that the concentration of intrinsic two-dimensional electron gas in the channel is lower, ensures that a deep potential well is still formed at the channel, and improves the confinement property of a current carrier in the channel.
Further, an ultra-thin insertion layer 1041 is grown between the nonpolar channel layer 104 and the nonpolar barrier layer 105, because the insertion layer can form an effective barrier between the nonpolar barrier layer and the nonpolar channel layer, and prevent the wave function of the two-dimensional electron gas from diffusing into the nonpolar barrier layer, thereby preventing the alloy disorder scattering in the ternary barrier material from adversely affecting the transport of the two-dimensional electron gas; moreover, the growth conditions of the barrier layer and the channel layer are different, the condition conversion process can cause the influences of uneven airflow, unstable temperature and the like in the reaction chamber, the insertion layer can play a transition role in the conversion of the growth conditions, and the adverse influence of the growth condition mutation on the heterojunction characteristics is effectively eliminated; in addition, the insertion layer can play a role in smoothing the appearance of an interface to a great extent, inhibiting the roughness scattering of the interface and improving the performance of the device.
Furthermore, the inserted layer is made of AlN, the forbidden bandwidth of AlN is large, the heterojunction energy band structure can be modulated by using the advantage of large forbidden bandwidth of AlN, the band step height between the barrier layer and the channel layer is obviously improved, the depth of a potential well is increased, and the domain limitation of two-dimensional electron gas in the channel is improved.
S6, forming a source 106 and a drain 107 in the non-polar channel layer 104 and the non-polar barrier layer 105, and forming a gate 108 on the non-polar barrier layer 105, the steps are as follows:
s61, depositing a first metal on the non-polar barrier layer 105 by a metal evaporation method, and annealing the first metal to make the first metal sink to the non-polar channel layer 104 to form a source electrode 106 and a drain electrode 107;
first, a source electrode region and a drain electrode region are etched on the nonpolar barrier layer 105; then, depositing a first metal on the nonpolar barrier layer 105 in the source electrode region and the drain electrode region and on the photoresist outside the source electrode region and the drain electrode region, wherein the first metal is an ohmic metal and has a metal stack structure composed of four layers of metals, the four layers of metals are sequentially Ti, Al, Ni and Au from bottom to top, and the thicknesses of the four layers of metals are 220/1400/550/450 a respectively; then, stripping the ohmic metal on the photoresist outside the source electrode area and the drain electrode area; finally, the sample subjected to ohmic metal evaporation and peeling is placed into a rapid thermal annealing furnace for annealing treatment, so that the ohmic metal on the nonpolar barrier layer 105 in the source electrode region and the drain electrode region sinks to the nonpolar channel layer 104, thereby forming ohmic contact between the ohmic metal and the heterojunction channel and forming the source electrode 106 and the drain electrode 107. Wherein the annealing treatment process conditions in the rapid thermal annealing furnace are as follows: annealing atmosphere is N2The annealing temperature was 850 ℃ and the annealing time was 30 s.
Further, a connection line between center points of the surfaces of the source 106 and the drain 107 is parallel to a c-axis direction on the nonpolar barrier layer 105, the c-axis direction is along a horizontal direction of the nonpolar barrier layer 105, please refer to fig. 3, fig. 3 is a schematic view illustrating the c-axis direction and the gate direction of the nonpolar InAlN/GaN high electron mobility transistor according to the embodiment of the present invention, wherein a connection line between a center point a of the source 106 and a center point B of the drain 107 is parallel to the c-axis direction, and the gate 108 is located on the connection line between a and B, so the gate 108 is parallel to the c-axis.
S62, etching the non-polar barrier layer 105, the non-polar channel layer 104 and the non-polar buffer layer 103 to form an isolation trench 1071;
photoetching an electric isolation area on the nonpolar barrier layer 105 by adopting the processes of gluing, drying glue, exposing, developing and stripping, then washing the sample with ultrapure water and drying the sample with nitrogen, and baking the sample on a hot plate at 110 ℃ for 2 min; then, sequentially etching the nonpolar barrier layer 105, the insertion layer 1041 and the nonpolar channel layer 104 in the electrical isolation region by using an Inductively Coupled Plasma (ICP) process to realize mesa isolation of the active region, wherein the total etching depth is 500 nm; finally, the sample is sequentially placed into an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the electrical isolation region, and then the sample is rinsed with ultrapure water and dried with nitrogen to form an isolation trench 1071.
When the insertion layer 1041 is grown between the nonpolar barrier layer 105 and the nonpolar channel layer 104, the nonpolar barrier layer 105, the insertion layer 1041, and the nonpolar channel layer 104 are etched, thereby forming the isolation trench 1071; when there is no intervening layer 1041 between the non-polar barrier layer 105 and the non-polar channel layer 104, the non-polar barrier layer 105 and the non-polar channel layer 104 are etched, thereby forming an isolation trench 1071.
S63, depositing a second metal on the non-polar barrier layer 105 by a metal evaporation method to form a gate 108;
photoetching a gate electrode area on the nonpolar barrier layer 105 by adopting processes of gluing, drying glue, exposing, developing and stripping, controlling the direction of a grid bar (the gate electrode area is generally rectangular, and the direction of a long edge in the rectangle is the direction of the grid bar) to be parallel to the c-axis direction of the surface of the epitaxial wafer, and washing a sample with ultrapure water and drying the sample with nitrogen; then, evaporating a second metal as a gate on the nonpolar barrier layer 105 in the gate electrode region and on the photoresist outside the gate electrode region, wherein the second metal is a schottky metal and is a metal stack structure composed of two layers of metals, the metal stack structure is sequentially Ni and Au from bottom to top, and the thicknesses of Ni and Au are 550/450 a respectively; and finally, putting the sample subjected to gate metal evaporation into acetone for ultrasonic treatment, wherein the ultrasonic time is set to 10min to remove the Schottky metal and the photoresist outside the gate electrode, then putting the sample into an NMP solution for ultrasonic removal of the stripping glue, washing the sample with isopropanol and ultrapure water, and drying with nitrogen to form the gate 108.
Further, the gate direction is determined by the relative orientation of the source and the drain, so that when the source and the drain are fabricated, the line connecting the drain and the source is parallel to the c-axis direction, and since the gate is located between the drain and the source, the gate is parallel to the c-axis direction, as shown in fig. 3.
S7, depositing SiN on the non-polar barrier layer 105, the source 106, the drain 107 and the gate 108 by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method to form a protective layer 109; the method comprises the following specific steps:
cleaning the surface of the sample with the manufactured gate 108, growing 200nm SiN on the nonpolar barrier layer 105, the source electrode 106, the drain electrode 107 and the gate 108 by using a PECVD process to form a protective layer 109, wherein the growth process conditions are as follows: by NH3And SiH4As the reaction gas, the substrate temperature was 300 ℃, the reaction chamber pressure was 600mTorr, and the RF power was 30W.
S8, etching an interconnect via region on the protection layer 109, and forming a metal interconnect layer 110 on the interconnect via region; the method comprises the following specific steps:
manufacturing metal interconnection open hole regions of a source electrode 106, a drain electrode 107 and a grid electrode 108 on the protective layer 109 by adopting the processes of gluing, drying glue, exposing, developing, stripping and the like, and carrying out ultra-pure water washing and nitrogen blow-drying on a sample; then, etching the protection layer 109 in the metal interconnection open region to form a metal interconnection open structure; then, depositing interconnection metal on the protective layer 109 in the metal interconnection open pore structure and outside the metal interconnection open pore structure by using an electron beam evaporation process, wherein the interconnection metal is a metal stack structure consisting of two layers of metal and sequentially comprises Ti and Au from bottom to top; finally, putting a sample subjected to interconnection metal evaporation into acetone for ultrasonic treatment, wherein the ultrasonic time is set to 10min to remove interconnection metal and photoresist outside an interconnection region, then putting the sample into an N-methyl-2-pyrrolidone (commonly called NMP) solution for ultrasonic removal of stripping glue, washing the sample with isopropanol and ultrapure water, and drying with nitrogen to form a metal interconnection layer 110, and leading out a source electrode 106, a drain electrode 107 and a grid electrode 108 from the metal interconnection layer 110; finally, a nonpolar InAlN/GaN high electron mobility transistor with a gate direction parallel to the c-axis is obtained, as shown in fig. 2, the nonpolar InAlN/GaN high electron mobility transistor with a sapphire substrate includes: a sapphire substrate 101; a low-temperature AlN nucleation layer 1021 on the substrate 101; a high-temperature AlN nucleation layer 1022 on the low-temperature AlN nucleation layer 1021; a non-polar buffer layer 103 on the high-temperature AlN nucleation layer 1022; a non-polar channel layer 104 on the non-polar buffer layer 103; an insertion layer 1041 on the non-polar channel layer 104; a non-polar barrier layer 105 on the insertion layer 1041; a source 106 on the non-polar channel layer 104; a drain 107 on the non-polar channel layer 104; a gate 108 on the non-polar barrier layer 105, with the gate 108 oriented parallel to the c-axis; a protective layer 109 covering the nonpolar barrier layer 105, the source electrode 106, the drain electrode 107, and the gate electrode 108; and a metal interconnection layer 110 on the source electrode 106, the drain electrode 107 and the gate electrode 108.
The preparation method provided by the embodiment of the invention only depends on growth control of the in-situ material, avoids damage of processes such as etching and ion implantation to a material device, greatly improves the process repeatability and stability, ensures the performance and reliability of an enhancement device, and can realize large-scale preparation of the enhancement device.
In the nonpolar InAlN/GaN high electron mobility transistor, the transport rate of carriers along the direction of the c axis is higher than that of carriers in each direction in the c plane, so that the relative direction of a source electrode and a drain electrode is controlled, the direction of a grid electrode is controlled, the effective transport direction of the carriers is parallel to the c axis, and the performance of a device is improved.
EXAMPLE III
On the basis of the first embodiment and the second embodiment, in this embodiment, a nonpolar smectic lattice matching InAlN/GaN high mobility transistor is fabricated on a semi-insulating SiC substrate, please refer to fig. 4, and fig. 4 is a schematic view of another structure of a nonpolar InAlN/GaN high electron mobility transistor provided in the embodiment of the present invention.
The method comprises the following specific steps:
s1, the semi-insulating SiC substrate 201 is subjected to high-temperature nitriding.
Placing a pure semi-insulating SiC substrate 201 above a graphite base to ensure the normal floating of the substrate, and then placing the graphite base into a reaction chamberThe normal rotation and revolution of the base can be ensured; opening a vacuum pump of the reaction chamber to vacuumize the reaction chamber, so that the vacuum degree of the reaction chamber is lower than 1 x 10-2Torr; introducing a mixed gas of high-purity ammonia gas and hydrogen gas into a reaction chamber, and simultaneously continuing to work by a vacuum pump of the reaction chamber to ensure that the pressure of the high-purity ammonia gas in the reaction chamber is 40 Torr; heating the graphite base by a radio frequency source, raising the temperature of the graphite base to 920 ℃ within 7min, and keeping the temperature for 5 min.
The influence of adverse factors such as dangling bonds attached to the surface of the SiC substrate can be eliminated in the high-temperature nitridation process of the SiC substrate, and a good substrate is provided for subsequent reactions.
S2, growing AlN on the substrate 201 to form a nucleating layer 202; the method comprises the following steps:
controlling the temperature of the graphite base to gradually rise to 1070 ℃, taking hydrogen as carrier gas to carry Al source trimethylaluminum, introducing ammonia gas as N source, and keeping the pressure in the reaction chamber in a dynamic balance of 40 Torr; wherein, the hydrogen flow is 800sccm, the ammonia flow is 3000sccm, and the trimethylaluminum flow is 12 sccm; under the condition, the reaction growth time of ammonia gas and trimethylaluminum is 20 minutes, and the growth thickness of the correspondingly formed high-temperature AlN is 200 nm.
It should be noted that, because the lattice mismatch between the SiC substrate and the epitaxial structure is small, the high-temperature AlN nucleation layer 202 is directly grown after the high-temperature nitridation of the SiC substrate is completed, and the formed high-temperature AlN nucleation layer 202 can increase the lateral growth rate of the epitaxial material, so as to prepare for the subsequent two-dimensional growth.
In steps S3 to S8, please refer to example two, and finally obtain the nonpolar InAlN/GaN high electron mobility transistor with the SiC substrate, please refer to fig. 4.
The nonpolar InAlN/GaN high electron mobility transistor with the SiC substrate comprises: a SiC substrate 201; a high-temperature AlN nucleation layer 202 on the SiC substrate 201; a non-polar buffer layer 203 on the high temperature AlN nucleation layer 202; a non-polar channel layer 204 on the non-polar buffer layer 203; an intervening layer 2041 on the nonpolar channel layer 204; a non-polar barrier layer 205 on the intervening layer 2041; a source 206 on the non-polar channel layer 204; a drain 207 on the non-polar channel layer 204; a gate 208 on the non-polar barrier layer 205, the gate 208 oriented parallel to the c-axis; an isolation trench 2071 formed by etching the nonpolar barrier layer 205, the insertion layer 2041 and the nonpolar channel layer 204 of the electrical isolation region to achieve mesa isolation of the active region; a protective layer 209 covering the non-polar barrier layer 205, the source electrode 206, the drain electrode 207, and the gate electrode 208; and a metal interconnection layer 210 on the source 206, the drain 207 and the gate 208.
Example four
On the basis of the first and second embodiments, in this embodiment, a nonpolar smectic lattice matching InAlN/GaN high mobility transistor is fabricated on a semi-insulating Si substrate, please refer to fig. 5, and fig. 5 is a schematic view of another structure of a nonpolar InAlN/GaN high electron mobility transistor provided in the embodiments of the present invention.
The method comprises the following specific steps:
s1, the semi-insulating Si substrate 301 is subjected to high-temperature nitridation processing.
Because the Si substrate can react with ammonia gas to generate SiN under high temperature conditions, and the SiN adversely affects subsequent epitaxy, a trimethyl aluminum source needs to be introduced into the reaction chamber before high-temperature nitridation treatment, so that aluminum atoms are deposited on the surface of the substrate to protect the substrate. Then, introducing a mixed gas of high-purity ammonia gas and hydrogen gas into the reaction chamber, and simultaneously, continuously operating a vacuum pump of the reaction chamber to ensure the high-purity ammonia gas atmosphere of 40Torr in the reaction chamber; finally, the graphite susceptor was heated by a radio frequency source to increase the temperature of the graphite susceptor to 920 ℃ over a period of 7 minutes and held at that temperature for 5 minutes.
The high-temperature nitridation process of the semi-insulating Si substrate not only can play a role in protecting the substrate, but also can eliminate adverse factors such as dangling bonds attached to the surface of the Si substrate and the like, and provides a good substrate for subsequent reactions.
S2, growing nucleation layer material on the substrate 301 to form nucleation layers, wherein the nucleation layers include a low-temperature AlN nucleation layer 3021, a high-temperature AlN nucleation layer 3022, and a graded AlGaN nucleation layer 3023. The method comprises the following steps:
s21, AlN is grown on the substrate 301 to form a low-temperature AlN nucleation layer 3021.
Controlling the temperature of the graphite base to gradually reduce the temperature to 620 ℃, taking hydrogen as carrier gas to bring Al source trimethylaluminum, simultaneously introducing ammonia gas as N source, and keeping the pressure in the reaction chamber in a dynamic balance of 40 Torr; wherein, the hydrogen flow is 800sccm, the ammonia flow is 1500sccm, and the trimethylaluminum flow is 6 sccm; growth is carried out under these conditions for 5 minutes, corresponding to a 30nm thick low temperature AlN nucleation layer 3021.
The low-temperature AlN nucleation layer 3021 can effectively relieve the stress between the sapphire substrate and the epitaxial material.
S22, growing AlN on the low-temperature AlN nucleation layer 3021 to form a high-temperature AlN nucleation layer 3022.
Controlling the temperature of the graphite base to gradually rise to 1070 ℃, taking hydrogen as carrier gas to carry Al source trimethylaluminum, introducing ammonia gas as N source, and keeping the pressure in the reaction chamber in a dynamic balance of 40 Torr; wherein, the hydrogen flow is 800sccm, the ammonia flow is 3000sccm, and the trimethylaluminum flow is 12 sccm; under the condition, the reaction growth time of ammonia gas and trimethylaluminum is 20 minutes, and the growth thickness of the correspondingly formed high-temperature AlN is 200 nm.
The high-temperature AlN nucleating layer can improve the lateral growth rate of AlN and prepare for subsequent two-dimensional growth.
S23, AlGaN is grown on the high-temperature AlN nucleation layer 3022, forming a high-temperature AlGaN nucleation layer 3023.
Controlling the temperature of the graphite base to gradually reduce the temperature to 1000 ℃, taking hydrogen as carrier gas to bring the hydrogen into a Ga source and an Al source, simultaneously introducing an N source, and keeping the pressure in the reaction chamber in a dynamic balance of 40 Torr; wherein, the Ga source is trimethyl gallium, and the flow rate of the Ga source is gradually increased from 0sccm to 100 sccm; the Al source is trimethylaluminum, and the flow rate of the Al source is gradually reduced from 12sccm to 0 sccm; the N source is ammonia gas, and the flow rate of the ammonia gas is 3000 sccm; the flow rate of the carrier gas hydrogen is 800 sccm; the growth time under the condition is 40min, and the thickness of the correspondingly formed high-temperature AlGaN nucleation layer 3023 is 600nm, wherein the Al composition is gradually changed from high to low.
The low-temperature AlN nucleating layer 3021, the high-temperature AlN nucleating layer 3022 and the graded AlGaN nucleating layer form a nucleating layer together, and the total thickness of the nucleating layer is 830 nm.
The low-temperature AlN nucleating layer, the high-temperature AlN nucleating layer and the gradient AlGaN nucleating layer are sequentially grown on the Si substrate, because the lattice mismatch between the Si substrate and the epitaxial material is very large, the stress in the epitaxial material can be further released by growing the AlGaN nucleating layer with the Al components gradually changing from high to low, and meanwhile, the generation of a parasitic channel can be avoided.
In steps S3 to S8, please refer to S3 to S8 of the second embodiment, and finally obtain the nonpolar InAlN/GaN high electron mobility transistor with Si substrate, please refer to fig. 5.
The nonpolar InAlN/GaN high electron mobility transistor with the Si substrate comprises: a Si substrate 301; a low-temperature AlN nucleation layer 3021 on the Si substrate 301; a high-temperature AlN nucleation layer 3022 on the low-temperature AlN nucleation layer 3021; a graded AlGaN nucleation layer 3023; on the high temperature AlN nucleation layer 3022; a nonpolar buffer layer 303 on the graded AlGaN nucleation layer 3023; a non-polar channel layer 304 on the non-polar buffer layer 303; an insertion layer 3041 on the nonpolar channel layer 304; a non-polar barrier layer 305 on the intervening layer 3041; a source 306 on the non-polar channel layer 304; a drain 307 on the non-polar channel layer 304; a gate 308 on the non-polar barrier layer 305, the gate 308 oriented parallel to the c-axis; an isolation trench 3071 formed by etching the nonpolar barrier layer 305, the insertion layer 3041, and the nonpolar channel layer 304 of the electrical isolation region to achieve mesa isolation of the active region; a protective layer 309 covering the non-polar barrier layer 305, the source electrode 306, the drain electrode 307, and the gate electrode 308; and a metal interconnection layer 310 on the source 306, the drain 307 and the gate 308.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (7)
1. A preparation method of a nonpolar InAlN/GaN high electron mobility transistor is characterized by comprising the following steps:
s1, growing a nucleation layer material on the substrate (101) to form a nucleation layer;
s2, growing GaN on the nucleation layer in a first condition to form a nonpolar buffer layer (103); the first condition is: the temperature range of the base is 900-1100 ℃, the pressure range of the reaction chamber is 9-11 Torr, the ratio of the first flow of the N source to the first flow of the Ga source is 9: 1-11: 1;
s3, growing GaN on the nonpolar buffer layer (103) under a second condition to form a nonpolar channel layer (104); the second condition is: the temperature range of the base is 900-1100 ℃, the pressure range of the reaction chamber is 9-11 Torr, the ratio range of the second flow of the N source to the second flow of the Ga source is 9: 1-11: 1, wherein the ratio of the second Ga source flow to the first Ga source flow is 1: 9-1: 11, and the ratio of the second N source flow to the first Ga source flow is 1: 9-1: 11;
s4, growing InAlN on the nonpolar channel layer (104) to form a nonpolar barrier layer (105); the growth conditions of the non-polar barrier layer (105) are as follows: the temperature range of the base is 650-800 ℃, the pressure range of the reaction chamber is 180-220 Torr, the flow ratio of the third flow of the N source to the Al source is 75-92, and the flow ratio of the third flow of the N source to the In source is 11-14;
s5, manufacturing a source electrode (106) and a drain electrode (107) in the nonpolar channel layer (104) and the nonpolar barrier layer (105), and manufacturing a grid electrode (108) on the nonpolar barrier layer (105) to obtain the nonpolar InAlN/GaN high electron mobility transistor.
2. The method of claim 1, wherein step S1 is preceded by the step of:
and performing nitridation treatment on the substrate (101), wherein the nitridation treatment temperature is 828-1012 ℃.
3. The method of claim 1, wherein step S4 includes:
s41, growing AlN on the nonpolar channel layer (104) to form an insertion layer (1041);
s42, InAlN is grown on the insertion layer (1041), and the nonpolar barrier layer (105) is formed.
4. The method of claim 1, wherein the nonpolar InAlN/GaN high electron mobility transistor is formed from a nonpolar barrier layer (105) of In1-xAlxN, wherein x ranges from 80% to 85%.
5. The method of claim 1, wherein step S5 includes:
s51, depositing a first metal on the nonpolar barrier layer (105) by using a metal evaporation method, and annealing the first metal to enable the first metal to sink to the nonpolar channel layer (104) to form a source electrode (106) and a drain electrode (107);
s52, etching the nonpolar barrier layer (105), the nonpolar channel layer (104) and the nonpolar buffer layer (103) to form an isolation trench (1071);
and S53, depositing a second metal on the nonpolar barrier layer (105) by using a metal evaporation method to form a grid electrode (108).
6. The method of claim 1, wherein the step of forming the non-polar InAlN/GaN high electron mobility transistor further comprises, after forming the source (106), drain (107), and gate (108) on the non-polar barrier layer (105):
s6, depositing SiN on the nonpolar barrier layer (105), the source electrode (106), the drain electrode (107) and the grid electrode (108) by using a plasma enhanced chemical vapor deposition method to form a protective layer (109);
s7, photoetching an interconnection opening area on the protective layer (109), and manufacturing a metal interconnection layer (110) in the interconnection opening area.
7. A non-polar InAlN/GaN high electron mobility transistor made by the method of any of claims 1-6.
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| CN104393039A (en) * | 2014-10-23 | 2015-03-04 | 西安电子科技大学 | InAlN/AlGaN enhanced-type high-electron mobility transistor and manufacturing method thereof |
| CN106033724A (en) * | 2015-03-09 | 2016-10-19 | 中国科学院苏州纳米技术与纳米仿生研究所 | III-family nitride reinforced HEMT and preparation method thereof |
| CN107481928A (en) * | 2017-07-25 | 2017-12-15 | 西安电子科技大学 | The preparation method of Schottky diode based on non-polar GaN body material |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104393039A (en) * | 2014-10-23 | 2015-03-04 | 西安电子科技大学 | InAlN/AlGaN enhanced-type high-electron mobility transistor and manufacturing method thereof |
| CN106033724A (en) * | 2015-03-09 | 2016-10-19 | 中国科学院苏州纳米技术与纳米仿生研究所 | III-family nitride reinforced HEMT and preparation method thereof |
| CN107481928A (en) * | 2017-07-25 | 2017-12-15 | 西安电子科技大学 | The preparation method of Schottky diode based on non-polar GaN body material |
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| 《Nonpolar AlGaN/GaN metal-insulator-semiconductor heterojunction field-effect transistors with a normally off operation》;KURODA M;《IEEE Transactions on Electron Device》;20100228;第57卷(第2期);368-372 * |
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