CN111682064A - High-performance MIS gate enhanced GaN-based high electron mobility transistor and preparation method thereof - Google Patents

High-performance MIS gate enhanced GaN-based high electron mobility transistor and preparation method thereof Download PDF

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CN111682064A
CN111682064A CN202010489644.7A CN202010489644A CN111682064A CN 111682064 A CN111682064 A CN 111682064A CN 202010489644 A CN202010489644 A CN 202010489644A CN 111682064 A CN111682064 A CN 111682064A
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CN111682064B (en
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郭志友
李渊
夏凡
谭秀洋
马建铖
夏晓宇
张淼
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South China Normal University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Abstract

The invention relates to a high-performance MIS grid enhanced GaN-based high electron mobility transistor and a preparation method thereof, wherein the device comprises an AlGaN layer positioned on a substrate, the AlGaN layer consists of an AlGaN barrier layer, a p-doped drift region and an n-doped drift region which are distributed on two sides of the AlGaN barrier layer, a passivation layer is positioned between a source electrode and a drain electrode, a groove extends into the barrier layer from the passivation layer, fills the p-GaN region of the groove, a grid positioned on the p-GaN region and a field plate contacted with the grid. The n/p doped layers with different gradients are formed on two sides of the barrier layer to inhibit current crowding in a source-drain direction, meanwhile, the p-GaN is connected below the grid electrode, the upper side of the grid electrode is in contact with the field plate, charge crowding below the grid electrode is controlled, electron transportation of the two-dimensional electron gas channel is smoother, adjustable promotion of breakdown voltage is achieved under the condition that high current density and high electron mobility of the device are guaranteed, on-resistance is reduced, and power characteristics and reliability of the device are improved.

Description

High-performance MIS gate enhanced GaN-based high electron mobility transistor and preparation method thereof
Technical Field
The invention relates to the field of high electron mobility transistors, in particular to a high-performance MIS gate enhanced GaN-based high electron mobility transistor and a preparation method thereof.
Background
With the development of clean energy, automation equipment, communication technology, automotive electronics, switching power supplies, the performance of power semiconductor devices is receiving attention. As a representative of the third generation semiconductor materials, GaN-based materials are often used for manufacturing high-temperature, high-frequency and high-power electronic devices due to their characteristics of large forbidden band width, high electron saturation mobility, high thermal conductivity, good stability, high critical breakdown field strength and the like. In addition, the AlGaN/GaN heterostructure after modulation doping has more excellent electron mobility, saturated electron speed and higher two-dimensional electron gas density at room temperature than GaN material and second-generation semiconductor material, and is an ideal material for manufacturing microwave high-power devices, so that the AlGaN/GaN heterojunction high-electron mobility transistor has very good application prospect.
The conventional AlGaN/GaN High Electron Mobility Transistor (HEMT) is a depletion type device, and is inconvenient to use in power conversion applications due to the characteristic that it must be operated by applying a negative bias, so that research into an AlGaN/GaN enhancement type HEMT having a normally-off characteristic has a very important meaning. The AlGaN/GaN enhanced HEMT reduces negative voltage sources, reduces circuit complexity and cost, has good circuit compatibility and has great application prospect.
At present, the AlGaN/GaN enhancement type HEMT manufacturing technology is reported internationally and domestically, and the main new technologies comprise a nanowire channel structure, a thin barrier layer structure, fluorine plasma treatment, a P-GaN cap layer structure, a groove gate Metal Insulator Semiconductor (MIS) structure and the like. The groove gate MIS structure has the characteristics of high threshold voltage, high breakdown voltage, high gate voltage swing and the like, and is a potential excellent technology for manufacturing the enhancement type HEMT.
Although the HEMT with the groove gate MIS structure has higher current density and smaller on-resistance, due to the potential difference between the source-grid and the drain-grid, an electric field is crowded at the side close to the drain to cause the current leakage of a buffer layer, so that ionization impact is easily caused to generate an avalanche process, and the breakdown of a device is caused. Meanwhile, a plurality of electron trap states exist between the dielectric layer and the AlGaN barrier layer, so that the current concentration ratio below the grid from the source electrode to the drain electrode is not uniform, and the AlGaN barrier layer does not fully play a role in bearing reverse withstand voltage in practice, so that the breakdown voltage of the device is often lower than a theoretically expected value.
Disclosure of Invention
The invention aims to overcome the defects of the prior art of the high electron mobility transistor with the groove gate MIS structure and provide a high-performance MIS gate enhanced GaN-based HEMT device and a manufacturing method thereof.
In view of the above purpose, the present invention provides at least the following technical solutions:
the high-performance MIS gate enhanced GaN-based high electron mobility transistor comprises a silicon substrate, an AlN nucleating layer, a GaN buffer layer, an AlGaN layer and a source/drain electrode which are sequentially stacked,
the AlGaN layer consists of a p-doped drift AlGaN region, an n-doped drift AlGaN region and an AlGaN barrier layer, wherein the p-doped drift AlGaN region is positioned below the source electrode, and the n-doped drift AlGaN region is positioned below the drain electrode;
a passivation layer between the source and the drain on the AlGaN layer;
the groove extends to a certain depth in the AlGaN barrier layer along the surface of the passivation layer;
the dielectric layer is positioned on the surface of the passivation layer and extends into the groove;
a p-GaN region filling the groove;
a gate in contact with an upper surface of the p-GaN region;
a field plate in contact with the gate and the dielectric layer.
Further, the Al composition of the p-doped drift AlGaN region and the n-doped drift AlGaN region decreases linearly from the lower surface to the upper surface thereof, the Al composition of the lower surface thereof is 1, and the Al composition of the upper surface thereof is 0.25.
Further, the thickness of the AlGaN layer is 2 μm, and the widths of the p-doped drift AlGaN region and the n-doped drift AlGaN region are both 4 μm.
Further, the depth of the groove extending into the AlGaN barrier layer is 1 μm, and the thickness of the p-GaN region is 3 μm.
Further, the passivation layer is SiN.
Further, the dielectric layer is HfO2。
Further, the thickness of the passivation layer is 2 μm, and the thickness of the dielectric layer is 0.5 μm.
Furthermore, the source/drain electrode is a Ti/Al/Ni/Au ohmic contact composite metal layer, and the grid electrode is a Ni/Au composite metal layer.
The preparation method of the high-performance MIS gate enhanced GaN-based high electron mobility transistor comprises the following steps,
carrying out heat treatment and surface nitridation on the silicon substrate;
sequentially epitaxially growing an AlN nucleating layer, a GaN buffer layer and an AlGaN barrier layer on the surface of the nitrided silicon substrate to form an epitaxial wafer;
etching a predetermined region in the AlGaN barrier layer to form a source region, a drain region and a groove gate region;
epitaxially growing AlGaN with drifting Al components in the source region and the drain region, p-doping the AlGaN in the source region, and n-doping the AlGaN in the drain region to form a p-doped drifting AlGaN region and an n-doped drifting AlGaN region;
depositing a passivation layer;
etching the passivation layer of the groove gate region, and exposing the AlGaN barrier layer to form a gate window;
depositing a dielectric layer;
etching the dielectric layer and the passivation layer above the p-doped drift AlGaN region and the n-doped drift AlGaN region to form a source region pattern and a drain region pattern;
depositing an ohmic contact metal layer in the source region pattern and the drain region pattern to form a source electrode and a drain electrode;
epitaxially growing a p-GaN region on the gate window;
depositing a metal layer in the p-GaN area to form a grid electrode;
and depositing field plate metal on the surfaces of the grid and the dielectric layer.
Further, the step of depositing the dielectric layer comprises the steps of:
adopting a plasma enhanced atomic layer deposition method, firstly carrying out plasma treatment on the groove gate region by using N2 gas of 900sccm at a high temperature of 300 ℃ under 1500W power for 10 minutes, and then depositing HfO with the thickness of 0.5 mu m2A dielectric layer.
Further, the Al composition in the p-doped drift AlGaN region and the n-doped drift AlGaN region decreases linearly from the lower surface to the upper surface of the regions, the Al composition of the lower surface is 1, and the Al composition of the upper surface is 0.25.
Compared with the prior art, the invention has at least the following beneficial effects:
according to the MIS gate enhanced GaN-based high electron mobility transistor, the n/p doped layers with different Al component gradients are respectively formed on the two sides of the AlGaN barrier layer, so that under the guidance of longitudinal Al component increase and transverse p/n polarity, current crowding in the source-drain direction is inhibited, current collapse on the source side is avoided, and the two-dimensional electron gas transmission speed on the drain side is increased. The reverse leakage current is reduced in the off state, the hole is injected under a high field to improve the stability of the on-resistance, the surface electric field and the body electric field below the grid can be effectively adjusted under the high-voltage blocking state, the current leakage of the buffer layer is inhibited, the peak electric field at the grid-drain side is reduced, and the breakdown voltage of the device is improved.
Meanwhile, the p-GaN semiconductor layer is connected to the lower portion of the metal grid, the field plate is arranged on the upper portion of the metal grid, charge crowding below the grid is further controlled, electron transportation of the two-dimensional electron air channel is smoother, the conduction band energy level and the potential profile of the grid to the drain electrode in the off state of the device can be linearly expanded, the current flowing direction in the on state is flatter, and current collapse and voltage breakdown possibly caused by severe potential change are relieved. Under the condition of ensuring high current density and high electron mobility of the device, the breakdown voltage can be improved in an adjustable mode, the on-resistance is reduced, and the power characteristic and the reliability of the device are improved.
Drawings
Fig. 1 is a cross-sectional view of a high performance MIS gate enhanced GaN-based high electron mobility transistor of the present invention.
Fig. 2 is a top view of the high performance MIS gate enhanced GaN-based high electron mobility transistor of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings, and the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, other embodiments obtained by persons of ordinary skill in the art without any creative effort belong to the protection scope of the present invention.
The present invention will be described in further detail below. As shown in fig. 1-2, the present invention provides a high performance MIS gate enhanced GaN-based high electron mobility transistor, which comprises a silicon substrate 1, an AlN nucleation layer 2, a GaN buffer layer 3, and an AlGaN layer, which are sequentially stacked. The AlGaN layer is composed of an AlGaN barrier layer 4, a p-doped drift AlGaN region 5, and an n-doped drift AlGaN region 6.
The passivation layer 7, the source electrode 9 and the drain electrode 10 are on the AlGaN layer, and the passivation layer 7 is between the source electrode 9 and the drain electrode 10. A groove extends along the surface of the passivation layer 7 to a depth into the AlGaN barrier layer 4. The dielectric layer 8 is located on the surface of the passivation layer 7 and extends into the recess. The p-GaN region 11 fills the groove, and the gate 12 is located on the p-GaN region 11 in contact with the upper surface of the p-GaN region 11. A field plate 13 is located at the device surface in contact with the gate 12 and the dielectric layer 8.
A p-doped drift AlGaN region 5 and an n-doped drift AlGaN region 6 are located on either side of the AlGaN barrier layer 4. A p-doped drift AlGaN region 5 is located below the source 9 and an n-doped drift AlGaN region 6 is located below the drain 10. The Al compositions of the p-doped drift AlGaN region 5 and the n-doped drift AlGaN region 6 decrease linearly from the lower surface to the upper surface of the AlGaN region, the Al composition of the lower surface thereof is 1, and the Al composition of the upper surface thereof is 0.25. The n/p doped layers with different gradients are respectively formed on two sides of the AlGaN barrier layer 4, current crowding in the source-drain direction is inhibited, meanwhile, a p-GaN semiconductor is connected below the metal grid, a field plate is added above the metal grid, and charge crowding below the grid is further controlled, so that electron transportation of a two-dimensional electron gas channel is smoother, the adjustable promotion of breakdown voltage is realized under the condition that high current density and high electron mobility of a device are guaranteed, the on-resistance is reduced, and the power characteristic and reliability of the device are improved.
The AlGaN layer has a thickness of 2 μm and the p-doped drift AlGaN region 5 and the n-doped drift AlGaN region 6 each have a width of 4 μm. The thickness of the passivation layer 7 is 2 μm. In a specific embodiment, the passivation layer 7 is preferably SiN. Dielectric layer 8 has a thickness of 0.5 μm, and in one embodiment, dielectric layer 8 is preferably HfO2。
The depth of the recess extending into the AlGaN barrier layer was about 1 μm, and the thickness of the p-GaN region 5 filled into the recess was 3 μm. In one embodiment, the AlN nucleation layer has a thickness of 4 μm and the GaN buffer layer 3 has a thickness of 10 μm on the silicon substrate.
The source electrode 9 and the drain electrode 10 are preferably Ti/Al/Ni/Au ohmic contact complex metal layers, the thickness of the Ti layer is preferably 0.4 μm, the thickness of the Al layer is preferably 1.8 μm, the thickness of the Ni layer is preferably 0.5 μm, and the thickness of the Au layer is preferably 0.8 μm.
The gate electrode 12 is preferably a Ni/Au complex metal layer, and the Ni layer and the Au layer are preferably 0.3 μm and 2.4 μm in thickness, respectively.
The structure of the device will be further explained by the preparation method. The preparation method of the high-performance MIS gate enhanced GaN-based high electron mobility transistor comprises the following steps.
Step 1, carrying out heat treatment and surface nitridation on the silicon substrate.
The substrate is selected from silicon, sapphire or diamond substrate. In this embodiment, the substrate is preferably a silicon substrate. Placing a silicon substrate in a reaction chamber of Metal Organic Chemical Vapor Deposition (MOCVD) equipment, vacuumizing the reaction chamber to 1 x 10 < -2 > Torr, introducing a mixed gas of hydrogen with the flow of 1500sccm and ammonia with the flow of 2000sccm, and carrying out heat treatment and surface nitridation on the silicon substrate under the protective gas, wherein the heating temperature is 1050 ℃ and the pressure is 20 Torr.
And 2, sequentially epitaxially growing an AlN nucleating layer, a GaN buffer layer and an AlGaN barrier layer on the surface of the nitrided silicon substrate to form an epitaxial wafer.
By adopting the MOCVD technology, an AlN nucleating layer with the thickness of 4 mu m is epitaxially grown on a silicon substrate under the process conditions that the temperature is 1050 ℃, the pressure is 20Torr, the flow rates of hydrogen and ammonia are 1500sccm and 2000sccm respectively, and the flow rate of an aluminum source is 30 sccm.
Keeping the temperature and the pressure unchanged, keeping the hydrogen flow unchanged, adjusting the ammonia flow to 6000sccm and the gallium source flow to 220sccm, and extending an undoped GaN buffer layer with the thickness of 10 mu m on the AlN nucleating layer.
On the GaN main buffer layer, MOCVD technique is adopted,
adjusting the temperature to 980 ℃, the pressure to 40Torr, the hydrogen flow to 3800sccm, the ammonia flow to 1800sccm, the gallium source flow to 30 mu mol/min and the aluminum source flow to 5 mu mol/min, and extending AlGaN semiconductor material on the GaN buffer layer to form an AlGaN barrier layer with the thickness of 2 mu m.
And 3, etching a preset region in the AlGaN barrier layer to form a source region, a drain region and a groove gate region.
On the AlGaN barrier layer, a source region with the width of 4 mu m is completely etched in sequence from the source to the drain, a groove gate region with the depth of 1 mu m and the width of 3 mu m is etched in a shallow way after the distance is 3 mu m, and a drain region with the width of 4 mu m is completely etched after the distance is 3 mu m.
And 4, epitaxially growing AlGaN with drifting Al components in the source region and the drain region, carrying out p-doping on the AlGaN in the source region, and carrying out n-doping on the AlGaN in the drain region to form a p-doped drifting AlGaN region and an n-doped drifting AlGaN region.
On a source electrode region and a drain electrode region which are formed by etching, an MOCVD technology is adopted, and under the process conditions that the temperature is 980 ℃, the pressure is 40Torr, the hydrogen flow rate is 3800sccm, the ammonia flow rate is 1800sccm, the gallium source flow rate is 30 mu mol/min and the aluminum source flow rate is linearly increased to 7mol/min from 5 mu mol/min, an AlGaN semiconductor material is extended to form an AlGaN barrier layer with the thickness of 2 mu m and drifting of Al components, wherein the Al component on the lower surface of the AlGaN barrier layer is 1, the Al component on the upper surface of the AlGaN barrier layer is 0.25, and the Al components are linearly decreased from the lower surface to the upper surface. While the AlGaN layer of the source region is implanted with a p-type impurity, preferably magnesium. The AlGaN layer in the drain region is implanted with an n-type impurity, preferably silicon.
And 5, depositing a passivation layer.
And depositing a SiN passivation layer with the thickness of 2 microns on the surface of the exposed AlGaN barrier layer by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) system under the process conditions of ammonia gas flow of 2.5sccm, nitrogen gas flow of 900sccm, silane flow of 200sccm, temperature of 300 ℃, pressure of 900mT and power of 25W.
And 6, etching the passivation layer of the groove gate region, and exposing the AlGaN barrier layer to form a gate window.
And removing the SiN passivation layer of the grid window by means of spin coating, soft baking, exposure and development and wet etching to expose the AlGaN barrier layer.
And 7, depositing a dielectric layer.
Using a plasma enhanced atomic layer deposition system, a high temperature of 300 deg.C, 900sccm of N was used at a processing power of 150W2The gas plasma-treats the gate window region for 10 minutes, then deposits HfO with a thickness of 0.5 μm2A dielectric layer.
And 8, etching the dielectric layer and the passivation layer above the p-doped drift AlGaN region and the n-doped drift AlGaN region to form a source region pattern and a drain region pattern.
In HfO2Depositing a mask layer on the dielectric layer to form a mask pattern, and performing dry etching on the HfO2Layers and SiN layers to form source region patterns and drain region patterns.
And 9, depositing an ohmic contact metal layer in the source region pattern and the drain region pattern to form a source electrode and a drain electrode.
Depositing Ti/Al/Ni/Au four layers of ohmic contact metal on the exposed AlGaN barrier layer by adopting an electron beam evaporator, wherein the thickness of the Ti layer is 0.4 mu m, the thickness of the Al layer is 1.8 mu m, the thickness of the Ni layer is 0.5 mu m, the thickness of the Au layer is 0.8 mu m, and the process condition of deposition is that the vacuum degree is less than 2.0 × 10-6Pa, power 200W, evaporation rate no greater than 3 angstroms/second.
After deposition, an inductively coupled plasma etching system is used for realizing mesa separation, nitrogen is ultrasonically cleaned, metal outside a source window and a drain window is stripped, and then 30s ohmic contact thermal annealing is carried out in the nitrogen atmosphere at 840 ℃ to form a source electrode and a drain electrode.
And step 10, epitaxially growing a p-GaN region on the grid window.
Epitaxially growing a P-GaN layer with a thickness of 3 μm in the gate window region, with an implantation energy of 10KeV and a P-dopant implantation dose of 9.5 × 1011cm-2。
And 10, depositing a metal layer in the p-GaN area to form a grid electrode.
Depositing Ni and Au two layers of metal with the thickness of 0.3 μm and 2.4 μm respectively by an electron beam evaporation method, and forming a gate electrode after annealing.
And 11, depositing field plate metal on the surfaces of the grid and the dielectric layer.
And depositing Ti and Au on the grid to form a field plate structure with the thickness of 1 mu m.
On the surface of the formed source, drain and grid structure, the photoetching is carried out to obtain a thickened electrode pattern, the electron beam evaporation technology is adopted to thicken the electrode, and the manufacture of the device is completed.
The above embodiments are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and all such changes, modifications, substitutions, combinations, and simplifications are intended to be included in the scope of the present invention.

Claims (10)

1. The high-performance MIS gate enhanced GaN-based high electron mobility transistor comprises a silicon substrate, an AlN nucleating layer, a GaN buffer layer, an AlGaN layer and a source/drain electrode which are sequentially stacked,
the AlGaN layer consists of a p-doped drift AlGaN region, an n-doped drift AlGaN region and an AlGaN barrier layer, wherein the p-doped drift AlGaN region is positioned below the source electrode, and the n-doped drift AlGaN region is positioned below the drain electrode;
a passivation layer between the source and the drain on the AlGaN layer;
the groove extends to a certain depth in the AlGaN barrier layer along the surface of the passivation layer;
the dielectric layer is positioned on the surface of the passivation layer and extends into the groove;
a p-GaN region filling the groove;
a gate in contact with an upper surface of the p-GaN region;
a field plate in contact with the gate and the dielectric layer.
2. The hemt of claim 1, wherein said p-doped drift AlGaN region and said n-doped drift AlGaN region have Al compositions that decrease linearly from the lower surface to the upper surface of the regions, wherein the Al composition of the lower surface is 1 and the Al composition of the upper surface is 0.25.
3. The hemt of claim 1, wherein said AlGaN layer has a thickness of 2 μm, and said p-doped drift AlGaN region and said n-doped drift AlGaN region each have a width of 4 μm; the depth of the groove extending into the AlGaN barrier layer is 1 mu m, and the thickness of the p-GaN region is 3 mu m.
4. The hemt of claim 1, wherein said passivation layer is SiN.
5. The hemt of claim 1, wherein said dielectric layer is HfO2。
6. The hemt of claim 1, wherein said passivation layer has a thickness of 2 μm and said dielectric layer has a thickness of 0.5 μm.
7. The hemt of claim 1, wherein said source/drain electrodes are Ti/Al/Ni/Au ohmic contact complex metal layers and said gate electrode is a Ni/Au complex metal layer.
8. The preparation method of the high-performance MIS gate enhanced GaN-based high electron mobility transistor is characterized by comprising the following steps,
carrying out heat treatment and surface nitridation on the silicon substrate;
sequentially epitaxially growing an AlN nucleating layer, a GaN buffer layer and an AlGaN barrier layer on the surface of the nitrided silicon substrate to form an epitaxial wafer;
etching a predetermined region in the AlGaN barrier layer to form a source region, a drain region and a groove gate region;
epitaxially growing AlGaN with drifting Al components in the source region and the drain region, p-doping the AlGaN in the source region, and n-doping the AlGaN in the drain region to form a p-doped drifting AlGaN region and an n-doped drifting AlGaN region;
depositing a passivation layer;
etching the passivation layer of the groove gate region, and exposing the AlGaN barrier layer to form a gate window;
depositing a dielectric layer;
etching the dielectric layer and the passivation layer above the p-doped drift AlGaN region and the n-doped drift AlGaN region to form a source region pattern and a drain region pattern;
depositing an ohmic contact metal layer in the source region pattern and the drain region pattern to form a source electrode and a drain electrode;
epitaxially growing a p-GaN region on the gate window;
depositing a metal layer in the p-GaN area to form a grid electrode;
and depositing field plate metal on the surfaces of the grid and the dielectric layer.
9. The method of claim 8, wherein the step of depositing the dielectric layer comprises the steps of:
adopting a plasma enhanced atomic layer deposition method, firstly carrying out plasma treatment on the groove gate region by using N2 gas of 900sccm at a high temperature of 300 ℃ under 1500W power for 10 minutes, and then depositing HfO with the thickness of 0.5 mu m2A dielectric layer.
10. The production method according to claim 8 or 9, wherein the Al composition in the p-doped drift AlGaN region and the n-doped drift AlGaN region decreases linearly from the lower surface to the upper surface of the regions, the Al composition at the lower surface is 1, and the Al composition at the upper surface is 0.25.
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