CN115588616A - Method and device for manufacturing enhanced gallium nitride high electron mobility transistor - Google Patents
Method and device for manufacturing enhanced gallium nitride high electron mobility transistor Download PDFInfo
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 197
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 36
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 14
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 128
- 238000002161 passivation Methods 0.000 claims abstract description 18
- 238000009792 diffusion process Methods 0.000 claims abstract description 14
- 238000000407 epitaxy Methods 0.000 claims abstract description 10
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims description 57
- 230000004888 barrier function Effects 0.000 claims description 24
- 229910001425 magnesium ion Inorganic materials 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 238000004544 sputter deposition Methods 0.000 claims description 9
- 150000002500 ions Chemical class 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 4
- 230000000903 blocking effect Effects 0.000 claims description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 claims description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 2
- 239000010409 thin film Substances 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 claims 1
- 238000004381 surface treatment Methods 0.000 claims 1
- 230000002411 adverse Effects 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 239000007789 gas Substances 0.000 description 11
- 229910052760 oxygen Inorganic materials 0.000 description 11
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- 238000010586 diagram Methods 0.000 description 8
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 238000009616 inductively coupled plasma Methods 0.000 description 6
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- 239000000463 material Substances 0.000 description 2
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- IRPGOXJVTQTAAN-UHFFFAOYSA-N 2,2,3,3,3-pentafluoropropanal Chemical compound FC(F)(F)C(F)(F)C=O IRPGOXJVTQTAAN-UHFFFAOYSA-N 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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Abstract
A method for manufacturing an enhanced gallium nitride high electron mobility transistor and a device are provided, wherein MOCVD epitaxy is performed twice when an epitaxial structure of an enhanced device is manufactured, a GaN Cap layer is epitaxially grown on an AlGaN layer by one time, the GaN Cap layer and part of the AlGaN layer in a grid region are etched off, so that the thickness of the AlGaN layer in the grid region is smaller than that of the AlGaN layer in other regions, then a P-GaN layer is epitaxially grown again to form an epitaxial structure of the enhanced device, and a passivation layer and a drain source gate electrode are manufactured to obtain the enhanced device. The invention can eliminate the adverse effect of Mg element diffusion on the device in the P-GaN doping process in the existing P-Gate HEMT device manufacturing process, is beneficial to ensuring and improving the threshold voltage of an enhancement device, and improves the conduction performance of the device and the saturation current capability of the device.
Description
Technical Field
The invention belongs to the technical field of semiconductors, relates to an enhanced power device, and provides a method and a device for manufacturing an enhanced gallium nitride high electron mobility transistor.
Background
Gallium nitride High Electron Mobility Transistors (GaN HEMTs) have great potential in High frequency power applications as representatives of Wide Bandgap (WBG) power semiconductor devices. The Si-based GaN HEMT device is a depletion mode device due to the material characteristics, but the depletion mode device has the risk of power-off short circuit in use, so the enhancement mode power device is an urgent device in the industry.
There are three current schemes for forming an enhancement device for GaN HEMTs: a Cascode structure formed by the low-voltage enhanced Si MOS + D-Mode GaN HEMT device, a groove Gate HEMT device and a P-type Gate enhanced GaN HEMT device P-Gate HEMT device; in which the Cascode structure and the P-Gate HEMT device have been commercialized.
The Cascode structure product has high reliability and high threshold voltage and grid bias range, but because the Cascode structure product is formed by cascade packaging of two devices, the circuit parasitic parameters between the devices are large, so that the devices cannot work under high frequency, the performance of the GaN HEMT device is greatly limited, and the Si device cannot be matched with the GaN device in the aspects of use environment temperature and the like, thereby improving the requirement of the Cascode product on the work environment temperature.
The epitaxial structure of the P-Gate HEMT device is P-GaN/AlGaN/GaN/Si, and the principle is as follows: the P-GaN raises a conduction band at an AlGaN/GaN interface, so that the conduction band is raised to be above a Fermi level, and two-dimensional electron gas (2 DEG) at the AlGaN/GaN heterojunction is exhausted, thereby realizing an enhancement device. In the process of realizing a P-Gate HEMT device, in the prior art, metal organic chemical vapor deposition MOCVD is used for sequentially extending AlN/AlGaN on a Si (111) substrate: C/GaN/AlGaN/P-GaN structure, etching the P-GaN layer of the non-grid region by using etching equipment, and forming Schottky contact and ohmic contact electrodes in the grid region and the drain/source region respectively by surface passivation, windowing, metal sputtering, annealing and other processes, wherein the detailed process steps are as follows:
1. MOCVD epitaxy of AlN/AlGaN on Si (111) substrates: the structure of C/GaN/AlGaN/P-GaN is shown in FIG. 1, wherein 10 is a Si (111) substrate, 11 is AlN buffer, and 12 is AlGaN: c,13 is GaN,14 is an AlGaN barrier layer, and 15 is P-GaN;
2. etching the non-gate region P-GaN layer, as shown in FIG. 2;
3. the surface passivation is shown in fig. 3, wherein 31 is a passivation layer, and the material of the passivation layer can be one or more of SiO2, siN and Al2O 3;
4. etching the passivation layer to define a drain/source electrode region, as shown in fig. 4, and etching the drain/source electrode region on both sides of the gate compared with fig. 3;
5. sputtering the drain/source electrode region to form a drain/source electrode, as shown in fig. 5, wherein 32 is the drain/source electrode, and the electrode material thereof may be a combination of Ti, al, ni, tiN, and Au;
6. etching the passivation layer in the gate region to define a gate region, as shown in fig. 6;
7. and sputtering to form a gate electrode, as shown in fig. 7, wherein 33 is the gate electrode, and the electrode material can be a combination of several of Ti, al, ni, tiN, au and W.
The above prior art has the following problems.
1. MOCVD epitaxy of P-GaN is carried out by introducing magnesium Chloride (CP) into GaN while epitaxy 2 Mg) as a dopant, while the growth temperature of GaN is generally>At 800 ℃, mg element can diffuse into an AlGaN layer or even a GaN channel layer at the lower layer in the epitaxial process, as shown in figure 8, at different epitaxial temperatures, the depth of Mg ion downward diffusion caused by P-GaN doping and the Mg ion concentration at different depths are shown, the Mg element diffusion into the lower layer can directly cause the Mg ion to permeate into the AlGaN layer or even the GaN channel layer at high temperature to form acceptor impurities, as shown in figure 8, P-GaN (thickness 60 nm) is extended at 900 ℃, mg ion can diffuse downward at 20nm, P-GaN (thickness 60 nm) is extended at 950 ℃, mg ion can diffuse downward at 30nm, P-GaN (thickness 60 nm) is extended at 1010 ℃, and Mg ion can diffuse downward at 40nm; and it can be seen from fig. 8 that the concentration of Mg penetrating into the AlGaN barrier layer (thickness 15nm-30 nm) can exceed 1e19, even if P-GaN on the AlGaN layer is completely etched, mg penetrating into AlGaN can make AlGaN weak P-type, which partially depletes 2DEG at the AlGaN barrier/GaN channel heterojunction, resulting in reduced density and increased on-resistance; meanwhile, electrons can be trapped in the device during the use process, and the current collapse of the device can be caused. The 2DEG concentration at the AlGaN/GaN interface is reduced, the mobility is reduced, the on-resistance of the HEMT device is higher, meanwhile, the Mg element is diffused into the AlGaN barrier layer and the GaN channel layer to introduce defects, and the defects are captured under the action of electrical stressElectrons cause the dynamic resistance of the device to be increased, current collapse is caused, and the working state of the device is influenced.
2. The conventional P-Gate HEMT device directly extends AlN/AlGaN on a Si (111) substrate in the preparation process: in the preparation process of the C/GaN/AlGaN/P-GaN structure, a P-GaN layer in a non-grid region is etched to the surface of AlGaN by using devices such as ICP (inductively coupled plasma) or ALE (aluminum oxide), and the process has two problems:
the requirements on the thickness uniformity of the P-GaN layer and the AlGaN layer are high, otherwise, the situation that the AlGaN layer in a partial region is completely etched and the P-GaN layer in the partial region is not completely etched occurs, and the two situations seriously affect the on-resistance of the device;
after etching to the AlGaN surface, the AlGaN surface is damaged, a dangling bond on the AlGaN surface is opened to combine with elements such as oxygen in the air to form a high-density surface state, and the surface state can capture electrons to influence the on-resistance and the dynamic on-resistance of the device. In the prior art, a buffer oxide etching solution BOE is used for treating an oxide layer formed by combining an AlGaN surface and an oxygen element, but only the AlGaN surface oxide layer caused by P-GaN self-stop etching can be treated, oxygen ions injected into the AlGaN layer in the etching process cannot be removed, a trap can be formed, the AlGaN layer is still oxidized to form a high-density surface state after being etched in the exposed air, and Al atoms are easier to combine with oxygen in the air to form a surface state relative to Ga atoms.
3. At present, the conventional P-GaN etching mainly adopts a mode of improving the GaN/AlGaN etching selection ratio, and Cl is generally used 2 /O 2 Iso-radical containing gas or BCl 3 /SF 6 When the fluorine-based gas is contained, a passivation layer which is difficult to etch, such as aluminum oxide or aluminum fluoride, is formed on the surface of AlGaN so as to achieve the purpose of improving the etching selection ratio of GaN/AlGaN, but Cl 2 /O 2 Iso-radical containing gas or BCl 3 /SF 6 When the fluorine-based gas is etched to the surface of AlGaN, a certain injection effect is formed on AlGaN, O or F ions are injected into the AlGaN layer by 6-10nm, and the injected ionsNegative electrical centers will form in the AlGaN layer, depleting the 2DEG in the AlGaN/GaN heterojunction, adversely affecting device performance.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the existing process of the P-Gate HEMT device has the following problems:
1. mg ions are diffused to the AlGaN barrier layer and the GaN channel layer in the P-GaN layer epitaxial process, so that the performance of the device is adversely affected, and the on-resistance and the dynamic resistance are affected;
2. the thicknesses of the P-GaN layer and the AlGaN layer are not uniform, so that the P-GaN layer is not etched completely or the AlGaN layer is etched away, and the device cannot be started;
3. in order to improve the etching selection ratio of GaN/AlGaN, oxygen-containing gas or fluorine-containing gas is used when P-GaN is etched in the prior art, and O ions or F ions are injected into the AlGaN layer, which can cause the increase of the on-resistance of the device and even cause the failure of normal opening.
The technical scheme of the invention is as follows: a method for manufacturing an enhanced gallium nitride high electron mobility transistor is characterized in that MOCVD epitaxy is performed twice when an epitaxial structure of a transistor device is manufactured, alN/AlGaN is sequentially epitaxially grown on a Si substrate for the first time: C/GaN/AlGaN/GaN Cap, then etching off the GaN Cap layer and part of the AlGaN layer in the grid region to make the AlGaN layer thickness in the grid region smaller than that in other regions, then carrying out secondary epitaxy, extending a P-GaN layer on the etched GaN Cap layer to make the P-GaN layer in the non-grid region not directly contact with the AlGaN layer, the GaN Cap layer being used as a Mg ion diffusion barrier layer when the P-GaN layer is secondarily extended for blocking Mg ions from diffusing into the AlGaN barrier layer, forming an epitaxial structure of the P-Gate HEMT device after the P-GaN layer is extended, and then manufacturing a device electrode to obtain the transistor device.
Further, the invention specifically comprises the following steps:
1) And (3) extending AlN/AlGaN on the Si substrate: C/GaN/AlGaN/GaN Cap structure, the thickness of the GaN Cap layer is 10nm-100nm;
2) Etching the GaN Cap layer and part of the AlGaN layer in the gate region of the device, wherein the total thickness of the AlGaN layer is 15nm-30nm, and the thickness of the etched AlGaN layer is 5nm-10nm;
3) The P-GaN layer is extended again, wherein the thickness range of the P-GaN layer is 60nm-120nm, and the Mg doping concentration is more than 1e19;
4) Etching the P-GaN and GaN Cap layers in the non-grid region, wherein the P-GaN layer is completely etched, and the GaN Cap layer is reserved with the thickness of 2nm-20 nm;
5) Carrying out surface passivation treatment on the epitaxial wafer obtained in the step 4);
6) Defining a drain/source electrode area on the surface of the passivation layer by photoetching and ICP etching, sputtering ohmic contact metal, etching the metal to form a drain/source electrode, and performing RTA annealing to form ohmic contact;
7) And photoetching and ICP etching the surface of the passivation layer to define a gate electrode area, sputtering gate metal, and forming ohmic contact or Schottky contact to obtain the enhanced gallium nitride high electron mobility transistor.
The invention also discloses an enhanced gallium nitride high electron mobility transistor device, wherein an AlN/AlGaN: the device is manufactured according to the manufacturing method, the GaN Cap layer covers the other region of the AlGaN except the gate region, and the thickness of the AlGaN layer of the gate region is smaller than that of the AlGaN layer of the other region.
The epitaxial layer is completed by MOCVD twice, and the GaN Cap layer with the thickness of 10nm-100nm on the top layer of the primary epitaxial structure is used as a Mg ion diffusion barrier layer of a secondary epitaxial P-GaN layer and is used for blocking Mg ions from diffusing into the AlGaN barrier layer, so that the 2DEG concentration and the electron mobility at the AlGaN/GaN heterojunction can be improved. FIG. 8 shows data of diffusion of Mg ions to a lower layer when P-GaN layers are epitaxially grown at different temperatures, and it is found through research that when the thickness of the GaN Cap layer exceeds 40nm, the diffusion of Mg ions into the lower AlGaN layer can be blocked, and meanwhile, in the manufacturing method of the present invention, a portion of the GaN Cap layer, into which Mg ions are injected, will be etched away in a subsequent P-GaN etching process, and device performance will not be affected.
According to the invention, the GaN Cap layer and part of the AlGaN barrier layer under the gate region are etched after one-time epitaxy, so that the threshold voltage of the enhancement device is ensured and improved. A10 nm-100nm GaN Cap layer is designed on the primary epitaxial AlGaN barrier layer to block Mg diffusion, but the increase of the 10nm-100nm GaN Cap layer inevitably reduces the threshold voltage, so the GaN Cap layer under the grid is etched, and in order to further increase the threshold voltage compared with the device in the prior art, the AlGaN under the GaN Cap layer in the grid region is also etched; the AlGaN/GaN HEMT device generates high-density 2DEG at the AlGaN/GaN heterojunction by means of polarization effect to conduct the device, when the thickness of the AlGaN barrier layer is reduced while other parameters are unchanged, the conduction band at the heterojunction is lifted more, the 2DEG concentration is reduced more, and then the threshold voltage is increased.
The method provided by the invention has the advantages that the P-GaN layer and the GaN Cap layer are etched in a mode of not containing O or F-based gas, and meanwhile, the 2nm-20nm GaN Cap layer is reserved, so that the AlGaN layer is prevented from being exposed to air to form a high-density surface state on the surface of the AlGaN layer, and the conduction performance of a device is reduced; in addition, the AlGaN barrier layer is prevented from being implanted by etching ions, and the formation of 2DEG in a negative electricity center depletion channel in the AlGaN barrier layer is avoided. In the manufacturing method, the P-GaN layer of the non-grid region is not directly contacted with the AlGaN layer, and the 10-100nm GaN Cap layer is arranged below the P-GaN layer, so that the P-GaN layer can be completely etched into the GaN Cap layer when being etched, and the phenomenon that the P-GaN layer cannot be opened because the P-GaN layer is not completely etched or the AlGaN layer is etched is avoided. According to the invention, a P-GaN self-stop etching mode is not used, etching does not contain oxygen, etching can be stopped on the GaN Cap layer through time control, the GaN Cap layer is kept at 2-20nm, the etching damage surface of the GaN Cap layer is far away from 2DEG, and the influence on the on-resistance and the dynamic on-resistance of a device is small.
Based on the three beneficial effects, the manufacturing method can ensure that the enhanced device has stable quality in the manufacturing process, and can effectively improve the conduction performance of the P-Gate HEMT device:
according to the invention, a 10-100nm GaN Cap layer is added on the AlGaN barrier layer, so that the problems that in the preparation process of the conventional enhanced GaN high-electron-mobility transistor process, the resistance of an epitaxial wafer after the surface P-GaN layer is removed is high, the conductor resistance of a device is high relative to a D-Mode device with the same epitaxial structure and the same size, and the current collapse is caused by the diffusion of Mg ions in the operation process of the device, which are caused by the diffusion of Mg ions when the P-GaN layer is out of extension are solved. According to the invention, the GaN Cap layer and part of the AlGaN layer under the grid region of the primary epitaxial layer are etched, and then the P-GaN layer is subjected to secondary epitaxy, so that the threshold voltage of the device is ensured to be consistent with that of a conventional P-Gate device, even higher than that of the conventional P-Gate device. In addition, the invention uses oxygen-free or fluorine-free process gas to etch the P-GaN layer and the GaN Cap layer, and reserves the GaN Cap layer with the thickness of 2nm-20nm, thereby ensuring that the AlGaN barrier layer is not exposed in the air, so that the current collapse phenomenon of the device can not be caused by the formation of high-density surface state, and simultaneously the problems of negative electricity center or defect formed by ion implantation into the AlGaN barrier layer in the existing gas etching process can be avoided, and the injected ions can cause the increase of the on-resistance of the device and the current collapse phenomenon of the device.
In addition, the GaN Cap layer arranged in the invention protects the AlGaN layer of the barrier layer, and when the P-GaN layer is etched, the etching is stopped at the GaN Cap layer, so that the AlGaN surface is not influenced by the etching, the surface state (interface state) of the AlGaN can be reduced, the negative electricity center of the AlGaN is further reduced, the influence on the 2DEG at the AlGaN/GaN position is reduced, and the saturation current capability of the device is increased.
Drawings
Fig. 1 is a schematic view of a manufacturing process step 1 of a P-Gate HEMT device epitaxial structure in the prior art.
Fig. 2 is a schematic view of a manufacturing process step 2 of the epitaxial structure of the P-Gate HEMT device of the prior art.
Fig. 3 is a schematic view of the manufacturing process step 3 of the epitaxial structure of the P-Gate HEMT device of the prior art.
Fig. 4 is a schematic view of the manufacturing process step 4 of the epitaxial structure of the P-Gate HEMT device of the prior art.
Fig. 5 is a schematic view of the manufacturing process step 5 of the epitaxial structure of the P-Gate HEMT device of the prior art.
Fig. 6 is a schematic view of the manufacturing process step 6 of the epitaxial structure of the P-Gate HEMT device of the prior art.
Fig. 7 is a schematic view of the prior art P-Gate HEMT device epitaxial structure fabrication process step 7.
FIG. 8 is a graph of the diffusion depth of Mg element in the epitaxial process of the epitaxial structure of the prior art P-Gate HEMT device.
FIG. 9 shows the epitaxial growth of AlN/AlGaN on a Si substrate in an embodiment of the transistor fabrication method of the present invention: the basic structure of C/GaN/AlGaN/GaN Cap is a schematic diagram of step 1.
Fig. 10 is a schematic diagram of step 2 of the device manufacturing method of the present invention.
Fig. 11 is a schematic diagram of step 3 of the device manufacturing method of the present invention.
Fig. 12 is a schematic diagram of step 4 of the device manufacturing method of the present invention.
Fig. 13 is a schematic diagram of step 5 of the device manufacturing method of the present invention.
Fig. 14 is a schematic diagram of the photolithographic definition of drain/source electrode regions in step 6 of the device manufacturing method of the present invention.
Fig. 15 is a schematic view of the formation of drain/source electrodes in step 6 of the device manufacturing method of the present invention.
Fig. 16 is a schematic diagram of photolithographically defining a gate region in step 7 of an embodiment of a method of fabricating a device in accordance with the present invention.
Fig. 17 is a schematic diagram illustrating the formation of gate metal in step 7 of the device manufacturing method according to the present invention.
The reference numbers in the figures are: 10-Si (111) substrate, 11-AlN buffer,12-AlGaN: c,13-GaN,14-AlGaN barrier layer, 15-P-GaN,16-GaN Cap layer, 31-passivation layer, 32-drain/source electrode and 33-gate electrode.
Detailed Description
The invention discloses a method for manufacturing an enhanced gallium nitride high electron mobility transistor and a device, which are prepared by a third-generation semiconductor GaN and design a P-GaN/GaN/AlGaN/GaN structure so as to eliminate the adverse effect of Mg element diffusion on the device in the P-GaN doping process.
The production method of the present invention is described below.
1) The invention uses MOCVD to extend AlN/AlGaN on a Si (111) substrate: the thickness of the last GaN Cap layer is about 10nm to 100nm, so as to prevent the Mg ions from diffusing downwards when the P-GaN layer is extended for the second time, as shown in fig. 9.
2) And etching the GaN Cap layer and part of the AlGaN barrier layer in the device gate region by using a photoetching and etching mode, wherein the GaN Cap layer is completely etched, the total thickness of the AlGaN layer is 15-30 nm, the thickness of the part of the AlGaN barrier layer is about 5-10 nm, the thickness range of the remained AlGaN layer is 5-25 nm, and the etching equipment is a high-precision low-damage ICP etching machine or ALE equipment, as shown in figure 10.
3) And a secondary epitaxial P-GaN layer, wherein the thickness of the P-GaN layer ranges from about 60nm to 120nm, the Mg doping concentration is larger than 1e19, the Mg ion diffusion is blocked by the GaN Cap layer and can not enter the lower AlGaN barrier layer, as shown in FIG. 11.
4) And photoetching to expose a non-grid region, etching the P-GaN and GaN Cap layers of the non-grid region by utilizing a high-precision low-damage etching machine ICP or ALE equipment, wherein the P-GaN layer is completely etched, the GaN Cap layer has 2-20nm of residue, the residual GaN Cap layer has the function of protecting the AlGaN surface from being etched on the P-GaN layer to enable damage to form a surface state, etching ions are ensured not to be injected into the AlGaN layer, so that no ion is injected to form a negative electricity center, the etching surface is far away from 2DEG, and the surface state has small influence on the 2DEG, as shown in figure 12. In the prior art, in the conventional manufacturing process of a P-Gate HEMT device, the P-GaN etching technology adopts self-stop etching, namely P-GaN is etched to the surface of AlGaN by gas containing O or F, when compounds with high bond energy such as AlGaO or AlGaF and the like are formed, namely etching is blocked, etching self-stop is realized, but etching stop depends on the chemical reaction of the surface of AlGaN, the etching can damage the surface of AlGaN, the chemical bond of the surface of the damaged AlGaN is opened, and Al atoms are easily combined with oxygen to form a high-density surface state. According to the invention, the non-grid region is preferably exposed by photoetching, then the P-GaN layer is etched by using a dry etching mode, because of the existence of the GaN Cap layer, O or F containing gas is not used when the P-GaN layer is etched, the etching process can be stopped in the added GaN Cap layer by time control, the etching integrity of the P-GaN layer is ensured, the AlGaN layer is not influenced, and the problems that the P-GaN layer is not completely etched or the AlGaN layer is etched are avoided.
5) And performing surface passivation treatment on the epitaxial wafer obtained in the step 4), wherein the passivation layer of the GaN layer has various existing processes. Surface N plasma treatment of the epitaxial wafer, for example by ALD, activates the GaN dangling bonds while depositing Al 2 O 3 A thin film having a thickness of about 2nm to 10nm; the process can also use PECVD or LPCVD for surface treatmentA SiN film is deposited to passivate the GaN surface as shown in fig. 13.
6) The drain/source electrode regions are defined lithographically, as shown in fig. 14. Sputtering ohmic contact metal, the electrode material of which can be a combination of Ti, al, ni, tiN and Au, etching the metal to form a drain/source electrode, and RTA annealing to form ohmic contact, as shown in FIG. 15.
7) And photoetching to define the gate region and etching the passivation layer, as shown in FIG. 16. Sputtering gate metal, the electrode material of which can be a combination of Ti, al, ni, tiN, au, W, forming ohmic or schottky contacts as shown in fig. 17, to this point an enhanced device infrastructure is completed.
By the method, the influence of Mg ions on the AlGaN layer when P-GaN is etched is eliminated, and meanwhile, the GaN Cap layer can protect the AlGaN layer when the P-GaN layer in the non-grid region is etched to the surface of the AlGaN, so that the process hidden danger of incapability of starting a device can be avoided. Under the manufacturing method of the invention, a corresponding enhanced gallium nitride high electron mobility transistor device is obtained, and an Si substrate is provided with AlN/AlGaN: the C/GaN/AlGaN/GaN Cap/P-GaN structure and the device electrode are manufactured according to the manufacturing method, and the enhancement device has excellent conduction performance and long service life because the process hidden trouble is eliminated.
Claims (5)
1. A method for manufacturing an enhanced gallium nitride high electron mobility transistor is characterized in that MOCVD epitaxy is carried out twice when an epitaxial structure of an enhanced device is manufactured, alN/AlGaN is sequentially epitaxially grown on a Si substrate for the first time: C/GaN/AlGaN/GaN Cap, then etching off the GaN Cap layer and part of the AlGaN layer in the grid region to make the AlGaN layer thickness in the grid region smaller than that in other regions, then carrying out secondary epitaxy, extending a P-GaN layer on the etched GaN Cap layer to make the P-GaN layer in the non-grid region not directly contact with the AlGaN layer, the GaN Cap layer being used as a Mg ion diffusion barrier layer when the P-GaN layer is secondarily extended for blocking Mg ions from diffusing into the AlGaN barrier layer, forming an epitaxial structure of the P-Gate HEMT device after the P-GaN layer is extended, and then manufacturing a device electrode to obtain the enhanced device.
2. The method as claimed in claim 1, further comprising the steps of:
1) And (3) extending AlN/AlGaN on the Si substrate: C/GaN/AlGaN/GaN Cap structure, the thickness of the GaN Cap layer is 10nm-100nm;
2) Etching the GaN Cap layer and part of the AlGaN layer in the gate region of the device, wherein the total thickness of the AlGaN layer is 15nm-30nm, and the thickness of the etched AlGaN layer is 5nm-10nm;
3) The P-GaN layer is extended again, wherein the thickness range of the P-GaN layer is 60nm-120nm, and the Mg doping concentration is more than 1e19;
4) Etching the P-GaN and the GaN Cap layer in the non-grid region, wherein the P-GaN layer is completely etched, and the GaN Cap layer is kept at the thickness of 2nm-20 nm;
5) Carrying out surface passivation treatment on the epitaxial wafer obtained in the step 4);
6) Defining a drain/source electrode area on the surface of the passivation layer by photoetching and ICP etching, sputtering ohmic contact metal, etching the metal to form a drain/source electrode, and performing RTA annealing to form ohmic contact;
7) And photoetching and ICP etching the surface of the passivation layer to define a gate electrode area, sputtering gate metal, and forming ohmic contact or Schottky contact to obtain the enhanced gallium nitride high electron mobility transistor.
3. The method for manufacturing an enhanced gallium nitride high electron mobility transistor according to claim 2, wherein in step 4), the non-gate region is exposed by photolithography, then an ICP etcher or ALE equipment is used to etch the P-GaN and GaN Cap layers in the non-gate region, the etching depth is controlled by time, so that the P-GaN layer is stopped after etching, the remaining GaN Cap layer protects the AlGaN surface from being damaged by etching to form a surface state, and etching ions are prevented from being implanted into the AlGaN layer.
4. The method as claimed in claim 2, wherein the step 5) of passivating comprises: surface N of epitaxial wafer by ALDPlasma treatment to activate GaN dangling bonds while depositing Al 2 O 3 A thin film with a thickness of 2nm-10nm; or PECVD or LPCVD is used for surface treatment and SiN film is deposited simultaneously to passivate the GaN surface.
5. An enhancement mode gallium nitride HEMT device, characterized in that an Si substrate has AlN/AlGaN: a C/GaN/AlGaN/GaN Cap/P-GaN structure and an electrode, the device being manufactured according to the manufacturing method of any one of claims 1 to 4, wherein the GaN Cap layer covers the AlGaN except for the gate region, and the AlGaN layer in the gate region has a smaller thickness than the AlGaN layer in the other region.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008027027A2 (en) * | 2005-09-07 | 2008-03-06 | Cree, Inc | Transistor with fluorine treatment |
| US20150097194A1 (en) * | 2012-04-17 | 2015-04-09 | Enkris Semiconductor, Inc. | Enhanced device and manufacturing method therefor |
| CN110034186A (en) * | 2018-01-12 | 2019-07-19 | 中国科学院苏州纳米技术与纳米仿生研究所 | The enhanced HEMT of group III-nitride and preparation method thereof based on composite potential barrier layer structure |
| US20200135478A1 (en) * | 2018-10-31 | 2020-04-30 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor arrangement and method of manufacture |
| US20200185508A1 (en) * | 2018-12-07 | 2020-06-11 | Gan Systems Inc. | GaN HEMT DEVICE STRUCTURE AND METHOD OF FABRICATION |
| CN111682064A (en) * | 2020-06-02 | 2020-09-18 | 华南师范大学 | High-performance MIS gate enhanced GaN-based high electron mobility transistor and preparation method thereof |
| US10854777B1 (en) * | 2014-12-23 | 2020-12-01 | Soraa Laser Diode, Inc. | Manufacturable thin film gallium and nitrogen containing semiconductor devices |
| CN113658862A (en) * | 2021-07-05 | 2021-11-16 | 西安电子科技大学广州研究院 | Preparation method of p-GaN gate enhanced HEMTs device with stable threshold voltage |
| CN113838931A (en) * | 2021-08-23 | 2021-12-24 | 华灿光电（浙江）有限公司 | High electron mobility transistor chip and preparation method thereof |
| CN114496789A (en) * | 2021-12-24 | 2022-05-13 | 西安电子科技大学芜湖研究院 | Preparation method of enhancement type transistor and enhancement type transistor |
-
2022
- 2022-12-12 CN CN202211589003.4A patent/CN115588616B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008027027A2 (en) * | 2005-09-07 | 2008-03-06 | Cree, Inc | Transistor with fluorine treatment |
| US20150097194A1 (en) * | 2012-04-17 | 2015-04-09 | Enkris Semiconductor, Inc. | Enhanced device and manufacturing method therefor |
| US10854777B1 (en) * | 2014-12-23 | 2020-12-01 | Soraa Laser Diode, Inc. | Manufacturable thin film gallium and nitrogen containing semiconductor devices |
| CN110034186A (en) * | 2018-01-12 | 2019-07-19 | 中国科学院苏州纳米技术与纳米仿生研究所 | The enhanced HEMT of group III-nitride and preparation method thereof based on composite potential barrier layer structure |
| US20200135478A1 (en) * | 2018-10-31 | 2020-04-30 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor arrangement and method of manufacture |
| US20200185508A1 (en) * | 2018-12-07 | 2020-06-11 | Gan Systems Inc. | GaN HEMT DEVICE STRUCTURE AND METHOD OF FABRICATION |
| CN111682064A (en) * | 2020-06-02 | 2020-09-18 | 华南师范大学 | High-performance MIS gate enhanced GaN-based high electron mobility transistor and preparation method thereof |
| CN113658862A (en) * | 2021-07-05 | 2021-11-16 | 西安电子科技大学广州研究院 | Preparation method of p-GaN gate enhanced HEMTs device with stable threshold voltage |
| CN113838931A (en) * | 2021-08-23 | 2021-12-24 | 华灿光电（浙江）有限公司 | High electron mobility transistor chip and preparation method thereof |
| CN114496789A (en) * | 2021-12-24 | 2022-05-13 | 西安电子科技大学芜湖研究院 | Preparation method of enhancement type transistor and enhancement type transistor |
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