CN114496789A - Preparation method of enhancement type transistor and enhancement type transistor - Google Patents
Preparation method of enhancement type transistor and enhancement type transistor Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
Abstract
The invention discloses a preparation method of an enhancement type transistor and the enhancement type transistor, wherein the preparation method comprises the following steps: providing a heterojunction comprising a first semiconductor layer and a second semiconductor layer; the second semiconductor layer is formed on the first semiconductor layer, and two-dimensional electron gas is formed in the heterojunction; the second semiconductor layer comprises a first barrier layer, an insertion layer and a second barrier layer, wherein the thermal decomposition temperature of the insertion layer is lower than that of the second barrier layer; performing dry etching on the second semiconductor layer to form a first groove extending into the insertion layer; carrying out thermal decomposition etching on the first groove to form a second groove; epitaxially growing a P-type doping layer in the second groove; preparing a source electrode, a drain electrode and a grid electrode; the source electrode and the drain electrode are grown in the second semiconductor layer, the grid electrode is located between the source electrode and the drain electrode, and the grid electrode is grown on the P-type doped layer. By performing the method of the present invention, the fabrication of high performance enhanced transistor devices can be achieved.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a preparation method of an enhancement type transistor and the enhancement type transistor.
Background
Power electronics are the core elements of power electronics systems. With the rapid development of power electronic technology, the limitations of the traditional silicon materials and the second-generation semiconductor materials are increasingly prominent, and the power electronic devices based on these materials cannot meet the urgent requirements of power systems in terms of high frequency, low loss, high power capacity and the like. Third generation wide bandgap semiconductor materials represented by GaN and SiC have the characteristics of large bandgap, high critical breakdown field, and extremely strong radiation resistance, and thus show excellent advantages in power electronic devices. The wide-bandgap semiconductor material GaN has the characteristics of large forbidden bandwidth, high saturated electron drift velocity, large critical breakdown electric field, stable chemical property and the like. Unlike SiC materials, GaN can be used to fabricate devices using GaN bulk materials, and can also be used to fabricate high performance devices using the unique heterojunction structure of GaN. The two-dimensional electron gas (2DEG) surface density in the AlGaN/GaN heterojunction structure is about 1013cm-2Mobility higher than 1500cm2And v.s, the GaN device has low on-resistance and high working frequency, and can meet the requirements of a next generation power electronic system on higher power, higher frequency, smaller volume and worse high-temperature operation of a power device.
Due to the polarization characteristic of materials, even if no gate voltage is applied, the conventional AlGaN/GaN HEMT has high-concentration 2DEG in a channel, so that the device is in a normally-on state, namely a depletion mode device. To achieve the turn-off function, a negative gate voltage must be applied. In the power switch, the switch is required to be in a normally-off state from the viewpoints of safety, energy saving and the like, so that a great deal of work is devoted to realizing the enhanced GaN-based HEMT device.
Disclosure of Invention
Therefore, the present invention is directed to a method for manufacturing an enhancement transistor and an enhancement transistor, so as to overcome the shortcomings of the prior art.
To this end, according to a first aspect, the present invention provides a method of manufacturing an enhancement transistor, comprising the steps of:
providing a heterojunction comprising a first semiconductor layer and a second semiconductor layer; the second semiconductor layer is formed on the first semiconductor layer and has a band gap wider than that of the first semiconductor layer, and a two-dimensional electron gas is formed in the heterojunction; the second semiconductor layer comprises a first barrier layer, an insertion layer and a second barrier layer, wherein the thermal decomposition temperature of the insertion layer is lower than that of the second barrier layer;
performing dry etching on the second semiconductor layer to form a first groove extending into the insertion layer;
carrying out thermal decomposition etching on the first groove to form a second groove; the thermal decomposition etching stops when reaching the second barrier layer;
epitaxially growing a P-type doping layer in the second groove; the P-type doping layer is used for exhausting the two-dimensional electron gas distributed in the area under the gate;
preparing a source electrode, a drain electrode and a grid electrode; the source electrode and the drain electrode are grown in the second semiconductor layer, the grid electrode is located between the source electrode and the drain electrode, and the grid electrode is grown on the P-type doped layer.
Further, a P-type doped layer is grown in the second groove and on the first barrier layer; before the step of preparing the source electrode, the drain electrode and the gate electrode, the method further comprises the following steps:
setting a mask layer on the P-type doping layer, and thermally oxidizing the P-type doping layer exposed from the mask layer to form a high-resistance layer; the mask layer covers the growth regions of the gate, the source and the drain.
Further, the step of performing thermal decomposition etching on the first groove to form a second groove includes:
carrying out thermal decomposition etching on the first groove in a chemical vapor deposition reaction chamber under a decomposition atmosphere to form a second groove; at the moment, the temperature in the chemical vapor deposition reaction chamber is a first temperature;
the step of epitaxially growing a P-type doped layer in the second groove comprises the following steps:
closing the decomposition atmosphere, adjusting the temperature in the chemical vapor deposition reaction chamber to a second temperature, and epitaxially growing a P-type doped layer in the second groove and on the first barrier layer; the second temperature is higher than the first temperature.
Further, the step of preparing the source electrode, the drain electrode and the gate electrode comprises:
etching the growth regions of the source electrode and the drain electrode respectively to form a source groove and a drain groove; the source groove and the drain groove extend into the first barrier layer, or extend into the insertion layer or extend into the second barrier layer;
growing a source electrode and a drain electrode in the source groove and the drain groove respectively;
and growing a grid on the P-type doped layer.
Further, the step of growing a gate on the P-type doped layer includes:
carrying out low-power plasma oxidation treatment on the P-type doped layer to form an oxide layer; the thickness of the oxide layer is nano-scale;
and growing a grid on the oxide layer.
Further, the P-type doped layer is a P-GaN layer.
According to a second aspect, the invention also provides an enhancement mode transistor device comprising:
a heterojunction including a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer having a band gap wider than that of the first semiconductor layer, the heterojunction having a two-dimensional electron gas formed therein; the second semiconductor layer comprises a first barrier layer, an insertion layer and a second barrier layer, wherein the thermal decomposition temperature of the insertion layer is lower than that of the second barrier layer;
the P-type doping layer is grown in the first barrier layer and the insertion layer and extends to the second barrier layer;
and the grid electrode is positioned between the source electrode and the drain electrode, and is grown on the P-type doped layer.
Furthermore, the P-type doped layer extends to the first barrier layer, and gaps between the P-type doped layer and the source electrode and gaps between the P-type doped layer and the drain electrode are filled with the high-resistance layer.
Further, the enhancement mode transistor device further includes:
the oxide layer is formed on the P-type doped layer, and the thickness of the oxide layer is in a nanometer level; the grid is formed on the oxide layer.
The technical scheme provided by the invention has the following advantages:
1. according to the preparation method of the enhancement transistor, the second semiconductor layer (namely the barrier layer) is arranged to comprise the first barrier layer, the insertion layer and the second barrier layer, and the thermal decomposition temperature of the insertion layer is set to be lower than that of the second barrier layer, so that the subsequent thermal decomposition etching can have the effect of self-stopping after reaching the second barrier layer; when a groove for growing a P-type doped region (P-type doped layer) under a gate is prepared to form an enhancement transistor, the groove is etched to the insertion layer by adopting a dry etching mode, then the thermal decomposition selection ratio between the insertion layer and the second barrier layer is utilized, the thermal decomposition etching is adopted until the surface of the second barrier layer is self-terminated, namely the groove is etched by adopting the dry etching mode and the self-termination thermal etching mode, so that the problems of over-etching and interface etching damage caused by single dry etching are solved, the problem of interface oxygen introduced by wet etching is also solved, the electron mobility of a device prepared by the method is improved, and the preparation of the enhancement transistor with excellent performance is realized.
2. According to the preparation method of the enhancement type transistor, provided by the invention, thermal decomposition etching and epitaxial growth of the P type doping layer are carried out in the chemical vapor deposition reaction chamber, so that the epitaxial growth of the P type doping layer can be carried out after the thermal decomposition etching is finished and the temperature is raised for a small span and the thermal decomposition atmosphere is closed, and the epitaxial growth of the P type doping layer is not required to be carried out after the temperature is raised and lowered independently, so that the connection smoothness in the preparation process steps is improved, and the preparation time and the preparation cost are saved.
3. According to the preparation method of the enhancement type transistor, the mask layer covering the growth area of the grid electrode is arranged, the P-type doping layer exposed from the mask layer is thermally oxidized to form the high-resistance layer, the release of two-dimensional electron gas is realized, and the saturation current of the device prepared by the method can be improved; in addition, the high-resistance layer can also play a role in protecting the whole device, so that the method can improve the interface state of the prepared device, inhibit current collapse and improve the performance of the device.
4. According to the preparation method of the enhancement transistor, the low-power plasma oxidation treatment is carried out on the P-type doping layer, so that the oxidation layer with the nanometer-level thickness is formed on the surface layer of the P-type doping layer, the barrier height between the grid and the P-type doping layer is increased while the internal P-type doping layer is not influenced, the threshold voltage of the device prepared by the method can be increased, the grid leakage can be improved, and the device performance can be improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart illustrating a method for manufacturing an enhancement mode transistor according to an embodiment of the present invention;
fig. 2 is a diagram of a structure of a device obtained after step S101 in fig. 1 is executed;
fig. 3 is a diagram of a structure of a device obtained after step S102 in fig. 1 is executed;
fig. 4 is a diagram of a structure of a device obtained after step S103 in fig. 1 is performed;
fig. 5 is a diagram of a structure of a device obtained after the steps S101 to S105 in fig. 1 are performed;
FIG. 6 is a schematic view illustrating another growth of a P-type doped layer according to an embodiment of the present invention;
fig. 7 is a schematic view illustrating a mask layer according to an embodiment of the present invention;
fig. 8 is a diagram of a structure of a device obtained after the steps S101 to S106 in fig. 1 are performed;
FIG. 9 is a flowchart illustrating another process of fabricating an enhancement transistor according to an embodiment of the present invention;
fig. 10 is a diagram illustrating a device structure of an enhancement transistor having an oxide layer according to an embodiment of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "upper", "lower", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and operate, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Example 1
The embodiment provides a preparation method of an enhancement transistor, as shown in fig. 1, the method includes the following steps:
s101: a heterojunction is provided that includes a first semiconductor layer and a second semiconductor layer.
In the present application, as shown in fig. 2, the second semiconductor layer is formed on the first semiconductor layer and has a band gap wider than that of the first semiconductor layer, a two-dimensional electron gas is formed in the heterojunction, and the second semiconductor layer includes a first barrier layer, an insertion layer, and a second barrier layer, and a thermal decomposition temperature of the insertion layer is lower than that of the second barrier layer. Here, the fact that the thermal decomposition temperature of the insertion layer is lower than the thermal decomposition temperature of the second barrier layer means that the second barrier layer does not thermally decompose when the insertion layer starts to thermally decompose at the temperature a, and the thermal decomposition temperature of the second barrier layer is higher than the temperature a, that is, a certain thermal decomposition selectivity ratio exists therebetween.
In this application, the first semiconductor layer and the second semiconductor layer are both group III compound layers, for example, the first semiconductor layer may be a GaN layer, the first barrier layer in the second semiconductor layer may be both AlGaN layers (the content of Al in the two layers may be the same or different), and the insertion layer may be a GaN layer.
In the present application, as shown in fig. 2, the heterojunction may be prepared on a substrate, and specifically, the substrate may be any one of a silicon substrate, a sapphire substrate, a silicon carbide substrate, or the like.
In the present application, before the heterojunction is fabricated on the substrate, as shown in fig. 2, a buffer layer may also be grown on the substrate, specifically, the buffer layer may also be a group III compound layer, such as any one or a combination of AlN, AlGaN, and GaN.
In the present application, a space control layer (which is illustrated in fig. 2 by way of example) may be further disposed between the first semiconductor layer and the second semiconductor layer, specifically between the first semiconductor layer and the lower barrier layer, and specifically, the space control layer may be an AlN layer.
In this application, the heterojunction may also be an existing heterojunction, on which a heterojunction with other structures such as a cap layer (shown in fig. 2 by taking the case that the heterojunction further has a cap layer thereon as an example) is already prepared, and the cap layer is etched in the dry etching process of the following step S102 without affecting the preparation of the final enhancement transistor.
S102: and performing dry etching on the second semiconductor layer to form a first groove extending into the insertion layer.
The device prepared by this step is shown in fig. 3.
In this application, the first groove only needs to extend into the insertion layer, and the depth extending into the insertion layer is not limited, for example, when the thickness of the insertion layer is 30nm, the thickness of the insertion layer subjected to dry etching may be any one of 1nm to 20 nm.
In the present application, ICP dry etching may be specifically adopted, and accordingly, the etching gas may be Cl2And BCl3The RF power and the ICP power may be 1 to 50w and 1 to 200w, respectively.
S103: and carrying out thermal decomposition etching on the first groove to form a second groove.
In the present application, as shown in fig. 4, the thermal decomposition etching is self-stopped when it reaches the second barrier layer. Specifically, when the insertion layer is a GaN layer and the second barrier layer is an AlGaN layer, the thermal decomposition etching is performed at 700 to 1000 ℃ in a nitrogen atmosphere (i.e., the lower barrier layer in the present application is not thermally decomposed at 700 to 1000 ℃).
In the application, after the thermal decomposition is finished, further processing can be performed by using a BOE solution or a TMAH solution, so that the surface of the finally formed second groove is smoother.
S104: and epitaxially growing a P-type doped layer in the second groove.
In the application, the P-type doped layer is used for exhausting the two-dimensional electron gas distributed in the area under the gate, so that the preparation of the enhancement device is realized. Specifically, the P-type doped layer may be a P-GaN layer or a P-AlGaN layer.
In the present application, the P-type doped layer may be grown only in the second groove, or may be grown on the second groove and the first barrier layer. Specifically, when the P-type doped layer is grown only in the second groove, the P-type doped layer may be grown after masking other regions (the upper surface of the first barrier layer), or the P-type doped layer filling the second groove and covering the first barrier layer may be grown (the P-type doped layer grown in the second groove and on the first barrier layer is in an intermediate state, and the P-type doped layer is still grown only in the second groove in the final state), and then the other regions are etched or subjected to processes such as thermal oxidation to form a high-resistance layer (see step S106 described below); correspondingly, when the P-type doped layer is grown in the second groove and on the first barrier layer (where the P-type doped layer grown in the second groove and on the first barrier layer is in a final state), the P-type doped layer can be obtained by directly growing.
S105: preparing a source electrode, a drain electrode and a grid electrode; the source electrode and the drain electrode are grown in the second semiconductor layer, the grid electrode is located between the source electrode and the drain electrode, and the grid electrode is grown on the P-type doped layer.
The device prepared through this step is shown in fig. 5.
In the present application, in order to realize that both the source and the drain are grown in the second semiconductor layer, the following steps may be performed:
step A: etching the growth regions of the source electrode and the drain electrode respectively to form a source groove and a drain groove; the source and drain trenches extend into the first barrier layer or into the intervening layer or into the second barrier layer.
And B: and growing a source electrode and a drain electrode in the source groove and the drain groove respectively.
In the application, the ohmic metal of the source electrode and the drain electrode can be Ti/Al/Ni/Au four-layer ohmic metal, and the metal of the grid electrode can be Ni/Au two-layer metal. Of course, this is only a specific example, and the metal of the source, the drain and the gate may be other cases.
In the present application, the P-type doped layer in step S104 may be grown only in the second recess (i.e., only in the growth region of the gate), or may be grown in the second recess and on the first barrier layer as shown in fig. 6, and in this case, before performing step S105, a step may be performed:
s106: setting a mask layer on the P-type doping layer, and thermally oxidizing the P-type doping layer exposed from the mask layer to form a high-resistance layer; the mask layer covers the growth regions of the gate, the source and the drain.
Here, the mask layer covers the growth region of the gate, so that the enhancement device is prepared by still having a P-type doped layer under the gate, and meanwhile, the two-dimensional electron gas is released by the high-resistance layer, so that the saturation current of the device prepared by the method is improved; in addition, the high-resistance layer can also play a role in protecting the whole device, so that the method can improve the interface state of the prepared device, inhibit current collapse and improve the performance of the device. Here, the mask layer may be SiO2The atmosphere gas of thermal oxidation can be one of oxygen or ozone, and the oxidation temperature can be 700-1000 ℃.
In addition, since the source and the drain in the present application are grown in the second semiconductor layer, the growth regions of the source and the drain need to be etched, and since the etching difficulty of the high resistance layer is high, as shown in fig. 7, the mask layer here can also cover the source, the drain and the growth regions, so that when the growth regions of the source and the drain are etched, the P-type doped layer and the second semiconductor layer with low etching difficulty are etched, thereby reducing the implementation difficulty of the method in the present application.
Correspondingly, if the P-type doped layer is grown in the second groove and on the first barrier layer in step S104, that is, the method includes step S106, when the gate is prepared in step S105, the mask layer on the P-type doped layer needs to be removed first, and specifically, the mask layer may be removed by using a BOE solution.
At this time, the structure of the device finally prepared is as shown in fig. 8.
According to the preparation method of the enhancement transistor, the second semiconductor layer (namely the barrier layer) comprises the first barrier layer, the insertion layer and the second barrier layer, and the thermal decomposition temperature of the insertion layer is set to be lower than that of the second barrier layer, so that the subsequent thermal decomposition etching can have the effect of self-stopping after reaching the second barrier layer; when a groove for growing a P-type doped region under a gate is prepared to form an enhancement transistor, the groove is etched to the insertion layer by adopting a dry etching mode, then the thermal decomposition selection ratio between the insertion layer and the second barrier layer is utilized, the thermal decomposition etching is adopted until the surface of the second barrier layer is self-terminated, namely the groove is etched by adopting a dry etching mode and a self-termination thermal etching mode, so that the problems of over-etching and interface etching damage caused by single dry etching are solved, the problem of interface oxygen introduced by wet etching is also solved, the electron mobility of a device prepared by the method is improved, and the preparation of the enhancement transistor with excellent performance is realized.
As an alternative implementation, when the P-type doped layer grown in step S104 is to fill the second groove and cover the first barrier layer (whether in an intermediate state or in a final state), the thermal decomposition etching and the epitaxial growth of the P-type doped layer may be performed in a cvd reactor, and as shown in fig. 9, the method for manufacturing the enhancement mode transistor includes the following steps:
s901: a heterojunction is provided that includes a first semiconductor layer and a second semiconductor layer. And the second semiconductor layer is formed on the first semiconductor layer and has a band gap wider than that of the first semiconductor layer, two-dimensional electron gas is formed in the heterojunction, and the second semiconductor layer includes a first barrier layer, an insertion layer and a second barrier layer, and the thermal decomposition temperature of the insertion layer is lower than that of the second barrier layer.
S902: and performing dry etching on the second semiconductor layer to form a first groove extending into the insertion layer.
S903: carrying out thermal decomposition etching on the first groove in a chemical vapor deposition reaction chamber under a decomposition atmosphere to form a second groove; at this time, the temperature in the chemical vapor deposition reaction chamber is the first temperature.
In this application, the thermal decomposition atmosphere can be nitrogen, and first temperature is 700 ~ 1000 ℃.
S904: closing the decomposition atmosphere, adjusting the temperature in the chemical vapor deposition reaction chamber to a second temperature, and epitaxially growing a P-type doped layer in the second groove and on the first barrier layer; the second temperature is higher than the first temperature.
Here, if the finally obtained P-type doped layer is only located in the second groove, the P-type doped layer outside the second groove region may be further subjected to etching or thermal oxidation to form a high resistance layer, and the like, which is not described herein again.
In this application, the second temperature is 700 ~ 1100 ℃, that is to say, the second temperature is actually only a little higher than first temperature.
S905: preparing a source electrode, a drain electrode and a grid electrode; the source electrode and the drain electrode are grown in the second semiconductor layer, the grid electrode is located between the source electrode and the drain electrode, and the grid electrode is grown on the P-type doped layer.
In this application, specific contents of steps S901 to S905 can be understood by referring to contents of steps S101 to S106, which are not described herein again.
According to the preparation method of the enhancement type transistor, thermal decomposition etching and epitaxial growth of the P type doping layer are carried out in the chemical vapor deposition reaction chamber, so that the epitaxial growth of the P type doping layer can be carried out after the thermal decomposition etching is finished and the temperature rise of a small span and the thermal decomposition atmosphere is closed, the epitaxial growth of the P type doping layer is not required to be carried out after the temperature rise and the temperature fall independently, the connection smoothness in the preparation process steps is improved, and the preparation time and the preparation cost are saved.
In addition, as another specific embodiment, before the gate is grown on the P-type doped layer in step S105 or step S905, as shown in fig. 10, a low-power plasma oxidation treatment may be performed on the P-type doped layer to form an oxide layer; the thickness of the oxide layer is nano-scale; then, a gate is grown on the oxide layer. Therefore, the barrier height between the grid and the P-type doping layer is increased while the internal P-type doping layer is not influenced, the threshold voltage of the device prepared by the method can be improved, the grid leakage can be improved, and the device performance can be improved.
Example 2
This embodiment provides an enhancement mode transistor prepared by the method of preparing the enhancement mode transistor of embodiment 1, specifically, as shown in fig. 5, the device includes a heterojunction, a P-type doped layer, a source, a drain and a gate.
The heterojunction comprises a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer has a band gap wider than that of the first semiconductor layer, and two-dimensional electron gas is formed in the heterojunction; the second semiconductor layer includes a first barrier layer, an insertion layer, and a second barrier layer, the insertion layer having a thermal decomposition temperature lower than that of the second barrier layer.
The P-type doped layer is grown in the first barrier layer and the insertion layer and extends to the second barrier layer.
And the grid electrode is positioned between the source electrode and the drain electrode, and is grown on the P-type doped layer.
As an alternative embodiment, as shown in fig. 8, the P-type doped layer may extend onto the first barrier layer, and the gaps between the P-type doped layer and the source and drain are filled with high resistance layers.
As an alternative embodiment, as shown in fig. 10, the enhancement transistor may further include: the oxide layer is formed on the P-type doped layer, and the thickness of the oxide layer is in a nanometer level; the grid is formed on the oxide layer.
The specific content of the device structure in this embodiment can be understood by referring to the preparation method in embodiment 1, which is not described herein again.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications derived therefrom are intended to be within the scope of the present invention.
Claims (9)
1. A preparation method of an enhancement transistor is characterized by comprising the following steps:
providing a heterojunction comprising a first semiconductor layer and a second semiconductor layer; the second semiconductor layer is formed on the first semiconductor layer and has a band gap wider than that of the first semiconductor layer, and a two-dimensional electron gas is formed in the heterojunction; the second semiconductor layer comprises a first barrier layer, an insertion layer and a second barrier layer, wherein the thermal decomposition temperature of the insertion layer is lower than that of the second barrier layer;
performing dry etching on the second semiconductor layer to form a first groove extending into the insertion layer;
carrying out thermal decomposition etching on the first groove to form a second groove; the thermal decomposition etching stops when reaching the second barrier layer;
epitaxially growing a P-type doping layer in the second groove; the P-type doping layer is used for depleting the two-dimensional electron gas distributed in the area under the gate;
preparing a source electrode, a drain electrode and a grid electrode; the source electrode and the drain electrode are both grown in the second semiconductor layer, the grid electrode is located between the source electrode and the drain electrode, and the grid electrode is grown on the P-type doping layer.
2. The method of claim 1, wherein the P-type doped layer is grown in the second trench and on the first barrier layer; before the step of preparing the source electrode, the drain electrode and the grid electrode, the method further comprises the following steps:
setting a mask layer on the P-type doping layer, and thermally oxidizing the P-type doping layer exposed from the mask layer to form a high-resistance layer; the mask layer covers the growth regions of the grid electrode, the source electrode and the drain electrode.
3. The method for manufacturing an enhancement transistor according to claim 2, wherein the step of performing thermal decomposition etching on the first recess to form a second recess comprises:
carrying out thermal decomposition etching on the first groove in a chemical vapor deposition reaction chamber under a decomposition atmosphere to form a second groove; at the moment, the temperature in the chemical vapor deposition reaction chamber is a first temperature;
the step of epitaxially growing a P-type doped layer in the second groove comprises:
closing the decomposition atmosphere, adjusting the temperature in the chemical vapor deposition reaction chamber to a second temperature, and epitaxially growing the P-type doping layer in the second groove and on the first barrier layer; the second temperature is higher than the first temperature.
4. The method of claim 1, wherein the step of forming the source, drain and gate comprises:
respectively etching the growth regions of the source electrode and the drain electrode to form a source groove and a drain groove; the source trench and the drain trench extend into the first barrier layer or into the insertion layer or into the second barrier layer;
growing the source electrode and the drain electrode in the source groove and the drain groove respectively;
and growing the grid on the P-type doped layer.
5. The method of claim 4, wherein the step of growing the gate on the P-doped layer comprises:
carrying out low-power plasma oxidation treatment on the P-type doped layer to form an oxide layer; the thickness of the oxide layer is nano-scale;
and growing the grid on the oxide layer.
6. The method of manufacturing an enhancement mode transistor according to any one of claims 1 to 5, wherein the P-type doped layer is a P-GaN layer.
7. An enhancement-mode transistor, comprising:
a heterojunction including a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer having a band gap wider than that of the first semiconductor layer, the heterojunction having a two-dimensional electron gas formed therein; the second semiconductor layer comprises a first barrier layer, an insertion layer and a second barrier layer, wherein the thermal decomposition temperature of the insertion layer is lower than that of the second barrier layer;
a P-type doped layer grown in the first barrier layer and the insertion layer and extending to the second barrier layer;
the source electrode and the drain electrode are grown in the second semiconductor layer, the grid electrode is located between the source electrode and the drain electrode, and the grid electrode is grown on the P-type doped layer.
8. The enhancement-mode transistor according to claim 7, wherein the P-doped layer extends onto the first barrier layer, and wherein gaps between the P-doped layer and the source and the drain are filled with a high resistance layer.
9. The enhancement mode transistor according to claim 7 or 8, further comprising:
the oxide layer is formed on the P-type doped layer, and the thickness of the oxide layer is in a nanometer level; the gate is formed on the oxide layer.
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| CN114759080A (en) * | 2022-06-13 | 2022-07-15 | 深圳市时代速信科技有限公司 | Semiconductor device and preparation method thereof |
| CN115588616A (en) * | 2022-12-12 | 2023-01-10 | 江苏长晶科技股份有限公司 | Method and device for manufacturing enhanced gallium nitride high electron mobility transistor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114759080A (en) * | 2022-06-13 | 2022-07-15 | 深圳市时代速信科技有限公司 | Semiconductor device and preparation method thereof |
| CN115588616A (en) * | 2022-12-12 | 2023-01-10 | 江苏长晶科技股份有限公司 | Method and device for manufacturing enhanced gallium nitride high electron mobility transistor |
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