CN110875382A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN110875382A
CN110875382A CN201810997623.9A CN201810997623A CN110875382A CN 110875382 A CN110875382 A CN 110875382A CN 201810997623 A CN201810997623 A CN 201810997623A CN 110875382 A CN110875382 A CN 110875382A
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layer
gate
semiconductor layer
semiconductor
grid
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吴星星
裴轶
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Gpower Semiconductor Inc
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Gpower Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductors. The bottom of the grid structure is located in the first semiconductor layer, and the grid structure can better exhaust two-dimensional electron gas in the first semiconductor layer through the relative position relation with the two-dimensional electron gas layer in the first semiconductor layer, so that the control capability of the grid structure on the two-dimensional electron gas is enhanced, and the working stability of the device is improved. The gate semiconductor layer grown again in the gate trench may reduce the interface state density between the first semiconductor layer and the gate semiconductor layer at the location of the gate trench. Interface state density between other structures formed on the grid semiconductor layer and the grid semiconductor layer is low, threshold voltage drift phenomenon can be reduced, grid electric leakage is reduced, dynamic characteristics, breakdown voltage and power performance of the device are improved, and current collapse effect is reduced.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
Most of the research is only directed to depletion type GaN HEMT (High Electron Mobility Transistor) devices because a large amount of charges generated by spontaneous polarization and piezoelectric polarization exist at the AlGaN or GaN heterojunction interface to generate High-concentration two-dimensional Electron gas (2DEG) so that the GaN HEMT device threshold voltage is negative, and in the AlGaN/GaN HEMT, the High-concentration 2DEG generated by spontaneous polarization and piezoelectric polarization causes the threshold voltage to be around-4V. The device can only be turned off when the channel 2DEG at the AlGaN/GaN heterojunction interface is in a depleted state when the GaN HEMT gate metal is biased negatively enough. Conventional depletion mode GaN HEMTs complicate circuit structures in rf microwave and high voltage applications because of the negative turn-on voltage used. In particular, in high voltage switching applications, fail safe requires that the switching device be in an off state without applying a gate voltage. Therefore, it is necessary to design and manufacture enhancement type gan hemts devices, that is, the threshold voltage of the devices becomes positive, and in practical application, the devices can be operated or pinched off only by applying a positive bias voltage. The circuit design of eliminating negative bias voltage simplifies the circuit and reduces the complexity of the circuit design and the cost of preparation.
The method for realizing the enhancement-type GaN HEMT is based on the GaAs process, and the change of the threshold voltage is regulated and controlled by notching the gate metal and thinning the thickness of the barrier layer. At present, researchers and manufacturers at home and abroad mostly adopt a dry etching method to form a groove under gate metal, but the threshold voltage of the GaN HEMT formed by the method is low, about 0-1V, the gate metal has large leakage and the dynamic range of gate voltage is small. However, GaN HEMTs are always limited by the high density of interface states between the dielectric layer and the barrier layer, which cause the threshold voltage to drift and degrade the high frequency characteristics of the device. Therefore, how to realize an enhancement-type GaN HEMT device with stable threshold voltage and well reduced leakage current becomes an urgent problem to be solved in the field.
Disclosure of Invention
The present invention provides a semiconductor device and a method for manufacturing the same.
The technical scheme provided by the invention is as follows:
a semiconductor device, comprising:
a substrate;
a first semiconductor layer formed on one side of the substrate;
a source electrode, a drain electrode and a grid electrode structure which is manufactured on one side, far away from the substrate, of the first semiconductor layer, wherein the grid electrode structure is filled with a grid groove, and the bottom of the grid electrode structure is positioned in the first semiconductor layer; the first semiconductor layer comprises a first channel layer and a first barrier layer which is manufactured on one side of the first channel layer, which is far away from the substrate, and a first two-dimensional electron gas layer is formed at the interface of the first channel layer and the first barrier layer; the grid structure sequentially comprises a grid semiconductor layer and a grid metal layer in the direction away from the substrate from the first semiconductor layer.
Further, a distance between a bottom of the gate structure and the first two-dimensional electron gas layer is less than or equal to 9 nm.
Furthermore, the distance between the surface, far away from the substrate, of the grid semiconductor layer covered in the grid groove and the first two-dimensional electronic gas layer is less than or equal to 35 nm.
Further, the gate structure further includes: and the first dielectric layer is manufactured between the grid semiconductor layer and the grid metal layer.
Further, the gate semiconductor layer comprises a gate channel layer and a gate barrier layer, a second two-dimensional electron gas layer is formed at the interface of the gate channel layer and the gate barrier layer, and the surface of one side, close to the substrate, of the gate channel layer at least extends into the first channel layer.
Further, the thickness of the gate barrier layer is less than the thickness of the first barrier layer.
Further, the first barrier layer comprises at least two sub-barrier layers, and the aluminum component content of each sub-barrier layer is different.
Further, the semiconductor device also comprises an etching stop layer positioned on one side of the first channel layer far away from the substrate, and the etching rate of the etching stop layer material is lower than that of the first barrier layer.
Further, the thickness of the etching stop layer is smaller than or equal to 10nm, and the bottom of the gate groove is located in the etching stop layer.
Further, the semiconductor device further comprises a second dielectric layer grown on the side, far away from the substrate, of the first barrier layer.
Further, at least a portion of the sidewalls of the gate structure is arc-shaped.
The present invention also provides a method for manufacturing a semiconductor device, comprising:
providing a substrate;
manufacturing a first semiconductor layer on one side of the substrate;
a gate groove for accommodating a gate structure is formed in one side, away from the substrate, of the first semiconductor layer, and the bottom of the gate groove is located in the first semiconductor layer;
in-situ secondary growth of a grid semiconductor layer in the grid groove;
manufacturing a grid electrode metal layer on one side, far away from the first semiconductor layer, of the grid electrode semiconductor layer, wherein the grid electrode semiconductor layer and the grid electrode metal layer form the grid electrode structure;
and manufacturing a source electrode and a drain electrode on one side of the first semiconductor layer far away from the substrate.
Further, after the step of manufacturing a gate semiconductor layer on a side of the gate trench far from the first semiconductor layer, the method further includes:
and manufacturing a first dielectric layer on one side of the grid semiconductor layer far away from the first semiconductor layer, wherein the grid metal layer is manufactured on the first dielectric layer.
In the semiconductor device provided by the embodiment of the application, the bottom of the gate structure is located in the first semiconductor layer, so that the distance between the bottom of the gate structure and the first two-dimensional electron gas layer in the first semiconductor layer is shortened, the gate structure can better exhaust the first two-dimensional electron gas in the first semiconductor layer, the control capability of the gate structure on the first two-dimensional electron gas is enhanced, and the working stability of the device is improved. Meanwhile, when the gate groove is formed, the first barrier layer can be inevitably damaged, so that the first semiconductor layer has certain defects. In addition, the gate semiconductor layer re-grown in the gate trench may reduce the interface state density between the first semiconductor layer and the gate semiconductor layer at the location of the gate trench. Interface state density between other structures formed on the grid semiconductor layer and the grid semiconductor layer is also lower, threshold voltage drift phenomenon of the device can be obviously reduced, grid electric leakage is reduced, dynamic characteristics, breakdown voltage and power performance of the device are improved, and current collapse effect can be reduced.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.
Fig. 2 is another schematic structural diagram of a semiconductor device according to an embodiment of the present invention.
Fig. 3 is another schematic structural diagram of a semiconductor device according to an embodiment of the present invention.
Fig. 4 is another schematic structural diagram of a semiconductor device according to an embodiment of the present invention.
Fig. 5 is a schematic view of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Icon: 10-a semiconductor device; 101-a substrate; 102-a first semiconductor layer; 121 — a first channel layer; 122 — a first barrier layer; 1221-first sub-barrier layer; 1222-a second sub-barrier layer; 123-a first two-dimensional electron gas layer; 103-a gate structure; 131-a gate semiconductor layer; 132-a gate metal layer; 133-a first dielectric layer; 134-gate trenches; 104-source; 105-a drain electrode; 106-etching stop layer; 107-second dielectric layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present invention, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
The embodiment of the present application further provides a semiconductor device 10, as shown in fig. 1, including a substrate 101, a first semiconductor layer 102, a gate structure 103, a source 104, and a drain 105.
The material of the substrate 101 may be determined according to actual needs. The material of the substrate 101 may be sapphire, silicon nitride, gallium nitride, silicon or other materials suitable for growing gallium nitride, and the embodiment of the present application does not limit the specific material form of the substrate 101.
The first semiconductor layer 102 is fabricated on the substrate 101 side, wherein the first semiconductor layer 102 may include a first channel layer 121 and a first barrier layer 122 fabricated on a side of the channel layer away from the substrate 101, and a first two-dimensional electron gas layer 123 is formed at an interface of the first channel layer 121 and the first barrier layer 122. Optionally, the first barrier layer 122 is an aluminum gallium nitride layer or an aluminum indium gallium nitride layer, and the first channel layer 121 is gallium nitride. The gate trench 134 may be formed on the first semiconductor layer 102 by masking, etching, and the like.
The gate structure 103 may include a gate semiconductor layer 131 and a gate metal layer 132. When the gate structure 103 is fabricated, the gate trench 134 may be formed in the first semiconductor layer 102, and then the gate trench 134 may be filled with the gate structure 103. The gate semiconductor layer 131 may cover the gate groove 134 or may cover the gate groove 134 and at least a portion of the surface of the first semiconductor layer 102. In order to deplete the two-dimensional electron gas below the gate structure 103 as much as possible, the distance L1 between the bottom of the gate structure 103 and the first two-dimensional electron gas layer 123 may be less than or equal to 9 nm. The inventor finds that if the distance between the bottom of the gate structure 103 and the first two-dimensional electron gas layer 123 is greater than 9nm, it is difficult to deplete the two-dimensional electron gas under the gate structure 103, and the difficulty in controlling the two-dimensional electron gas by the gate structure 103 is also increased, so that the turn-off sensitivity of the device is reduced. The gate groove 134 may be a groove with a rectangular, U-shaped, V-shaped or trapezoidal cross section.
When an enhancement device is formed conventionally, since the problems of increased on-resistance, large leakage current and the like are caused by etching damage in the process of forming the gate trench 134 by etching, before the gate structure 103 is covered on the gate trench 134, a second growth may be performed in an MOCVD (metal organic chemical vapor deposition) apparatus to form the gate semiconductor layer 131 in the gate trench 134, and the gate semiconductor layer 131 completely covers the gate trench 134. The gate semiconductor layer 131 is grown secondarily in the MOCVD equipment, and partial etching damage and defects can be repaired in a high-temperature growth environment, so that the electron mobility and the threshold voltage stability are improved, the distance between the bottom of the gate structure 103 and the first two-dimensional electron gas layer 123 is smaller than or equal to 4nm, and the two-dimensional electron gas below the gate groove 134 is further depleted on the basis that the good electron mobility and the good threshold voltage can be guaranteed. The material of the gate semiconductor layer 131 after the secondary growth may be aluminum gallium nitride, indium gallium nitride, n-type gallium nitride, p-type gallium nitride, or other III-V compounds. Polarization charges can also be introduced into the gate semiconductor layer 131 secondarily grown in the gate trench 134 to further deplete the two-dimensional electron gas and increase the threshold voltage of the device. Preferably, on the basis of ensuring that the gate metal layer 132 has a strong control capability on the two-dimensional electron gas, the two-dimensional electron gas below the trench is further exhausted by using polarization charge consumption, and the distance from the upper surface of the secondarily-grown gate semiconductor layer 131 covering the gate trench 134 to the first two-dimensional electron gas layer 123 is set to be less than or equal to 35 nm.
Further, as shown in fig. 2, the semiconductor device 10 further includes a first dielectric layer 133, the first dielectric layer 133 is formed on a side of the gate semiconductor layer 131 away from the first barrier layer 122, the first dielectric layer 133 is located between the gate semiconductor layer 131 and the gate metal layer 132, the first dielectric layer 133 covers at least a portion of the surface of the gate semiconductor layer 131, and the gate metal layer 132 is formed on a side of the first dielectric layer 133 away from the gate semiconductor layer 131. The first dielectric layer 133 may be SiN or SiO2、SiON、Al2O3、HfO2、HfAlOxOr a combination thereof. In order to further improve the threshold voltage, reduce the gate leakage and increase the swing of the gate voltage, after the twice-grown gate semiconductor layer 131 is grown, the first dielectric layer 133 is grown in situ by using the same preparation method, and because the interface state density between the twice-grown gate semiconductor layer 131 and the in-situ grown first dielectric layer 133 is low, the threshold voltage drift phenomenon of the device can be significantly reduced, the gate leakage is reduced and the dynamic characteristics of the device are improved. The threshold voltage of the device is in a linear relationship with the thickness of the first dielectric layer 133 below the gate metal layer 132, and in order to ensure the controllability of the gate metal layer 132 on the two-dimensional electron gas and to enable the small deviation value of the threshold voltage to be within the acceptable range of the device operation, the thickness of the first dielectric layer 133 may be 5-40 nm.
A source 104 and a drain 105 are formed on a side of the first semiconductor layer 102 away from the substrate 101. The gate metal layer 132 is formed in the gate trench 134, wherein the distance between the bottom of the gate metal layer 132 and the first two-dimensional electron gas layer 123 is less than or equal to 75nm, so that the two-dimensional electron gas under the groove can be controlled. The source electrode 104 and the drain electrode 105 may be a single layer of metal or a stack of multiple layers of metal, and one or a combination of titanium, aluminum, nickel, or gold may be used. The gate metal layer 132 may be a single layer of metal or a stack of multiple layers of metal. The material of the gate metal layer 132 may be one or a combination of Ni, W, Ti, Pd, Au, and Al. Optionally, a distance between the gate metal layer 132 and the source 104 is smaller than a distance between the gate metal layer 132 and the drain 105.
In one embodiment, as shown in fig. 3, the semiconductor device 10 further includes an etch stop layer 106 formed on a side of the first channel layer 121 away from the substrate 101. The material of the etch stop layer 106 is etched at a lower rate than the first barrier layer 122 such that the gate trench 134 extends through the first barrier layer 122 and the trench bottom stops within the etch stop layer 106. By controlling the thickness of the etching stop layer 106, the distance between the bottom of the gate trench 134 and the first two-dimensional electron gas layer 123 can be controlled more accurately. At this time, the thickness of the etching stop layer 106 is set to be less than or equal to 10nm, and the distance between the bottom surface of the gate structure 103 close to the substrate 101 and the upper surface of the first channel layer 121 far from the substrate 101 may be less than or equal to 5 nm.
Optionally, the material of the etch stop layer 106 is an aluminum-containing material, such as an aluminum nitride material, and the material of the etch stop layer 106 and the material of the first barrier layer 122 are different, or the aluminum composition content of both is different. Preferably, when the aluminum composition content of etch stop layer 106 is higher than the aluminum composition content of first barrier layer 122, the stopping of the trench bottom inside etch stop layer 106 can be controlled more precisely.
In one embodiment, the gate semiconductor layer 131 may have a multi-layer structure including a gate channel layer and a gate barrier layer. A second two-dimensional electron gas layer is formed at the interface of the gate channel layer and the gate barrier layer, and the surface of the gate channel layer on the side close to the substrate 101 at this time extends at least into the first channel layer 121. Optionally, the thickness of the gate barrier layer is smaller than the thickness of the first barrier layer 122, and when the thickness of the gate barrier layer is smaller than or equal to half of the thickness of the first barrier layer 122, the concentration of the two-dimensional electron gas in the area below the gate structure 103 can be better reduced. Optionally, a distance between the upper surface of the gate semiconductor layer 131 and the first two-dimensional electron gas layer 123 is less than or equal to 35 nm. In order to avoid the problem of the increase in on-resistance caused by the gate channel layer formed on the first barrier layer 122, the gate barrier layer may be made of one or a combination of AlGaN and AlInN, or the same material as the first barrier layer 122.
In one embodiment, at least a portion of the sidewall of the T-shaped gate trench is an arc-shaped surface, and the surface of the gate structure 103 contacting the arc-shaped surface matches the arc-shaped surface. The arcuate surface may be located at a corner of the gate trench 134 on a side away from the substrate 101. By such a gate slot structure with an arc-shaped surface, when the voltage of the drain electrode 105 is increased, the corresponding potential gradient of the arc-shaped surface becomes more gentle, the electric field intensity at the bottom of the gate slot 134 near the edge of the drain electrode 105 is reduced, which is actually equivalent to enlarging the area of a depletion region, so as to increase the electric field intensity of the area below the whole gate structure 103. And the arc-shaped surface can increase the bonding force between the first dielectric layer 133 and the gate metal layer 132, so that the gate metal layer 132 is not easy to fall off, and the reliability of the device is improved.
The side of the gate slot 134 may also be formed of two parts, one part being an arc-shaped surface and the other part being a flat surface, the arc-shaped surface not extending to the bottom of the gate slot 134. The shape of the face of the gate structure 103 in contact with the gate trench 134 may include a portion of an arc face and a portion of a flat face.
In another embodiment, referring again to fig. 4, the first barrier layer 122 comprises a plurality of sub-barrier layers, at least two sub-barrier layers, such as a first sub-barrier layer 1221 and a second sub-barrier layer 1222, wherein the first sub-barrier layer 1221 is formed on a side of the first channel layer 121 away from the substrate 101, the second sub-barrier layer 1222 is formed on a side of the first sub-barrier layer 1221 away from the first channel layer 121, the second sub-barrier layer 1222 has a thickness smaller than that of the first sub-barrier layer 1221, and a bottom of the gate trench 134 extends at least to an interface where the second sub-barrier layer 1222 is close to the first sub-barrier layer 1221.
The first sub-barrier layer 1221 and the second sub-barrier layer 1222 have different aluminum composition contents. By providing the first barrier layer 122 as a multi-layer structure with different al content of each sub-barrier layer, the al content decreases in a direction away from the substrate 101, during the etching process for etching the gate trench 134, the bottom of the gate trench 134 may stop in the sub-barrier layer on the side close to the channel layer 121, such as the first sub-barrier layer 1221 in fig. 4. The first two-dimensional electron layer 123 under the etched gate trench 134 can be depleted to different degrees by adjusting the thicknesses of different sub-barrier layers in the first barrier layer 122. The thickness of the first sub-barrier layer 1221 close to the first channel layer 121 is made smaller than the thickness of the second sub-barrier layer 1222 far from the first channel layer 121, and preferably, the thickness of the sub-barrier layer located at the side close to the first channel layer 121 and in direct contact with the first channel layer 121 is less than or equal to 8nm, so as to achieve the purpose of adjusting the threshold voltage of the enhancement mode high electron mobility transistor.
In one embodiment, as shown in fig. 4, semiconductor device 10 further includes a second dielectric layer 107 grown on a side of first barrier layer 122 remote from substrate 101. The second dielectric layer 107 may be an insulating material, and may be made of silicon nitride, aluminum oxide, silicon dioxide, or hafnium oxide, and the leakage current of the gate may be reduced by providing the second dielectric layer 107.
To sum up, in the semiconductor device 10 provided in the embodiment of the present application, the bottom of the gate structure 103 is located in the first semiconductor layer 102, so that the distance between the bottom of the gate structure 103 and the first two-dimensional electron gas layer 123 in the first semiconductor layer 102 is shortened, the first two-dimensional electron gas layer 123 below the gate in the first semiconductor layer 102 can be better exhausted by the gate structure 103, the control capability of the gate on the first two-dimensional electron gas layer 123 is enhanced, and the working stability of the device is improved. Meanwhile, when the gate trench 134 is formed, the first barrier layer 122 may be inevitably damaged, so that the first semiconductor layer 102 may have certain defects. In addition, the gate semiconductor layer 131 re-grown in the gate groove may reduce the interface state density between the first semiconductor layer 102 and the gate semiconductor layer 131 at the location of the gate groove 134. Interface state density between other structures formed on the gate semiconductor layer 131 and the gate semiconductor layer 131 is also low, so that threshold voltage drift of the device can be reduced remarkably, gate leakage can be reduced, dynamic characteristics, breakdown voltage and power performance of the device can be improved, and current collapse effect can be reduced.
The embodiment of the present application also provides a method for manufacturing the semiconductor device 10, as shown in fig. 5, including the following steps S101 to S106.
In step S101, a substrate 101 is provided.
Step S102 is to fabricate a first semiconductor layer 102 on one side of the substrate 101.
After the preparation of the substrate 101 is completed, the substrate 101 may be placed into a growth chamber, and the first semiconductor layer 102 is formed on one side of the substrate 101 by using a metal organic chemical vapor deposition method. It is understood that the first semiconductor layer 102 may be fabricated to include the first channel layer 121 and the first barrier layer 122, and furthermore, a nucleation layer and a buffer layer may be prepared between the substrate 101 and the first channel layer 121.
The material of the first semiconductor layer 102 may be a III-V compound. It is understood that the nucleation layer is located on the substrate 101 side, the buffer layer is located on the side of the nucleation layer away from the substrate 101, the first channel layer 121 is located on the side of the buffer layer away from the nucleation layer, and the first barrier layer 122 is located on the side of the first channel layer 121 away from the buffer layer. The first channel layer 121 and the first barrier layer 122 may form a heterojunction structure, and the first two-dimensional electron gas layer 123 is formed at an interface of the first channel layer 121 and the first barrier layer 122. The material of the first barrier layer 122 may be any semiconductor material capable of forming a heterojunction structure with the first channel layer 121, including gallium-based compound semiconductor materials or group III nitride semiconductor materials, such as InxAlyGazN1-x-y-z, where x is 0. ltoreq. 1, y is 0. ltoreq. 1, and z is 0. ltoreq. 1.
In step S103, a gate trench 134 for accommodating the gate structure 103 is formed in a side of the first semiconductor layer 102 away from the substrate 101, and a bottom of the gate trench 134 is located in the first semiconductor layer 102.
In the substep S131, a mask layer is formed on the side of the first barrier layer 122 away from the first channel layer 121.
After the first semiconductor layer 102 is prepared on the substrate 101 in the growth chamber, the substrate 101 with the first semiconductor layer 102 prepared may not be taken out of the growth chamber. Instead, the same preparation method as that for preparing the first semiconductor layer 102 is continuously adopted in the growth chamber, and the mask layer is continuously prepared on the side of the first barrier layer 122 away from the first channel layer 121, and the material of the mask layer may be silicon nitride or other nitrides.
In the substep S132, a mask window corresponding to the etching gate trench 134 is formed on the mask layer.
After the preparation of the mask layer is completed, the substrate 101 prepared with the first semiconductor layer 102 and the mask layer may be moved out of the growth chamber. And removing part of the mask layer corresponding to the gate groove 134 on the mask layer by adopting a photoetching process to form a mask window.
In the substep S133, the first barrier layer 122 is etched based on the mask layer, so that the portion of the first semiconductor layer 102 corresponding to the mask window is removed, and the gate trench 134 is formed, wherein the mask layer may form a step surface with the first semiconductor layer 102.
When the first semiconductor layer 102 is etched, hydrogen, chlorine or ammonia gas may be used to etch the mask window in the MOCVD growth chamber in the MOCVD growth system, and the bottom of the gate trench 134 is located in the first semiconductor layer 102. It is to be understood that the gate semiconductor layer 131 may cover not only the gate trench 134 but also a portion of the first barrier layer 122 in order to be subsequently prepared. The length of the opening of the gate trench 134 within the mask window may be smaller than the length of the mask window, so that a stepped surface is formed between the mask layer and the first barrier layer 122. The gate trench 134 is used for accommodating the gate structure 103, and the gate trench 134 may be a groove with a U-shaped, V-shaped, or rectangular cross section. Meanwhile, in order to enable the first two-dimensional electron gas layer 123 under the gate structure 103 to be better depleted, the distance between the bottom of the gate structure 103 and the first two-dimensional electron gas layer 123 may be less than or equal to 9 nm. Accordingly, the distance between the bottom of the gate trench 134 and the first two-dimensional electron gas layer 123 is less than or equal to 9 nm.
Step S104, growing a gate semiconductor layer 131 in situ in the gate trench 134 on a side far from the first semiconductor layer 102.
Step S105, a gate metal layer 132 is formed on a side of the gate semiconductor layer 131 away from the first semiconductor layer 102, and the gate semiconductor layer 131 and the gate metal layer 132 form the gate structure 103.
In detail, after the preparation of the gate trench 134 is completed, the gate semiconductor layer 131 may be prepared by continuing the in-situ secondary growth in the growth pre-chamber without removing the mask layer. The material of the gate semiconductor layer 131 may be aluminum gallium nitride, indium gallium nitride, N-type gallium nitride, P-type gallium nitride, or other III-V group compounds. The distance from the upper surface of the gate semiconductor layer 131 covering the gate trench 134 to the first two-dimensional electron gas layer 123 is 35nm or less.
Optionally, the thickness of the gate semiconductor layer 131 may be smaller than the depth of the gate groove 134, so that after the bottom and the sidewall of the gate groove 134 are covered by the gate semiconductor layer 131, the gate groove 134 may still form a groove shape, thereby facilitating the preparation of other structures.
The first semiconductor layer 102 can be inevitably damaged to a certain degree in the manufacturing process, and the thickness of the gate channel layer can be larger than or equal to 6nm, so that a certain distance is reserved between the second two-dimensional electron gas layer and the first semiconductor layer 102, the distance enables the second two-dimensional electron gas layer to be away from the etching damage, and the problem of large leakage current of the device can be effectively solved.
Optionally, in order to avoid the problem of the increase of the on-resistance caused by the gate channel layer prepared on the first barrier layer 122, the gate barrier layer may be made of one or a combination of AlGaN and AlInN. Or the gate barrier layer may be the same material as the first barrier layer 122.
After the in-situ secondary growth of the gate semiconductor layer 131 is completed, the first dielectric layer 133 continues to be grown in situ in the growth chamber by using a metal organic chemical vapor deposition method, and then the gate metal layer 132 is prepared, and the metal material used for preparing the gate metal layer 132 can adopt P-type doping or doping in other forms. By controlling the depth of the trench of the gate trench 134 and the thickness of the gate semiconductor layer 131, the distance between the bottom of the gate metal layer 132 prepared in the gate trench 134 and the first two-dimensional electron gas layer 123 can be controlled within 75nm, so that the performance of the semiconductor device 10 in the application of enhancement devices in the embodiment of the present application can be further improved, and the control capability of the gate structure 103 on the first two-dimensional electron gas layer 123 can be enhanced.
In step S106, a source 104 and a drain 105 are formed on a side of the first semiconductor layer 102 away from the substrate 101.
After the gate metal layer 132 is formed, the mask layer may be removed to expose the surface of the first barrier layer 122, and the source electrode 104 and the drain electrode 105 may be formed on the surface of the first barrier layer 122. Optionally, the mask layer may be removed by a dry etching process. It is understood that the step of preparing the gate structure 103 may be performed before the step of preparing the source electrode 104 and the drain electrode 105, or may be performed simultaneously with the source electrode 104, the gate metal layer 132 and the drain electrode 105, and the order of preparing the source electrode 104, the drain electrode 105 and the gate metal layer 132 is not limited in the embodiments of the present application.
In one embodiment, the method further comprises: before the first barrier layer 122 is fabricated, an etch stop layer 106 is fabricated on a side of the channel layer remote from the substrate 101. A second dielectric layer 107 may be further formed on a side of the first semiconductor layer 102 away from the substrate 101, where the second dielectric layer 107 covers at least a portion of the surface of the first semiconductor layer 102 between the source 104 and the gate structure 103 and between the gate structure 103 and the drain 105.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (13)

1. A semiconductor device, comprising:
a substrate;
a first semiconductor layer formed on one side of the substrate;
a source electrode, a drain electrode and a grid electrode structure which is manufactured on one side, far away from the substrate, of the first semiconductor layer, wherein the grid electrode structure is filled with a grid groove, and the bottom of the grid electrode structure is positioned in the first semiconductor layer; the first semiconductor layer comprises a first channel layer and a first barrier layer which is manufactured on one side of the first channel layer, which is far away from the substrate, and a first two-dimensional electron gas layer is formed at the interface of the first channel layer and the first barrier layer; the grid structure sequentially comprises a grid semiconductor layer and a grid metal layer in the direction away from the substrate from the first semiconductor layer.
2. The semiconductor device of claim 1, wherein a distance between a bottom of the gate structure and the first two-dimensional electron gas layer is less than or equal to 9 nm.
3. The semiconductor device according to claim 1, wherein a distance from a surface of the gate semiconductor layer covering the gate trench in a direction away from the substrate to the first two-dimensional electron gas layer is 35nm or less.
4. The semiconductor device of claim 1, wherein the gate structure further comprises:
and the first dielectric layer is manufactured between the grid semiconductor layer and the grid metal layer.
5. The semiconductor device according to claim 1, wherein the gate semiconductor layer comprises a gate channel layer and a gate barrier layer, and wherein a second two-dimensional electron gas layer is formed at an interface of the gate channel layer and the gate barrier layer, and wherein a surface of the gate channel layer on a side close to the substrate extends at least into the first channel layer.
6. The semiconductor device of claim 5, wherein a thickness of the gate barrier layer is less than a thickness of the first barrier layer.
7. The semiconductor device of claim 1, wherein the first barrier layer comprises at least two sub-barrier layers, each of the sub-barrier layers having a different aluminum composition content.
8. The semiconductor device of claim 1, further comprising an etch stop layer on a side of the first channel layer remote from the substrate, wherein the etch stop layer material is etched at a lower rate than the first barrier layer.
9. The semiconductor device according to claim 8, wherein a thickness of the etch stop layer is less than or equal to 10nm, and a bottom of the gate trench is located within the etch stop layer.
10. The semiconductor device according to any one of claims 1 to 9, further comprising a second dielectric layer grown on a side of the first barrier layer remote from the substrate.
11. The semiconductor device according to any one of claims 1 to 9, wherein at least a portion of the sidewall of the gate structure is arc-shaped.
12. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
manufacturing a first semiconductor layer on one side of the substrate;
a gate groove for accommodating a gate structure is formed in one side, away from the substrate, of the first semiconductor layer, and the bottom of the gate groove is located in the first semiconductor layer;
in-situ secondary growth of a grid semiconductor layer in the grid groove;
manufacturing a grid electrode metal layer on one side, far away from the first semiconductor layer, of the grid electrode semiconductor layer, wherein the grid electrode semiconductor layer and the grid electrode metal layer form the grid electrode structure;
and manufacturing a source electrode and a drain electrode on one side of the first semiconductor layer far away from the substrate.
13. The method for manufacturing a semiconductor device according to claim 12, wherein after the step of forming a gate semiconductor layer on a side of the gate trench remote from the first semiconductor layer, the method further comprises:
and manufacturing a first dielectric layer on one side of the grid semiconductor layer far away from the first semiconductor layer, wherein the grid metal layer is manufactured on the first dielectric layer.
CN201810997623.9A 2018-08-29 2018-08-29 Semiconductor device and method for manufacturing the same Pending CN110875382A (en)

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