CN216354230U

CN216354230U - Semiconductor device and application thereof

Info

Publication number: CN216354230U
Application number: CN202122963183.5U
Authority: CN
Inventors: 林信南; 石黎梦
Original assignee: Shenzhen Jing Xiang Technologies Co ltd
Current assignee: Shenzhen Jing Xiang Technologies Co ltd
Priority date: 2020-12-01
Filing date: 2021-11-26
Publication date: 2022-04-19
Anticipated expiration: 2031-11-26
Also published as: CN113889531A; CN113990950A; WO2022116915A1; CN113990949B; CN113990949A; CN113990948A

Abstract

The invention discloses a semiconductor device and application thereof, wherein the semiconductor device comprises: a substrate; a channel layer disposed on the substrate; a barrier layer disposed on the channel layer; a drain electrode disposed on the barrier layer and in contact with the channel layer; a source electrode disposed on the barrier layer and in contact with the channel layer; a gate disposed on the barrier layer and between the source and the drain; and a passivation layer disposed on the barrier layer and between the gate and the barrier layer; and the oxide layer is arranged on the passivation layer and is positioned between the grid and the passivation layer. The semiconductor device provided by the invention can improve the stability of threshold voltage.

Description

Semiconductor device and application thereof

Technical Field

The invention belongs to the technical field of semiconductors, and particularly relates to a semiconductor device and application thereof.

Background

Gallium nitride as a wide bandgap semiconductor has the characteristics of high breakdown electric field, high electron saturation velocity and mobility, so that the gallium nitride-based power device can be used for preparing a new generation of high-power converter, and the existing gallium nitride-based power device is a transverse heterojunction AlGaN/GaN high-electron-mobility transistor device. The silicon substrate has the advantages of large size and low cost, a buffer layer is formed between the gallium nitride base and the substrate to improve the lattice mismatch and thermal expansion coefficient mismatch between the substrate and the gallium nitride base, and the buffer layer is doped with carbon to inhibit the lateral punch-through of the semiconductor device. But because the interfaces of the semiconductor layers with different materials have defects, the formed semiconductor device has higher leakage current and leakage voltage.

Disclosure of Invention

The invention aims to provide a semiconductor device and application thereof, and the semiconductor device and the application thereof can improve the stability of threshold voltage.

In order to solve the technical problems, the invention is realized by the following technical scheme:

the present invention provides a semiconductor device, which at least comprises:

a substrate;

a channel layer disposed on the substrate;

a barrier layer disposed on the channel layer;

a drain electrode disposed on the barrier layer and in contact with the channel layer;

a source electrode disposed on the barrier layer and in contact with the channel layer;

a gate disposed on the barrier layer and between the source and the drain; and

a passivation layer disposed on the barrier layer and between the gate and the barrier layer;

and the oxide layer is arranged on the passivation layer and is positioned between the grid and the passivation layer.

Optionally, the passivation layer is made of aluminum nitride.

Optionally, the oxide layer is made of aluminum oxide.

Optionally, the gate extends into the barrier layer and has a predetermined distance from the bottom of the barrier layer.

Optionally, the barrier layer is a gallium nitride layer of 3-6um and 20-30 nm.

Optionally, the barrier layer is made of Al_0.23Ga_0.77N。

Optionally, the gate includes:

a titanium metal layer;

an aluminum metal layer disposed on the titanium metal layer;

a nickel metal layer disposed on the aluminum metal layer; and

and the gold metal layer is arranged on the nickel metal layer.

Optionally, the distance between the gate and the source is 2-3 um.

Optionally, the distance between the gate and the drain is 14-15 um.

The invention also provides an electronic device comprising the semiconductor device

As described above, the passivation layer made of aluminum nitride has a high forbidden bandwidth and a high thermal conduction efficiency, and can improve the blocking capability of the gate dielectric against leakage current and the quality of the interface with gallium nitride. When the forbidden band width and the conduction band offset are large, electrons can be restrained from passing through the dielectric layer, and the grid leakage condition is reduced. And because the aluminum nitride and the gallium nitride have good lattice matching and heat conduction characteristics, the aluminum nitride in the passivation layer is in direct contact with the gallium nitride, and the interface quality can be improved. Meanwhile, the aluminum nitride layer manufactured by PEALD can reduce the interface defect between an oxide layer and gallium nitride, reduce the leakage current of the grid electrode, improve the stability and the reliability of the grid electrode and enable the semiconductor device to have lower threshold voltage hysteresis.

Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 to 6 are process diagrams of a semiconductor device.

Fig. 7 to 10 are process diagrams of manufacturing a semiconductor device having an insertion layer in a channel layer.

Fig. 11 is a schematic view of a semiconductor device structure having an insertion layer in a channel layer.

Fig. 12 to 16 are process diagrams of manufacturing a semiconductor device having a shaped gate.

Fig. 17 is a schematic view of another semiconductor device with an opposite gate.

Fig. 18 to 22 are process diagrams of manufacturing the semiconductor device with the drain surrounded by the gate.

Fig. 23 is a top view of fig. 22.

Fig. 24 is a schematic view of a semiconductor device having a gallium nitride layer under a gate.

Fig. 25 to 28 are diagrams of a manufacturing process of a semiconductor device in which a gallium nitride layer is made into a passivation layer.

Fig. 29 is a schematic view of a semiconductor device having multiple gallium nitride layers under a gate.

Fig. 30 to 36 are diagrams illustrating a manufacturing process of a semiconductor device in which a drain electrode is connected to a gallium nitride layer.

Fig. 37 is a top view of fig. 36.

Fig. 38 to 40 are process diagrams of manufacturing a semiconductor device having a metal electrode pad.

Fig. 41-43 are process diagrams of semiconductor device fabrication with air bridge embedded source field plate.

Fig. 44 is a schematic view of a semiconductor device structure having multiple passivation layers.

Fig. 45 to 58 are manufacturing process diagrams of a semiconductor device.

Fig. 59 to 63 are process diagrams of a P-type field effect transistor.

Fig. 64 is a schematic view of a monolithically integrated semiconductor device having a P-type field effect transistor.

Fig. 65-76 are schematic diagrams of monolithically integrated metal-oxide-semiconductor field effect transistors and high electron mobility transistor structures.

Fig. 77 is an equivalent circuit diagram of fig. 76.

Fig. 78 is a half-bridge circuit diagram.

Fig. 79 is an equivalent circuit diagram of a half bridge circuit without isolation trenches.

Fig. 80 is an equivalent circuit diagram of a half-bridge circuit provided with an isolation trench.

Fig. 81 to 88 are diagrams of a manufacturing process of a half bridge circuit provided with an isolation trench.

Fig. 89 is a semiconductor epitaxial structure.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1 to fig. 89, the semiconductor device or the monolithically integrated semiconductor device according to the present invention includes a substrate 100, an epitaxial structure disposed on the substrate 100, and a source 107, a drain 108 and a gate 109 disposed on the epitaxial structure. Wherein the epitaxial structure includes a heterostructure formed of gallium nitride and aluminum gallium nitride (GaN/AlGaN). And in the present application, the semiconductor device is, for example, a semiconductor power device.

Referring to fig. 1, in an embodiment of the invention, the substrate 100 may be a silicon substrate, such as silicon (Si) or silicon carbide (SiC). In other embodiments, the substrate 100 may also be sapphire (Al)₂O₃) Gallium arsenide (GaAs), lithium aluminate (LiAlO)₂) Gallium nitride (GaN), or other semiconductor substrate materials. After the substrate 100 is formed, a buffer layer 101 may be formed between the substrate 100 and the epitaxial structure by a chemical vapor deposition method or a metal organic chemical vapor deposition method to improve lattice matching between the substrate 100 and the epitaxial structure, and the material of the buffer layer 101 may be, for example, one or more of gallium nitride, aluminum gallium nitride, or aluminum nitride. In the embodiment, the buffer layer 101 is, for example, an aluminum nitride buffer layer, and the thickness of the buffer layer 101 is, for example, 1-4um, specifically, 1 um.

Referring to fig. 1 to 5, in an embodiment of the present invention, the epitaxial structure includes a channel layer 102 disposed on a buffer layer 101, and a barrier layer 103 disposed on the channel layer 102. Channel layer 102 is disposed on buffer layer 101, and for example, 3-6um gallium nitride may be grown on buffer layer 101 to form channel layer 102. In the present embodiment, the thickness of the channel layer 102 is, for example, 4 um. The barrier layer 103 is formed on the channel layer 102, the barrier layer 103 is, for example, an aluminum gallium nitride layer, and the material of the barrier layer 103 is, for example, Al_0.23Ga_0.77And N is added. And the thickness of the barrier layer 103 is, for example, 20 to 30nm, specifically, 25nm, for example. In this embodiment, a gate opening 1041 is further disposed on the barrier layer 103 for depositing the gate 109. In this embodiment, the channel layer 102 and the barrier layer 103 may be prepared by a chemical vapor deposition method or a metal organic chemical vapor deposition method.

Referring to fig. 1 to 3, in an embodiment of the invention, a gate dielectric layer may be further disposed in the semiconductor device to reduce the threshold voltage hysteresis. Specifically, in the present embodiment, the gate dielectric layerIncluding a passivation layer 105 and an oxide layer 106 disposed on the barrier layer 103, and the passivation layer 105 is, for example, an aluminum nitride layer disposed on the barrier layer 103. In the present embodiment, the passivation layer 105 is deposited by Plasma Enhanced Atomic Layer Deposition (PEALD). The oxide layer 106 is, for example, an aluminum oxide layer disposed on the aluminum nitride layer, and is deposited by, for example, Atomic Layer Deposition (ALD), and the passivation layer 105 and the oxide layer 106 cover the barrier layer 103 and the gate opening 1041 on the barrier layer 103. The thickness of the passivation layer 105 is, for example, 1 to 5nm, and specifically, may be, for example, 2 nm. The thickness of the oxide layer 106 is, for example, 5 to 10nm, specifically, 8 nm. And after the oxide layer 106 is formed, the passivation layer 105 and the oxide layer 106 are exposed to N₂The environment and the temperature are, for example, 300-.

As shown in fig. 2 to fig. 6, since the AlN material of the passivation layer 105 has a higher forbidden bandwidth and a higher thermal conduction efficiency, the blocking capability of the gate dielectric against the leakage current and the quality of the interface with the gan can be improved. When the forbidden band width and the conduction band offset are large, electrons can be restrained from passing through the dielectric layer, and the grid leakage condition is reduced. Because aluminum nitride and gallium nitride have good lattice matching and thermal conductivity characteristics, the aluminum nitride in the passivation layer 105 is in direct contact with the gallium nitride, which can improve the quality of the interface. Meanwhile, in the present embodiment, aluminum nitride and aluminum oxide are used as the gate insulating dielectric, and the aluminum nitride layer formed by PEALD can reduce the interface defect between the oxide layer 106 and the gallium nitride, reduce the leakage current of the gate 109, and improve the stability and reliability of the gate 109, so that the semiconductor device has a lower threshold voltage hysteresis. The phenomenon of threshold voltage hysteresis caused by the fact that deep level traps exist at the interface of the oxide layer 106 and the barrier layer 103 to trap channel electrons under larger forward gate pressure can be avoided, and the stability of the threshold voltage is further improved.

Referring to fig. 1, 5 to 6, after the passivation layer 105 and the oxide layer 106 are formed, a source electrode 107, a gate electrode 109 and a drain electrode 108 are formed, respectively. The source 107 and drain 108 are located on either side of the gate opening 1041 and are in contact with the barrier layer 103. Grid electrode109 are located within the interface and are in contact with the oxide layer 106. In this embodiment, both sides of the passivation layer 105 and the oxide layer 106 may be etched to the barrier layer 103, and the metal Ti/Al/Ni/Au may be deposited on the barrier layer 103 on both sides of the passivation layer 105 and the oxide layer 106, respectively, to form the source electrode 107 and the drain electrode 108. Where Ti/Al/Ni/Au is indicated herein, the gate 103 includes a titanium metal layer, an aluminum metal layer disposed on the titanium metal layer, a nickel metal layer disposed on the aluminum metal layer, and a gold metal layer disposed on the nickel metal layer. The subsequent writing method is the same as that in the present embodiment, and will not be described in detail later. After forming the source 107 and drain 108, nitrogen (N) may be used₂) Ambient and temperature conditions such as 750-. In the present embodiment, as shown in fig. 5, the source 107 and the drain 108 may be as high as the oxide layer 106. As shown in fig. 6, the source 107 and the drain 108 are higher than the oxide layer 106. After the source 107 and the drain 108 are formed, Ni/Au metal is deposited on the oxide layer 106 in the gate opening 1041 and on the oxide layer 106 at two sides of the gate opening 1041 to form the gate 109, and the cross section of the gate 109 may be in a symmetrical "T" shape. In the present embodiment, the distance between the source 107 and the gate 109 is, for example, 2-3um, and specifically, for example, 2.5 um. The distance between the gate 109 and the drain 108 is, for example, 14-15um, specifically, 14.5 um. The width of the gate 109 is, for example, 3-4um, specifically, 3 um. The source 107 and the drain 108 may be as high as the gate dielectric layer, or may be as high as the gate dielectric layer and as high as the gate 109. Since the barrier layer 103 at the bottom of the gate 109 in this embodiment is completely etched, the threshold voltage is not sensitive to the etching depth, and the electric field inside the gan is weak when the device is turned off, which further reduces the hysteresis of the threshold voltage.

Referring to fig. 7 to 11, in another embodiment of the present invention, an insertion layer 113 may be further disposed in the channel layer 102 to divide the channel layer 102 into a plurality of channel layers, so as to form a plurality of two-dimensional electron gas channels. In the present embodiment, for example, one insertion layer 113 and two channel layers are provided. Specifically, referring to fig. 10, for example, gallium nitride of 3-6um may be deposited on a silicon substrate 100 by using a vapor phase epitaxy (MOCVD) technique to form a first channel layer1021, and the thickness of the first channel layer 1021 is specifically 4um, for example. After the first channel layer 1021 is formed, 1-2nm of aluminum nitride is deposited on the first channel layer 1021 to form the insertion layer 113, and the thickness of the insertion layer 113 is 1.5nm, for example, specifically. After the formation of the insertion layer 113, a gallium nitride layer of 5-7nm is deposited on the insertion layer 113 to form the second channel layer 1022, and the thickness of the second channel layer 1022 is specifically, for example, 6 nm. After forming the second channel layer 1022, 15-20nm of aluminum gallium nitride may be deposited over the second channel layer 1022 to form the barrier layer 103, and the thickness of the barrier layer 103 is, for example, 17 nm. In the present application, after the barrier layer 103 is formed, ammonia (NH) gas may be used for the surface of the barrier layer 103₃) The treatment is performed so that N atoms in the ammonia gas are bonded to vacancies on the surface of the barrier layer 103, thereby reducing defects on the surface of the barrier layer 103. In addition, the gate dielectric layer in the implementation includes an oxide layer 106 processed at a high temperature, and a better interface is formed between the oxide layer 106 and the barrier layer 103. The current collapse effect caused by etching damage when the gate opening 1041 is etched to form a recessed gate is avoided.

Referring to fig. 7 to 10, after the barrier layer 103 is formed, the barrier layer 103, the insertion layer 113 and the second channel layer 1022 with a predetermined thickness are etched to form a gate opening 1041. In the present embodiment, when the gate opening 1041 is formed, the etching depth of the recessed gate is, for example, 20nm to 25nm, and specifically, for example, 23nm, that is, 1 nm to 1.5nm of the second channel layer 1022 is removed, so as to ensure that the barrier layer 103 under the gate opening 1041 is completely etched when the gate opening 1041 is formed. After forming the gate opening 1041, a layer of aluminum oxide may be deposited as the oxide layer 106 on the gate opening 1041 and the barrier layer 103 by using Atomic Layer Deposition (ALD), and the oxide layer 106 may be used as a gate dielectric layer. After the oxide layer 106 is formed, the oxide layer 106 may be filled with oxygen (O) at 500 deg.C₂) An annealing process is performed in the ambient to improve the quality of the oxide layer 106. For Al prepared by ALD₂O₃Dielectric material of Al₂O₃The energy band difference between the GaN and the substrate is large, the grid leakage current can be effectively reduced, the grid annealing is carried out, and the quality of an oxide layer can be improved.

Referring to fig. 8 to 10, in the present embodiment, after the oxide layer 106 is formed, both ends of the oxide layer 106 and the barrier layer 103 are etched to the second channel layer 1022, and Ti/Al/Ni/Au metal is deposited on both ends of the oxide layer 106 and the barrier layer 103 to form the source electrode 107 and the drain electrode 108. And metal Ni/Au is deposited in the gate opening 1041 and over the gate opening 1041 to form the gate 109, and the gate 109 extends to both sides of the gate opening 1041.

Referring to fig. 7 to 10, in the present embodiment, a first two-dimensional electron gas channel 114 is formed at the junction of the first channel layer 1021 and the insertion layer 113, and is located in the first channel layer 1021. At the junction of the second channel layer 1022 and the barrier layer 103, and within the second channel layer 1022, a second two-dimensional electron gas channel 115 is formed. In addition, in the embodiment, the gate 109 extends to the second two-dimensional electron gas channel 115 and is located above the first two-dimensional electron gas channel 114, and the first two-dimensional electron gas channel 114 is not etched at all, so that a higher mobility can be maintained, and a formed semiconductor device has a higher breakdown voltage. In particular, the breakdown voltage may reach, for example, 700V. And in the present embodiment, the first two-dimensional electron gas channel 114 is 5-7nm, for example, 6nm away from the heterostructure formed by the second channel layer 1022 and the barrier layer 103. Closer relative to the channel in a dual channel device. Therefore, the mobility of the first two-dimensional electron gas channel 114 is large, so the on-resistance is lower, and the on-current of the drain 108 is large, so that the semiconductor device has a stable sub-threshold swing.

Referring to fig. 10, in the present embodiment, the source 107 and the drain 108 are in contact with the second channel layer 1022, when the voltage of the gate 109 is 0, the insertion layer 113 is thin and is not enough to generate the second two-dimensional electron gas channel 115, and the depth of the potential well is increased due to the raising action of the first channel layer 1021, which is not enough to generate the first two-dimensional electron gas channel 114, and both two-dimensional electron gas channels are closed. When the gate 109 voltage increases, the potential barrier decreases and the two-dimensional electron gas channels open.

Referring to fig. 11, in another embodiment, the insertion layers include a first insertion layer 1131 disposed between the first channel layer 1021 and the second channel layer 1022, and a second insertion layer 1132 disposed between the second channel layer 1022 and the barrier layer 103. And the thickness of the second insertion layer 1132 is the same as that of the first insertion layer 1131, specifically, for example, 1.5 nm. A cap layer 116, a protective layer 117, and a passivation layer 105 are also provided between the barrier layer 103 and the oxide layer 106. Specifically, after the barrier layer 103 is formed, gallium nitride of 2 to 5nm is deposited on the barrier layer 103 to form the cap layer 116, and the thickness of the cap layer 116 is specifically, for example, 3 nm. In the present embodiment, after forming the cap layer 116, a layer of aluminum nitride or silicon nitride is deposited on the cap layer 116 as the protection layer 117. The thickness of the protection layer 117 is not limited in this embodiment, and the thickness of the protection layer 117 may be, for example, 10 to 1000 nm. After the formation of the protection layer 117, the cap layer 116, the barrier layer 103, the second insertion layer 1132, and the second channel layer 1022 having a predetermined thickness are etched to form a gate opening. In the present embodiment, the gate opening is formed by, for example, removing 1-1.5nm of the second channel layer 1022 to ensure that the barrier layer 103 under the gate opening is completely etched when the gate opening is formed. After forming the gate opening, a layer of aluminum nitride may be deposited in the passivation layer 117 and the opening in sequence as the passivation layer 105, and a layer of aluminum oxide as the oxide layer 106. In this embodiment, the passivation layer 105 and the oxide layer 106 are used as gate dielectric layers, the passivation layer 105 can further suppress interface defects between the gan and the alumina, and after the oxide layer 106 is formed, the oxide layer 106 can be annealed to improve the quality of the oxide layer 106.

Referring to fig. 11, in the present embodiment, after forming the gate dielectric layer, both ends of the gate dielectric layer and the protection layer 117 are etched to the cap layer 116, and metal is deposited on both ends of the gate dielectric layer and the protection layer 117 to form the source electrode 107 and the drain electrode 108. And metal is deposited in and over the gate opening to form a gate 109, and the gate 109 extends to both sides of the gate opening 1041. In the present embodiment, the first two-dimensional electron gas channel 114 is formed at the junction of the first channel layer 1021 and the insertion layer 113, and within the first channel layer 1021. At the junction of the second channel layer 1022 and the second insertion layer 1132, and within the second channel layer 1022, a second two-dimensional electron gas channel 115 is formed. In addition, in the embodiment, the gate 109 extends to the second two-dimensional electron gas channel 115 and is located above the first two-dimensional electron gas channel 114, and the first two-dimensional electron gas channel 114 is not etched at all, so that a higher mobility can be maintained, and a formed semiconductor device has a higher breakdown voltage.

Referring to fig. 12 to 17, in an embodiment of the invention, power loss caused by leakage current of the gate 109 can be reduced by the structure of the gate 109. In the present embodiment, the substrate 100 is a silicon substrate, and has a thickness of 100-200nm, such as 150 nm. The buffer layer 101 is disposed on the substrate 100, and specifically, for example, gallium nitride or aluminum nitride of 2-4um may be formed on the substrate 100 by a Metal Organic Chemical Vapor Deposition (MOCVD) method to form the buffer layer 101, and the thickness of the buffer layer 101 is specifically, for example, 2.8 um.

Referring to fig. 12, in the present embodiment, an epitaxial structure is disposed on the buffer layer 101, for example, the epitaxial structure includes a channel layer 102 and a barrier layer 103 disposed in sequence, the channel layer 102 is, for example, 120-170nm gallium nitride, and the thickness of the channel layer 102 is, for example, 150 nm. The barrier layer 103 is, for example, an aluminum nitride and is, for example, Al of 20-30nm_0.21GA_0.79N, the specific thickness of the barrier layer 103 is, for example, 25 nm.

Referring to fig. 12, in the present embodiment, after the epitaxial structure is formed, a gate dielectric layer 110 may be formed on the barrier layer 103, and in the present embodiment, for example, a low pressure chemical vapor deposition method may be used to deposit 25-35nm of silicon nitride (Si) on the barrier layer 103₃N₄) To form a gate dielectric layer 110, and the thickness of the gate dielectric layer 110 is 30nm, for example. After forming the gate dielectric layer 110, a protective layer 111 may be formed on the gate dielectric layer 110. Specifically, for example, a plasma enhanced chemical vapor deposition method may be used to deposit 180-220nm thick tetraethyl orthosilicate (TEOS) on the gate dielectric layer 110 to form the protective layer 111, and the thickness of the protective layer 111 is, for example, 200 nm.

Referring to fig. 12 to 16, in the present embodiment, the semiconductor device is provided with the gate 109 having a special shape, so as to reduce the electric field intensity at the edge of the gate. Specifically, after the protective layer 111 is formed, a gate opening is formed on the epitaxial structure and metal is deposited in the gate opening to formAnd a gate 109. In the present embodiment, the gate opening includes a first region 1042 and a second region 1043. For example, first, in the middle region of the epitaxial layer, the protective layer 111 is etched toward the substrate 100, and the protective layer 111 and the gate dielectric layer 110 are removed in the etched region to form a first region 1042. The bottom of the first region 1042 is in contact with the barrier layer 103, and a portion of the barrier layer 103 can be etched away when forming the first region 1042. After forming the first region 1042, 25-35nm of silicon nitride (Si) is deposited simultaneously in the first region 1042 and on the protective layer 111₃N₄) To form passivation layer 112. The passivation layer 112 has a thickness of, for example, 35nm, and the passivation layer 112 in the first region 1042 is connected to the gate dielectric layer 110 to isolate a portion of the gate electrode 109 from the barrier layer 103, thereby blocking tunneling of gate electrons. After the passivation layer 112 is formed, the barrier layer 103 in the etched region is etched away along a sidewall of the first region 1042 toward the substrate 100 to form a second region 1043. The bottom of the second region 1043 is in contact with the channel layer 102. The second region 1043 is located at one side of the first region 1042, and the width of the second region 1043 is 1/3-2/3 of the width of the first region 1042, specifically, the width of the second region 1043 is 1/2 of the width of the first region 1042. The first region 1042 may be formed by etching using SF₆Etching, wherein sulfur hexafluoride (SF) is used for etching the second region 1043₆) And boron chloride (BCl)₃) And (6) etching.

Referring to fig. 13 to 15, in the present embodiment, after the gate opening is formed, the surface of the etched barrier layer 103 may be cleaned by using plasma to reduce the etching damage. After forming the gate opening, metal is deposited in the first region 1042 and the second region 1043 within the gate opening to form a stepped gate 109. In this embodiment, the metal in the first region 1042 forms a schottky contact with the barrier layer 103 and the channel layer 102. The metal in the second region 1043 is equivalent to a field plate structure, which can improve the breakdown voltage of the device. The stepped gate 109 thus effectively blocks electron tunneling and redistributes the electric field at the edge of the schottky contact, resulting in a smaller gate 109 leakage current than conventional devices, and thus reduced power loss due to gate 109 leakage current.

Referring to fig. 15 to 16, in the present embodiment, the passivation layer 112, the protection layer 111, the gate dielectric layer 110 and the barrier layer 103 are etched on both sides of the gate electrode 109 to the channel layer 102, and Ti/Al/Ni/Au metal is deposited on the channel layer 102 to form the source electrode 107 and the drain electrode 108. In this embodiment, the protruding portion of the gate electrode 109 is close to the drain electrode 108 side. The electric field intensity of the edge of the gate 109 close to the drain side is prevented from being much larger than that of the electric field intensity below the gate 109 under the same bias voltage, so that the device is easy to break down under a smaller drain voltage due to uneven electric field distribution. And the larger electric field at the edge of the gate 109 causes electrons to be injected laterally from the gate 109 into the surface states of the barrier layer 103, the trapped electrons can hop from one surface state to another under high field, resulting in surface lateral leakage current. The stepped gate 109 in this embodiment can reduce the electric field intensity at the edge of the gate 109, so that the inner electric field is distributed uniformly, and the generation of leakage current of the gate 109 is prevented, thereby improving the breakdown voltage to a greater extent.

Referring to fig. 17, in another embodiment of the present invention, the shaped gate 109 includes a first sub-portion 109a disposed in the gate opening and a second sub-portion 109b disposed on the gate opening, so that both low-pass resistance and very high breakdown voltage can be obtained. In the present embodiment, the epitaxial structure includes a channel layer 102 disposed on the substrate 100 and a barrier layer 103 disposed on the channel layer 102, wherein the channel layer 102 is, for example, gallium nitride, and the barrier layer 103 is, for example, an aluminum gallium nitride layer. The barrier layer 103 is provided with an opening, and for example, boron chloride (BCl) can be used₃) Or chlorine (Cl)₂) The barrier layer 103 is plasma etched to form openings, and metal is deposited in the openings to form recessed gates, and the barrier layer 103 under the recessed gates is etched in its entirety. In this embodiment, an oxide layer 106 is further disposed on the barrier layer 103 as a gate dielectric layer, and the oxide layer 106 covers the opening, where the oxide layer 106 is, for example, an aluminum oxide layer. In forming the gate electrode 109, both sides of the oxide layer 106 and the barrier layer 103 may be etched to the channel layer 102, or a portion of the thickness of the channel layer 102 may be etched and metal may be deposited on the channel layer 102 to form the source electrode 107 and the drain electrode 108. On the openingMetal is deposited on the oxide layer 106 and on the oxide layer 106 on both sides of the opening to form a gate 109, and the source 107 and the drain 108 are located on both sides of the gate 109.

Referring to fig. 17, in an embodiment of the invention, the gate 109 includes a first sub-portion 109a disposed in the opening and a second sub-portion 109b disposed on the opening. The first sub-portion 109a is located in the opening to form a recessed gate, and the length of the first sub-portion 109a is, for example, 90-100nm, and specifically, for example, 95 nm. Since the opening where the first segment 109a is located has been etched into the channel layer 102, a structure similar to an enhanced metal-oxide semiconductor field effect transistor (MOSFET) can be formed, and the electron mobility under the etched region is lower, thereby obtaining a lower on-resistance. The second portion 109b is disposed on the opening and extends on the oxide layer 106, and the length of the second portion 109b is, for example, 0.8-1.2um, specifically, 1 um. In this embodiment, the length D2 of the second section 109b exceeds the length D1 of the first section 109a, and the ratio of the length D2 of the second section 109b to the length D1 of the first section 109a is close to 10:1, for example, in the range of 9:1 to 12: 1. A structure similar to a depletion mode High Electron Mobility Transistor (HEMT) is formed. Due to the arrangement of the first and second sub-sections 109a, 109b, both a low-pass resistance and a large breakdown voltage can be obtained. When the semiconductor device is operated, the threshold voltage can be controlled by the first section 109a, and the drain 108 can be controlled to have a larger voltage by the second section 109 b. And the second sub-portion 109b is asymmetrically disposed with respect to the first sub-portion 109a, and has an extension length toward the drain electrode 108 greater than an extension length toward the source electrode 107. When the device is turned off, the second section 109b near the drain 108 side concentrates the electric field, thereby shielding the electric field at the edge of the first section 109 a. The problem that the controllability of threshold voltage is poor due to overlarge leakage current of the gate 109 is avoided.

Referring to fig. 17, in the present embodiment, the length D1 of the first portion 109a of the gate 109 is set so that the gate 109 has a smaller on-resistance, and the length D2 of the second portion 109b is set so that the voltage of the drain 108 can be controlled, and in the present embodiment, the distance between the second portion 109b and the channel includes only the oxide layer 106 and the barrier layer 103, so that the control capability of the gate 109 can be further improved. By arranging the special-shaped grid 109, the current leakage of the drain electrode 108 caused by low blocking force of the potential around the channel can be avoided. And gate 109 leakage current caused by etching damage is large and threshold voltage controllability is poor during recess gate etching.

Referring to fig. 18 to 23, in another embodiment of the present invention, a semiconductor device having a ring-shaped gate is further provided to suppress leakage current. In the present embodiment, for example, aluminum nitride is deposited on a silicon substrate 100 as a buffer layer 101, and a gallium nitride layer is deposited on the buffer layer 101 as a channel layer 102, and an aluminum gallium nitride forming barrier layer 103 is deposited on the channel layer 102. The material of the barrier layer 103 is specifically, for example, Al_0.25Ga_0.75And N is added. After the formation of the GaN/AlGaN heterostructure, silicon nitride (Si) is deposited on the barrier layer 103 to a thickness of, for example, 25-35nm₃N₄) As the gate dielectric layer 110, a specific thickness of the silicon nitride layer is, for example, 30 nm. And the silicon nitride can simultaneously serve as a surface passivation layer. After the gate dielectric layer 110 is formed, chlorine gas (Cl) is used on the outside of the gate dielectric₂) Boron chloride (BCl)₃) The plasma etches toward the substrate 100 side, forming isolation trenches 118. And the gate dielectric layer 110 and the barrier layer 103 are etched away to the surface of the channel layer 102, and the channel layer 102 with a partial thickness can also be etched away, so as to ensure that the barrier layer 103 is completely etched. So that the gate dielectric layer 110 and the barrier layer 103 in the middle of the etching form a mesa structure.

Referring to fig. 20, in the present embodiment, after forming the mesa structure, a passivation layer 119 is formed on the mesa structure and the isolation trench 118, and the passivation layer 119 covers the surface of the gate dielectric layer 110 and fills a portion of the isolation trench 118, which can be used for planarization. Specifically, for example, a layer of 400-600nm silicon dioxide (SiO) can be deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD)₂) To form a passivation layer 119. The thickness of the passivation layer 119 is, for example, 500 nm.

Referring to fig. 20 to 23, in the present embodiment, after the passivation layer 119 is formed, a source opening, a drain opening and a gate opening are formed on the passivation layer 119. Wherein the source opening is used for depositing metal to form the source 107, the drain opening is used for depositing metal to form the drain 108, and the gate opening is used for depositing metal to form the source 107. In the present embodiment, the source opening is located at one side of the passivation layer 119 and near the isolation trench 118. The drain opening is located on the other side of the passivation layer 119 and near the central region of the passivation layer 119 to ensure the formation of the ring-shaped gate 109. The gate opening is disposed around the drain opening and has a predetermined distance from the isolation trench 118. And the source opening and the drain opening are etched into channel layer 102 and contact channel layer 102, and the gate opening is etched into gate dielectric layer 110 and contact gate dielectric layer 110.

Referring to fig. 20-23, in the present embodiment, after forming the source opening and the drain opening, Ti/Al/Ti/TiN metal is deposited in the source opening to form the source 107, and Ti/Al/Ti/TiN metal is deposited in the drain opening to form the drain 108. After forming the source 107 and the drain 108, a gate opening is formed by etching, and a metal TiN is deposited in the gate opening to form the gate 109, and a plurality of electrodes may be deposited by Physical Vapor Deposition (PVD). The source 107 is disposed on one side of the gate 109, and the gate 109 is disposed around the drain 108. The gate 109 channel surrounding the drain 108 can suppress leakage current because leakage current not provided around the ring gate 109 includes gate 109 to source 107 leakage current, mesa edge to source 107 leakage current, and gate 109 surrounded region to source 107 leakage current. After the gate 109 surrounding the drain 108 is provided, the high voltage applied to the drain 108 can be cut off by the channel of the gate 109, so that the mesa edge outside the gate 109 and the region surrounded by the gate 109 can be protected from the high voltage of the drain 108, thereby eliminating the leakage current caused by the high voltage at the mesa edge and the isolation region, realizing ultra-low leakage current and high on/off current ratio of the drain 108, and further protecting the semiconductor device from the damage of the high leakage voltage.

Referring to fig. 23, in the present embodiment, the source 107 and the drain 108 are disposed in a rectangular shape, and the gate 109 is disposed in a rectangular ring shape. The source 107 and the gate 109 have a first distance L1. The gate 109 is equidistant from the drain 108 on opposite sides of the drain 108. The gate 109 and the drain 108 have a second distance L2 in a connecting direction of the source 107 and the drain 108, and the gate 109 and the drain 108 have a third distance L3 in a connecting direction perpendicular to the source 107 and the drain 108. In the present embodiment, the first distance L1 is greater than the second distance L2 and the third distance L3, and the second distance L2 is equal to the third distance L3. The voltage between the gate 109 and the drain 108 can be balanced, ensuring the quality of the formed semiconductor device. In other embodiments, the source 107 and drain 108 are arranged in a circular configuration and the gate 109 is arranged in a circular ring. Alternatively, the source 107 and the drain 108 are disposed in an elliptical shape, and the gate 109 is disposed in an elliptical ring shape. The present invention does not limit the specific shapes of the source 107, the drain 108, and the gate 109 as long as the drain 108 and the gate 109 disposed outside the drain 108 correspond in shape.

Referring to fig. 24, in another embodiment of the present invention, gate leakage current can be improved by changing the material of the gate. In this embodiment, a higher schottky barrier metal gate to p-GaN interface may be used to reduce the gate leakage current of the device.

In the present embodiment, a buffer layer 101 is provided on a substrate 100, and an epitaxial structure includes a channel layer 102 provided on the buffer layer 101, and a barrier layer 103 provided on the channel layer 102. In the present embodiment, the channel layer 102 is made of gan, and the thickness of the channel layer 102 is, for example, 1.0-1.1um, specifically, 1.0 um. The material of the barrier layer 103 is specifically Al_0.26Ga_0.74N, and the barrier layer 103 has a thickness of, for example, 10 to 15nm, specifically, 10nm, for example.

Referring to fig. 24, in the present embodiment, a gan layer 127, which is a P-type gan layer, is formed on the barrier layer. The thickness of the P-type gallium nitride layer is, for example, 40 to 60nm, specifically, 50 nm. After the P-type gallium nitride layer is formed, the P-type gallium nitride layer is etched such that gallium nitride layer 127 covers only the locations where the gates are formed. The P-type gallium nitride layer 127 disposed under the gate 109 may deplete channel charges so that the device is in an off state in an initial state. Holes are injected from the P-GaN into the heterojunction, which can increase the electron concentration of the channel. And a P-GaN structure is arranged under the gate 109, so that lower gate leakage current can be realized under higher gate voltage. The gallium nitride layer 127 can improve the potential of a channel, deplete electrons below a gate, when the gate voltage is 0V, the electrons below the channel are completely depleted, when the gate voltage reaches the built-in potential of a PN junction, holes are injected into the channel layer from the P-type gallium nitride layer, but the electrons of the channel are blocked by a potential barrier of a heterojunction and cannot reach the gate, the holes are gathered in a channel region to attract a large number of electrons for neutralization, the accumulated electrons have high mobility under a high drain voltage condition, but the mobility of the injected holes is 2 orders of magnitude lower than that of the electrons, so that the holes can only be gathered below the gate electrode, and further, the low gate current and the large drain current are ensured.

Referring to fig. 24, in the present embodiment, after forming the gallium nitride layer 127, a source 107 and a drain 108 are disposed on two sides of the epitaxial structure, respectively, and the source 107 and the drain 108 are made of Ti/Al/Ni/Au. And after forming the source 107 and the drain 108, a high temperature anneal may be performed on the source 107 and the drain 108 to improve the quality of the source 107 and the drain 108. After source 107 and drain 108 are formed, metal Ti/Al is deposited on gallium nitride layer 127 to form gate 109. And the thickness of the Ti metal layer in the gate electrode 109 is, for example, 25 to 35nm, specifically, 30nm, for example. The thickness of the Al metal layer is, for example, 165-175nm, specifically, 170 nm. The schottky barrier height of the Ti/Al contact is 2.08eV, the higher metal/p-GaN schottky barrier height is beneficial to reducing the gate leakage current and shifting the threshold voltage to the positive direction, and the HEMT device with the positive threshold voltage can combine the safe operation with the driving circuit.

Referring to FIG. 24, in another embodiment, the gate comprises a Au/TiN metal layer, for example, and the thickness of the TiN film is less than 10nm, for example. And the TiN thin film is formed by high temperature annealing based on TiN and nitride, and the thermal annealing condition is less than 700 ℃, for example, to avoid TiN decomposition or nitrogen vacancy formation. The oxygen impurities and nitrogen vacancies are N-type dopants, enhancing leakage current through the barrier by tunneling. The thermal annealing process can reduce oxygen impurities and nitrogen vacancies and trigger stress modulation inside the AlGaN layer. As the TiN/AlGaN interface strain decreases, a strain gradient is created in the AlGaN barrier, resulting in a pseudo P-type doping at the surface of the AlGaN barrier. Thereby significantly reducing leakage current. Unlike other commonly used gate metals such as Au, Pt, or Ni, TiN does not diffuse into the AlGaN barrier layer even after thermal annealing. To form a pseudo P-type layer in the AlGaN layer requires a reduction in strain at the TiN/AlGaN interface, and therefore the TiN layer needs to have a higher compressive strain after thermal annealing to partially compensate for the tensile strain of the AlGaN barrier layer at the TiN/AlGaN interface. And further, a simple TiN gate metal preparation process is realized so as to improve the reliability of the gate. A reduction in tensile stress in the AlGaN layer near the TiN/AlGaN interface is observed for thinner TiN films after thermal annealing. So that the AlGaN barrier surface forms a pseudo P-type layer (like a diode) to significantly reduce the gate leakage current. The manufacturing process reserves a larger band gap of the AlGaN potential barrier and is an effective method for improving the breakdown voltage of the gate.

Referring to fig. 25 to 28, in another embodiment of the present invention, a P-type gan gate can be prepared by using hydrogen plasma, which can significantly suppress the current collapse effect and reduce the surface leakage. In the present embodiment, the substrate 100 is, for example, a silicon substrate, and the buffer layer 101 is disposed on the substrate 100 and is, for example, made of gallium nitride doped with carbon. And the thickness of the buffer layer 101 is, for example, 4-5um, specifically, 4.8 um. The channel layer 102 is disposed on the buffer layer 101, and is, for example, a non-doped gallium nitride layer with a thickness of 140 nm and 160nm, and the thickness of the channel layer 102 is, for example, 150 nm. The barrier layer 103 is provided on the channel layer 102, and is, for example, an undoped aluminum gallium nitride layer having a thickness of 15 to 20nm, and the barrier layer 103 has a thickness of, specifically, 18nm, for example. Gallium nitride layer 127 is disposed on barrier layer 103, and gallium nitride layer 127 is, for example, a P-type gallium nitride layer having a thickness of 60-80 nm. The gallium nitride layer 127 is doped with, for example, Mg ions at a doping concentration of, for example, 2X 10⁹cm^-3-3×10⁹cm^-3。

Referring to fig. 26 to 27, in the present embodiment, after the gallium nitride layer 127 is formed, a source opening 1044 and a drain opening 1045 are formed on two sides of the gallium nitride layer 127, respectively, and metal Ti/Al/Ni/Au is deposited in the openings to form the source 107 and the drain 108. In forming the opening, the gan layer 127 and the barrier layer 103 with a predetermined thickness may be etched away. After forming the source 107 and drain 108, the semiconductor device is filled with N at, for example, 800-₂Environment ofThe intermediate rapid thermal treatment may be performed for 30 to 50 seconds, for example, and the temperature may be 850 ℃ for example, and the rapid thermal treatment may be performed for 30 seconds, for example, to form a good ohmic contact. After the source electrode 107 and the drain electrode 108 are formed, metal Ni/Au is evaporated on the gallium nitride layer 127 to form a gate electrode 109. Wherein the gate 109 is disposed proximate to the source 107.

Referring to fig. 28, in the present embodiment, after the electrodes are formed, the gallium nitride layer 127 is treated with hydrogen plasma, and the hydrogen plasma is injected into the gallium nitride layer 127. The hydrogen atoms may passivate shallow acceptor impurities in gallium nitride layer 127, and passivated gallium nitride layer 127 is converted to a high resistance state to form passivation layer 1273. In the present embodiment, after implanting hydrogen atoms in gallium nitride layer 127, a Mg — H complex may be generated. And for example, an ICP deep reactive etcher (Oxford plasma System100) may be used for hydrogen plasma injection. To ensure that the depth of hydrogen injection does not affect the two-dimensional electron gas channel, the power of the ICP deep reactive etcher is set to, for example, 300W, the chamber pressure is set to, for example, 8mTorr, the RF power is set to, for example, 2W, and the plasma energy and density can be adjusted by varying the ICP power in the low pressure regime. After the hydrogen atom implantation is completed, the semiconductor device may be annealed at, for example, 300-.

Referring to fig. 28, in the present embodiment, after the gallium nitride layer 127 is processed by using the hydrogen plasma, the passivation layer 1273 is formed on the surface of the gallium nitride layer 127 not covered by the gate, so as to significantly suppress the current collapse effect and reduce the surface leakage, and the GaN gallium nitride layer 127 can shield the surface potential fluctuation. Negative polarization charges exist on the GaN/AlGaN interface, so that the longitudinal electric field in the AlGaN can be improved, and the transverse electric field gathered at the edge of the grid electrode is reduced. The gallium nitride layer 127 covered by the gate is still a P-type gallium nitride layer, and the formed polarization junction ensures that the semiconductor device obtains larger breakdown voltage and inhibits the current collapse phenomenon of the device while ensuring lower on-resistance, so that the static power consumption of the semiconductor device is further reduced, and the overall performance of the device is improved.

Referring to FIG. 29, in another embodiment of the present invention, another liquid crystal display device having other elements is providedThe semiconductor device made of the gate material can simultaneously have higher breakdown electric field and thermal stability. In the present embodiment, an aluminum nitride buffer layer 101 is provided on a silicon substrate 100, and an epitaxial structure includes a gallium nitride channel layer 102 provided on the buffer layer 101, and an aluminum gallium nitride barrier layer 103 provided on the channel layer 102. In the present embodiment, the material of the barrier layer 103 is specifically Al_0.23Ga_0.77N, and the barrier layer 103 has a thickness of, for example, 45 to 55nm, specifically, 47nm, for example. A thicker barrier layer 103 may generate sufficient two-dimensional hole gas. On both sides of the epitaxial structure, a source electrode 107 and a drain electrode 108 are disposed in contact with the channel layer 102, respectively, and the material of the source electrode 107 and the drain electrode 108 is Ti/Al/Ni/Au.

Referring to fig. 29, in the present embodiment, a first gallium nitride layer 1271 and a second gallium nitride layer 1272 are further disposed on the barrier layer 103 and between the source 107 and the drain 108, wherein the first gallium nitride layer 1271 is disposed on the barrier layer 103, and the second gallium nitride layer 1272 is disposed on the first gallium nitride layer 1271. The first gallium nitride layer 1271 is an undoped gallium nitride layer, and the thickness of the first gallium nitride layer 1271 is, for example, 10-15nm, specifically, 10 nm. The second gallium nitride is a P-type doped gallium nitride layer with a doping concentration of, for example, 2 × 10⁹cm^-2-5×10⁹cm^-2Specifically, for example, 3X 10⁹cm^-2. The thickness of the second gallium nitride layer 1272 is, for example, 30 to 40nm, and specifically, 30nm, for example. Wherein the second gallium nitride layer 1272 completely covers the first gallium nitride layer 1271. The width of the first gallium nitride layer 1271 is equal to the width of the second gallium nitride layer 1272, and the width of the first gallium nitride layer 1271 and the width of the second gallium nitride layer 1272 are smaller than the distance between the source electrode 107 and the drain electrode 108, so as to ensure that the first gallium nitride layer 1271 and the second gallium nitride layer 1272 have a preset distance between the source electrode 107 and the drain electrode 108.

Referring to fig. 29, in the present embodiment, a gate 109 is disposed between the source 107 and the gan layer. The gate 109 is in contact with the first gallium nitride layer 1271 and the second gallium nitride layer 1272, and the height of the gate 109 is higher than the second gallium nitride layer 1272. At the corner where the gate 109 and the second gallium nitride layer 1272 are formed, the base electrode 129 is also provided. The base electrode 129 is disposed at the same height as the gate electrode 109, and the base electrode 129 is made of the same material as the gate electrode 109. In the manufacturing process, the gate electrode 109 and the base electrode 129 may be obtained by depositing metal Ti/Al. In the present embodiment, the base electrode 129 is connected to the gate electrode 109 and forms an ohmic contact with the second gallium nitride layer 1272, so that when the device is turned off, the two-dimensional electron gas and the two-dimensional hole gas between the base electrode 129 and the drain electrode 108 can cancel each other at a lower drain voltage, and the breakdown voltage of the semiconductor device can be further improved.

Referring to fig. 30-37, in an embodiment of the invention, when the P-type gan layer 127 is disposed under the gate 109, the device is affected by current collapse under high voltage conditions. The present embodiment provides a semiconductor device, which can leave the P-type gallium nitride layer 127 at the edge of the drain 108 when etching the P-type gallium nitride layer 127, and is connected to the drain 108, so as to prevent the current collapse under high voltage when the device is turned off. In the present embodiment, an aluminum nitride buffer layer 101 is disposed on the substrate 100, and the buffer layer 101 is, for example, aluminum oxide. The channel layer 102 is disposed on the buffer layer 101, and the channel layer 102 is, for example, gallium nitride. A barrier layer 103 is disposed on channel layer 102, and barrier layer 103 is, for example, aluminum gallium nitride. A high density of two-dimensional electron gas is generated at the AlGaN/GaN interface. The channel layer 102 is provided with a gallium nitride layer 127, and is a P-type gallium nitride layer. The thickness of gallium nitride layer 127 is, for example, 40-100 nm.

Referring to fig. 31-32, in the present embodiment, after the gallium nitride layer 127 is formed, the gallium nitride layer 127 is etched to form a first gallium nitride structure 1273 and a second gallium nitride structure 1274. The first gallium nitride structure 1273 is located below the gate 109, and the second gallium nitride layer 127 structure is located between the gate 109 and the drain and close to the drain. After the first gallium nitride structure 1273 and the second gallium nitride structure 1274 are formed, a layer of silicon nitride and a layer of silicon oxide are sequentially deposited on the barrier layer 103, the first gallium nitride structure 1273 and the second gallium nitride structure 1274, and a first passivation layer 1301 and a second passivation layer 1302 are respectively formed. The arrangement of the passivation layers on both sides can reduce the influence of surface defects of the barrier layer 103 on the reliability of the semiconductor device. The thickness of the passivation layer on the first gallium nitride structure 1273 and the second gallium nitride structure 1274 is equal to the thickness of the passivation layer on the barrier layer 103. Two protrusions are thus formed on the passivation layer, including, for example, a first protrusion 135 on the first gallium nitride structure 1273 and a second protrusion 136 on the second gallium nitride structure 1274.

Referring to fig. 33 to 34, after forming the passivation layer, a source opening 1044 is formed on a side of the first gallium nitride structure 1273 opposite to the second gallium nitride structure 1274, and a drain opening 1045 is formed on a side of the second gallium nitride structure 1274 opposite to the first gallium nitride structure 1273. And the distance between the source opening 1044 and the first gallium nitride structure 1273 is greater than the distance between the second drain opening 1045 and the second gallium nitride structure 1274. And the passivation layer and the predetermined thickness of the barrier layer 103 are etched away while the source opening 1044 and the drain opening 1045 are etched. At the bottom of the source opening 1044 and the drain opening 1045, only the 3-5nm barrier layer 103 remains to reduce the ohmic contact resistance. While forming the source opening 1044 and the drain opening 1045, a contact opening 1046 is formed over the second gallium nitride structure 1274, i.e., on the second protrusion 136, in contact with the second gallium nitride structure 1274. And the bottom of the contact opening 1046 is in contact with the second gallium nitride structure 1274. A Ti/Al/Ti/TiN metal layer is deposited within source opening 1044, drain opening 1045, and contact opening 1046, forming source 107, drain 108, and contact electrode 1083. The source 107 is located in the source opening 1044 and extends to two sides of the source opening 1044. The drain 108 is located in the drain opening 1045 and extends to two sides of the drain opening 1045. The contact electrode 1083 is located within the contact opening 1046 and extends to both sides of the contact opening 1046. And the contact electrode 1083 is connected to the drain, and the second gallium nitride structure 1274 is connected to the drain 108 through the contact electrode 1083.

Referring to fig. 32-36, after forming the source 107, the drain 108, and the contact electrode 1083, a gate opening 1041 is formed over the first gallium nitride structure 1273. In etching the gate opening 1041, the passivation layer over the first gallium nitride structure 1273 is etched away, such that the gate opening 1041 contacts the first gallium nitride structure 1273. A TiN/Ti/Al metal layer is deposited in the gate opening 1041 to form the gate 109, and the gate 109 fills the gate opening 1041 and extends toward two sides of the gate opening 1041 and extends out of the first protrusion 135.

Referring to fig. 38-40 in combination with fig. 18-23, in one embodiment of the present invention, a plurality of layers of different electrode materials may be used, and a metal pad is formed on the electrode, so that the electrode has low contact resistance, a flat surface and good thermal stability. In the embodiment, a substrate 100, a buffer layer 101, a channel layer 102, a barrier layer 103, a gate dielectric layer 110, an isolation trench 118 formed by etching the barrier layer 103 and the gate dielectric layer 110, and a passivation layer 119 are sequentially disposed on the substrate 100. In the present embodiment, the source 107 and the drain 108 are located on two sides of the mesa structure and are respectively connected to the channel layer 102. The gate 109 is located between the source 107 and the drain 108 and close to the source 107, and the gate 109 is connected to the gate dielectric layer 110. And the source 107, the drain 108 and the gate 109 in this embodiment are disposed at the same height as the passivation layer 119.

Referring to fig. 38 to 39, in the present embodiment, the source 107 and the drain 108 are made of Ti/Al/Ti/TiN, and the gate 109 is made of TiN. Namely, the source electrode 107 and the drain electrode 108 include a first titanium metal layer 1072 in contact with the channel layer 102 and the barrier layer 103, an aluminum metal layer 1073 on the first titanium metal layer 1072, a second titanium metal layer 1074 on the aluminum metal layer 1073, and a titanium nitride layer 1075 on the first titanium metal layer 1072. In the annealing process, titanium metal on the channel layer 102 and the barrier layer 103 reacts with nitrogen atoms out-diffused by aluminum gallium nitride to form titanium nitride (TiN), the TiN has stable chemical properties, upper metal with larger work function than the TiN can be prevented from diffusing to the surface of AlGaN, and N vacancies left in the AlGaN play a role of shallow donor, so that the doping concentration of the AlGaN can be improved, and ohmic contact can be formed more easily. The aluminum metal layer 1073 covers the first titanium metal layer 1072 and serves as a catalyst to promote the reaction of Ti with N atoms, and the aluminum metal layer 1073 itself can form a stable AlN compound by bonding with N and can form an alloy having a low work function with Ti. For example, an AlTi alloy, such as TiAl, may be formed between first Ti-metal layer 1072, Al-metal layer 1073, and second Ti-metal layer 1074₃. The titanium nitride layer 1075 on the second titanium metal layer 1074 can be used as a conductive material such as an electrode and an electrical contact, and the thickness of the titanium nitride layer is, for example20nm。

Referring to fig. 38 to 40, in the present embodiment, after the source electrode 107, the drain electrode 108 and the gate electrode 109 are formed, a layer of SiO material is deposited on the passivation layer 119₂/Si₃N₄/SiO₂The composite dielectric layer 120 is passivated. After composite dielectric layer 120 is formed. A plurality of windows are formed on the source 107, the drain 108 and the gate 109 by using Inductively Coupled Plasma (ICP) or Reactive Ion Etching (RIE) equipment and by using physical bombardment plasma etching, and the windows penetrate through the composite dielectric layer 120. When the window is formed by etching the composite dielectric layer 120, the titanium nitride layer 1075 can be completely removed by using methods such as physical bombardment plasma etching and the like because the titanium nitride layer 1075 is thin, and the appearance of the window formed by etching can be ensured to be smooth enough. After forming the window, metal is deposited within the window, and on both sides of the window, to form a metal pole pad. And the metal pad includes a first metal pad 121 located above the source 107 and connected to the source 107. And a second metal pad 122 located above the drain 108 and connected to the drain 108. And a third metal pad 123 over the gate 109 and connected to the gate 109. The metal electrode pad is made of chemically stable metal. In the present embodiment, the metal electrode pad has a symmetrical "T" shape, for example.

Referring to fig. 38 to 40, in the present embodiment, the titanium nitride on the source 107 and the drain 108 is etched away when the metal pad is formed. Can avoid the formation of TiAl₃When alloyed, TiN does not take part in the reaction of the alloy, so that in TiAl₃There is a boundary between the alloy and TiN, resulting in TiAl₃And the contact resistance between the electrode and TiN is higher, so that the contact resistance of the electrode is further reduced. And a metal electrode pad is formed above the electrode, so that the contact area is larger, and the metal electrode pad has a flat surface and good thermal stability.

Referring to fig. 41 to 43, in another embodiment of the present invention, a semiconductor device having a field plate is further provided to increase the breakdown voltage of the drain region without increasing the parasitic capacitance. In the present embodiment, the semiconductor device includes a substrate 100, an epitaxial structure on the substrate 100, a plurality of electrodes connected to the epitaxial structure, and a field plate 125 disposed on the gate 109.

Referring to fig. 41, in the present embodiment, a buffer layer 101 is disposed on a substrate 100, and the material of the buffer layer 101 is, for example, aluminum nitride. A channel layer 102 is provided on the buffer layer 101, and a material of the channel layer 102 is, for example, gallium nitride. A barrier layer 103 is provided on the channel layer 102, and the material of the barrier layer 103 is, for example, aluminum gallium nitride. A gate dielectric layer 110 is disposed on the barrier layer 103, and the gate dielectric layer 110 is made of, for example, silicon nitride. In other embodiments, a layer of gallium nitride may also be deposited as a capping layer on barrier layer 103.

Referring to fig. 41-43, in the present embodiment, after forming the gate dielectric layer 110, a plurality of openings may be formed on the gate dielectric layer 110, and the gate dielectric layer 110 and the barrier layer 103 are etched away to reach the channel layer 102 during etching the openings. And to ensure that the barrier layer 103 at the opening is completely etched, a portion of the channel layer 102 may be etched away. And metal is deposited in the openings in a stacked arrangement to form source 107, drain 108 and gate 109. For example, a source opening and a drain opening may be formed on both sides of the gate dielectric layer 110, and metal Ti/Al/Ni/Au may be deposited in the source opening and the drain opening to form the source 107 and the drain 108. After forming the source 107 and drain 108, the semiconductor device is filled with N at, for example, 800-₂For example, 45 to 50s, and the temperature may be, for example, 870 ℃ and the time for the rapid heat treatment may be, for example, 50 s. Then, an opening is formed between the source electrode 107 and the drain electrode 108 by using electron beam lithography or reactive ion dry etching (RIE), and Ni/Au metal is deposited in the opening to form the gate electrode 109. In the present embodiment, a source 107, a drain 108, and a gate 109 are in contact with the channel layer 102. The source 107, the drain 108 and the gate 109 are higher than the gate dielectric layer 110 and are arranged at the same height. The top of the gate 109 extends to both sides of the opening to form the gate 109.

Referring to fig. 41 to 43, in the present embodiment, after forming the source 107, the drain 108 and the gate 109, a dielectric layer 124 is formed between the source 107 and the gate 109, between the drain 108 and the gate 109, and on top of the gate 109. The dielectric layer 124 may be formed by depositing a silicon nitride layer on the gate dielectric layer 110 between the source 107 and the gate 109, between the drain 108 and the gate 109, and on top of the gate 109, for example, by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method at a temperature of, for example, 250-300 ℃. In the present embodiment, for example, the dielectric layer 124 between the source 107 and the gate 109 and between the drain 108 and the source 107 is defined as a first dielectric layer 1241, and the dielectric layer 124 above the gate 109 is defined as a second dielectric layer 1242. The first dielectric layer 1241 is disposed at the same height as the gate 109, and the second dielectric layer 1242 is located above the gate 109 and extends to both sides of the gate 109, and covers a portion of the first dielectric layer 1241 to form an isolation structure between the formed field plate 125 and the gate 109.

Referring to fig. 41 to 43, in the present embodiment, after forming the dielectric layer 124, a groove 126 is formed between the gate 109 and the drain 108, and a metal Ni/Au is deposited on one side of the groove 126 and above the groove 126 to form a field plate 125. The field plate 125 is disposed, for example, in a "7" shape, and is adjacent to the gate 109. In the present embodiment, for convenience of description, the field plate 125 is divided into a first subfield plate 1251 and a second subfield plate 1252, and the field plate 125 in the growth direction of the semiconductor device is defined as the first subfield plate 1251, for example, and the field plate 125 in the vertical direction to the growth direction of the semiconductor device is defined as the second subfield plate 1252, for example.

Referring to fig. 41 to 43, in the present embodiment, after the dielectric layer 124 is formed, the second dielectric layer 1242 is etched toward the substrate 100 at a side close to the drain 108. And the second dielectric layer 1242, the first dielectric layer 1241 and the gate dielectric layer 110 with a predetermined thickness are etched away to form the recess 126. In this embodiment, a gate dielectric layer 110, a first dielectric layer 1241 and a second dielectric layer 1242 with a predetermined width are further disposed between the recess 126 and the gate 109 to form an isolation structure. After forming the groove 126, metal is evaporated on one side of the groove 126 and on the groove 126 to form the field plate 125. The first subfield-board 1251 is located at the side of the recess 126 remote from the isolation structure and the width of the first subfield-board 1251 is e.g. 1/2-3/5 of the width of the recess 126. In this embodiment the width of the first subfield-board 1251 is e.g. 1/2 of the width of the groove 126. The first subfield plate 1251 is disposed in a growth direction of the semiconductor device, and one end of the first subfield plate 1251 extends into the gate dielectric layer 110 and the other end extends toward the growth direction of the semiconductor device and is higher than the second dielectric layer 1242. One end of the second subfield board 1252 is connected to the other end of the first subfield board 1251 and the other end of the second subfield board 1252 extends towards the gate 109 and ends above the gate 109. Specifically, the other end of the second subfield plate 1252 is located above the central region of the gate electrode 109, for example. The second subfield-board 1252 is perpendicular to the first subfield-board 1251 and parallel to the plane in which the second dielectric layer 1242 lies. The second subfield-board 1252 has a predetermined distance from the second dielectric layer 124 because one end of the first subfield-board 1251 is higher than the second dielectric layer 1242.

Referring to fig. 41 to 43, in the present embodiment, the field plate 125 extending into the gate dielectric layer 110 is closer to the two-dimensional electron gas channel, so that the surface electric field distribution can be better adjusted and the depletion region width can be expanded. And the air bridge embedded source field plate arranged in a 7 shape enables the semiconductor device to support higher breakdown voltage. And the semiconductor device having the air bridge embedded source field plate has reduced leakage current and almost no increase in parasitic capacitance between the gate electrode 109 and the drain electrode 108, maintaining high frequency characteristics. With the help of the air bridge embedded source field plate, the semiconductor device can have a breakdown voltage of up to several hundred volts and has the ability to operate at high frequencies.

Referring to fig. 44, in an embodiment of the invention, a semiconductor device with improved breakdown performance is provided. In the present embodiment, the substrate 100 is, for example, a silicon substrate, and is, for example, made of nonpolar silicon Si (111). A buffer layer 101 is disposed on the substrate 100 and is made of, for example, gan doped with carbon, and a channel layer 102 is disposed on the buffer layer 101, for example, a non-doped gan layer. Barrier layer 103 is disposed on channel layer 102 and is, for example, a non-doped aluminum gallium nitride layer. After the barrier layer 103 is formed, mesa etching is performed on the edge of the barrier layer 103. For example, BCl can be used₃Reactive Ion Etching (RIE) of the gas to form isolation trenches outside the semiconductor device,isolation between adjacent semiconductor devices is achieved. And after the isolation groove is formed by etching, the wafer can be cleaned by using isopropanol, acetone and ultrapure water.

Referring to fig. 44, in the present embodiment, after forming the isolation trench, silicon nitride (SiNx) is deposited on the barrier layer 103 and in the isolation trench to form a gate dielectric layer 110. And gate dielectric layer 110 covers the isolation trench. After the gate dielectric layer 110 is formed, a layer of tetraethyl orthosilicate (TEOS) is deposited on the gate dielectric layer 110 to form a first passivation layer 1301. The thickness of the first passivation layer 1301 is, for example, 8-12um, specifically, 9um, 10um or 11 um. After the first passivation layer 1301 is formed, the first passivation layer 1301, the gate dielectric layer 110 and a partial thickness of the barrier layer 103 are etched on both sides near the isolation trench to form a source opening and a drain opening. Wherein the source opening and the drain opening extend into the barrier layer 103 and the barrier layer 103 at the bottom of the openings has a thickness of, for example, 3-5 nm. Ti/Al/Ti/TiN is deposited in the source and drain openings and on the first passivation layer 1301 by sputtering, and then patterned by dry etching to form the source electrode 107 and the drain electrode 108. In the present embodiment, the source 107 and the drain 108 extend to two sides of the source opening and the drain opening, respectively, to form the source 107 and the drain 108 with "T" shaped cross sections. After the source 107 and drain 108 are formed, annealing may be performed at 800-900 deg.C for 30-50 seconds in a nitrogen atmosphere to ensure good ohmic contact. After annealing, the first passivation layer 1301 is etched on the first passivation layer 1301 and on the side near the source 107, forming a gate opening. And the bottom of the gate opening contacts gate dielectric layer 110. TiN/Ti/Al is deposited in the gate opening and then patterned by dry etching to form gate 109. In the present embodiment, the gate electrode 109 extends toward both sides of the gate opening to form the gate electrode 109 having a "T" shape in cross section.

Referring to fig. 44, in the present embodiment, after the source electrode 107, the drain electrode 108 and the gate electrode 109 are formed, a layer of Tetraethylorthosilicate (TEOS) is deposited on the source electrode 107, the drain electrode 108 and the gate electrode 109 to form a second passivation layer 1302. The thickness of the second passivation layer 1302 is, for example, 2-6um, and specifically, for example, 3um or 4 um. A second passivation layer 1302 covers the source electrode 107, the drain electrode 108, and the gate electrode 109. An opening is formed in the second passivation layer 1302 and above the source 107 and the drain 108, respectively. A metal Ti/Al/Ti/TiN is deposited in the opening and on the second passivation layer 1302 to form a first field plate 131 connected to the source electrode 107 and a second field plate 132 connected to the drain electrode 108. The first field plate 131 is located in the opening on the source electrode 107 and extends toward the side of the gate 109, and a forward projection of the first field plate 131 on the first passivation layer 1301 covers the gate 109. The second field plate 132 is located in the opening on the drain electrode 108 and extends toward the side of the gate 109 with a predetermined distance from the first field plate 131.

Referring to fig. 44, in the present embodiment, after the first field plate 131 and the second field plate 132 are formed, silicon nitride (SiNx) is deposited on the first field plate 131 and the second field plate 132 to form a third passivation layer 1303, and the third passivation layer 1303 covers the first field plate 131 and the second field plate 132. And the thickness of the third passivation layer 1303 is, for example, 2-5um, specifically, 3um, for example. On the third passivation layer 1303, the first and

second windows

133 and 134 are etched. Wherein a first window 133 is disposed over the source electrode 107 and communicates with the first field plate 131. A second aperture 134 is disposed over the drain 108 and communicates with the second field plate 132. After the third passivation layer 1303 is formed, it is located at N at a temperature of, for example, 400 ℃ and 450 DEG C₂/H₂And carrying out alloy annealing treatment in the atmosphere.

Referring to fig. 44, in the present embodiment, after the third passivation layer 1303 is formed, polyimide (polyimide) is coated on the third passivation layer 1303, so as to form the protection layer 1304. The polyimide has the relative dielectric constant of 3.1-3.5, the breakdown field strength of more than 200KV/mm, good mechanical properties, good adhesion, corrosion resistance, high temperature resistance, irradiation resistance and better planarization performance. Meanwhile, the passivation layer formed by the silicon nitride and the polyimide can bear mechanical stress caused by the filler during plastic packaging, and the passivation layer is prevented from cracking and metal deformation.

Referring to fig. 44, in the present embodiment, a layer of polyimide may be coated on the third passivation layer 1303 by using dynamic spin coating. After the photoresist is applied, the passivation layer 1304 may be exposed and developed to form a patterned passivation layer 1304. For example, ultraviolet light, deep ultraviolet light, or an electron beam may be selected to expose and remove the polyimide on the first window 133 and the second window 134, and an oil solution is used to dissolve the polyimide in the unexposed area, thereby forming the patterned protection layer 1304. In the present embodiment, the protective layer 1304 exposes the first window 133 and the second window 134. After the patterned protective layer 1304 is formed, the protective layer 1304 is post-baked to improve the adhesion of the polyimide. The baking temperature is 50-800 deg.C, and the baking time is 30s-1 h. After post-baking, the protective layer 1304 is cured, so that the surface density of the protective layer 1304 can be improved, and defects can be avoided or reduced. The curing process is a heating curing process, and the temperature of the heating curing process is, for example, 100 ℃ to 150 ℃, and the time is, for example, 30 to 100 seconds. The density of the solidified protective layer 1304 is high, and the traps on the surface of the passivation layer are passivated by the protective layer 1304, so that the situation that the field plate has more traps and charges on the surface or in the body of a medium, and a local high electric field is generated at the edge of the metal field plate to generate high-energy carriers to cause an avalanche effect, and further the whole semiconductor device is broken down, can be avoided.

Referring to fig. 45 to 58, in an embodiment of the present invention, a semiconductor device is further provided, which can suppress leakage current and improve quality of the semiconductor device. Specifically, referring to fig. 45 to 49, in the present embodiment, an aluminum nitride buffer layer 101 is disposed on a silicon substrate 100, a gallium nitride channel layer 102 is disposed on the aluminum nitride buffer layer 101, a barrier layer 103 is disposed on the channel layer 102, and the barrier layer 103 is made of, for example, aluminum gallium nitride. A gallium nitride layer 127 is deposited on barrier layer 103 and gallium nitride layer 127 is etched to form patterned gallium nitride layer 127. Wherein the patterned gan structure is, for example, annular gan layers 127 to form the drain 108 between the annular gan layers 127. After patterned gallium nitride layer 127 is formed, a silicon nitride layer is deposited on gallium nitride layer 127, forming first passivation layer 1301. A source opening 1043 and a drain opening 1044 are etched in the first passivation layer 1301, wherein the source opening 1043 is located on one side of the annular gallium nitride layer 127, and the drain opening 1044 is located in the annular gallium nitride layer 127. And while etching the source opening 1043 and the drain opening 1044, the first passivation layer 1301 and the barrier layer 103 are etched away such that the bottom of the source opening 1043 and the drain opening 1044 are in contact with the channel layer 102. A Ti/Al/Ti/TiN metal layer is deposited within source opening 1043 and drain opening 1044 to form source 107 and drain 108, with drain 108 centered on annular gallium nitride layer 127.

Referring to fig. 49 to 54, in the present embodiment, after the source 107 and the drain 108 are formed, silicon nitride (SiN) is deposited on the source 107, the drain 108 and the first passivation layer 1301 to form a first insulating layer 1371. Over the gan layer 127, the first insulating layer 1371 is etched to form a gate 109 opening. In etching the gate 109 opening, the first insulating layer 1371 and the first passivation layer 1301 above the gallium nitride layer 127 are etched away, so that the gate 109 opening is in contact with the gallium nitride layer 127. A metal layer of TiN/Ti/Al is deposited within the gate 109 opening to form gate 109. The gate 109 fills the opening of the gate 109, extends outward of the gan ring, and covers a portion of the first insulating layer 1371. After forming the gate 109, silicon oxide (SiO) is deposited over the gate 109 and the first insulating layer 1371₂) A second insulating layer 1372 is formed. Titanium nitride (TiN) is deposited on the second insulating layer 1372 to form a first field plate 1381, and the first field plate 1381 covers a portion of the gate 109 except on the gallium nitride.

Referring to fig. 55 to 57, in the present embodiment, after forming the first field plate 1381, silicon oxide (SiO) is deposited on the first field plate 1381 and on the second insulating layer 1372₂) And the silicon oxide layer is subjected to Chemical Mechanical Polishing (CMP) to form a flat third insulating layer 1373. An opening is etched through the third, second and first insulating

layers

1373, 1372 and 1371 above the drain 108 and source 107, and tungsten is deposited in the opening to form drain conductive plug 1391 and source conductive plug 1392. And metallic aluminum is deposited on drain conductive plug 1391, source conductive plug 1392, and third insulating layer 1373 between drain conductive plug 1391 and source conductive plug 1392 to form a second field plate. And the second field plate comprises a first sub-field plate 1383 connected to the drain conductive plug 1391, a second sub-field plate 1384 connected to the source conductive plug 1392, and a plurality of

sub-field plates

1383 and 1384 disposed on the first sub-field plate and the second sub-field plateThird subfield-plate 1385 between plates 1384 and third subfield-plate 1385 covers first field plate 1381 between source 107 and drain 108.

Referring to fig. 57 to 58, in the present embodiment, after the second field plate is formed, a layer of silicon nitride (SiNx) is deposited on the second field plate and the third insulating layer 1373 to form the second passivation layer 1302. And an opening is etched through second passivation layer 1302 and metal tungsten is deposited in the opening over second sub-field plate 1384 and third sub-field plate 1385 to form first conductive plug 1394 connected to second sub-field plate 1384 and second conductive plug 1395 connected to third sub-field plate 1385. And metallic aluminum is deposited on the second passivation layer 1302 to form a third field plate. And the third field plate comprises a fourth sub-field plate 1386 and a fifth sub-field plate 1387, wherein the fourth sub-field plate 1386 is on and connected to the first conductive plug 1394 and the fifth sub-field plate 1387 is on and connected to the second conductive plug 1395. Finally, a layer of polyimide (polyimide) is deposited over the first and second

conductive plugs

1394 and 1395 and the second passivation layer 1302 to form a protective layer 1303.

Referring to fig. 59 to 64, in an embodiment of the present application, the present disclosure provides a semiconductor device and a method for manufacturing the same, wherein the semiconductor device is a monolithically integrated semiconductor device including a first device and a second device. The first device is a P-type field effect transistor, and the second device is an N-type field effect transistor. The first device includes an epitaxial structure and a first source 1071, a first drain 1081, an oxide layer 106 on the first source 1071 and the first drain 1081, and a first gate 1091 on the oxide layer 106 formed thereon. The second device includes an epitaxial structure and a second source 1072, a second drain 1082, and a second gate 1092 formed thereon. In the present embodiment, the epitaxial structure includes a substrate 100, a buffer layer 101, a channel layer 102, a barrier layer 103, and a plurality of gallium nitride layers. In which a buffer layer 101 is formed on a substrate 100, a channel layer 102 is formed on the buffer layer 101, and a barrier layer 103 is formed on the channel layer 102. In this embodiment, for example, 3 gallium nitride layers are included.

Referring to fig. 59, in the present embodiment, a substrate 100 is, for example, a silicon substrate. An aluminum nitride film is sputtered on the substrate 100 to form a buffer layer 101. After the aluminum nitride layer is formed, the formed buffer layer 101 may be subjected to a high temperature annealing process to improve the quality of the buffer layer 101. The buffer layer 101 is disposed between the substrate 100 and the channel layer 102, and may prevent silicon in the substrate 100 from reacting with gallium in the channel layer 102.

Referring to fig. 59, in the present embodiment, the channel layer 102 is a gallium nitride layer, and gallium nitride may be grown on the buffer layer 101 by a chemical vapor deposition method or a metal organic chemical vapor deposition method. Firstly, in a reaction chamber of a device for growing gallium nitride, for example, one or more of helium, argon, nitrogen and hydrogen are introduced into the reaction chamber, then the temperature of the reaction chamber is raised to a preset temperature, wherein the preset temperature is the growth temperature of the gallium nitride layer, and the gallium nitride layer with a preset thickness, i.e., the channel layer 102, is grown under the condition.

Referring again to fig. 59, in the present embodiment, the epitaxial structure provides a source of hole carriers from the top unintentionally doped gan, two-dimensional hole gas induced polarization at the algan heterostructure interface. The barrier layer 103 may be formed on the channel layer 102 using, for example, a low temperature chemical vapor deposition method such as Plasma Enhanced Chemical Vapor Deposition (PECVD). A first gallium nitride layer 141, a second gallium nitride layer 142, and a third gallium nitride layer 143 are formed in this order on the barrier layer 103. The first gallium nitride layer 141 is an unintentionally doped gallium nitride layer for separating the P-type gallium nitride layer from the barrier layer, which can increase mobility of holes, and the thickness of the first gallium nitride layer 141 may be, for example, 15 to 25nm, and specifically, 20 nm. The second gallium nitride layer 142 is a doped P-type gallium nitride layer. The third gan layer 143 is a heavily doped P-type gan layer, which can form a good ohmic contact with the top electrode. In the present embodiment, the dopant source of P doping is magnesium (Mg), which has higher activation energy as an acceptor doping, and thus has lower hole mobility in P-type gan material. Wherein the doping concentration of magnesium ions in the second gallium nitride layer 142 is, for example, 1e19cm^-3-2e19cm^-3The doping concentration of magnesium ions in the third gallium nitride layer 143 is, for example, 5e19cm^-3-6e19cm^-3. Gallium nitride and aluminum gallium nitride heterostructures may generate two-dimensional hole gas, in this embodiment, a two-dimensional electron gas layer of negative polarity is generated in the barrier layer 103 and near the channel layer 102, while a two-dimensional electron gas layer of positive polarity is generated in the first gallium nitride layer 141 and near the channel layer 102.

Referring to fig. 60, in the present embodiment, after forming the epitaxial structure, a metal Ni/Au/Ni is deposited on one side of the epitaxial structure by electron beam evaporation to form a first source 1071 and a first drain 1081. Specifically, the first source electrode 1071 and the first drain electrode 1081 are disposed on the third gallium nitride layer 143, and a predetermined distance is formed between the first source electrode 1071 and the first drain electrode 1081, so as to form the recess 144. In the present embodiment, the first source electrode 1071 and the first drain electrode 1081 include a plurality of metal layers, for example, a first metal layer, a second metal layer and a third metal layer sequentially disposed, where the first metal layer is, for example, a Ni metal layer, the second metal layer is, for example, an Au metal layer, and the third metal layer is a Ni metal layer.

Referring to fig. 61, in the present embodiment, after the first source electrode 1071 and the first drain electrode 1081 are formed, the P-type gan layer at the bottom of the recess 144 may be removed by using an etching technique such as Inductively Coupled Plasma (ICP) or Reactive Ion Etching (RIE). Specifically, the removed P-type gallium nitride layer includes the third gallium nitride layer 143 and the second gallium nitride layer 142 at the bottom of the recess 144, and at this time, the bottom of the recess 144 stays on the surface of the first gallium nitride layer 141.

Referring to FIG. 62, in some embodiments, chlorine gas (Cl) is used₂) Or boron chloride (BCl)₃) Mesa etching is performed on the epitaxial structure to form an isolation trench 146 at a side of the first source 1071 away from the recess 144 and at a side of the first drain 1081 away from the recess 144. The isolation trench 146 may be used to connect adjacent semiconductor devices, and the isolation trench 146 passes through the electrode, the third gallium nitride layer 143, the second gallium nitride layer 142, the first gallium nitride layer 141, the barrier layer 103, and a portion of the channel layer102 at a predetermined distance from the buffer layer 101.

Referring to fig. 63, in the present embodiment, after forming the isolation trench 146, for example, an Atomic Layer Deposition (ALD) technique is used to deposit aluminum oxide on the bottom wall and the sidewall of the recess 144 and above the first source 1071 and the first drain 1081, so as to form the oxide layer 106. And Ni/Au is deposited on the oxide layer 106 as a first gate 1091 to form the first device. And the first gate 1091 covers part of the oxide layer 106, including the oxide layer 106 on the bottom wall and the sidewall of the recess 144, and the oxide layer 106 on the side close to the recess above the first source 1071 and the first drain 1081, and the part of the oxide layer 106 far from the recess 144 above the first source 1071 and the first drain 1081 is not covered. The first gate 1091 includes a plurality of metal layers, such as a nickel metal layer 1101 and an Au metal layer 1102 disposed on the Ni metal layer 1101 in this embodiment.

Referring to fig. 64, in other embodiments, the second device may be formed simultaneously with the formation of the first device to form a monolithically integrated semiconductor device. In the present embodiment, the epitaxial structures of the first device and the second device are the same, and the second device is isolated from the first device by the isolation trench 146. Specifically, when the mesa etching is performed during the fabrication of the first device, the epitaxial structure may be etched twice in the region where the second device is formed. In the first etching process, mesa etching is performed around the second gate 1092 and with the position of the second gate 1092 as the center. The mesa structure 145 and the second gate 1092 are formed with a first predetermined distance H1, and the third gallium nitride layer 143, the second gallium nitride layer 142, the first gallium nitride layer 141, and the barrier layer 103 outside the second gate 1092 are etched away during the first etching. After the first etching is finished, the second etching is performed. The second etching is centered on the mesa structure 145 formed by the first etching, and is located at two sides of the mesa structure 145 formed by the first etching, and has a first predetermined distance H2(H2> H1) from the second gate 1092 to the isolation trench 146. The barrier layer 103 is etched away to the channel layer 102 again to form a step with the mesa structure 145 formed by the first etching. In the embodiment, steps are formed on two sides of the mesa structure 145 formed by the first etching. After the second etching is completed, Ni/Au is deposited as a second gate 1092 on the mesa structure 145 formed for the first time and in the center of the mesa structure 145. And respectively depositing Ti/AL/Ni/Au on the two symmetrical steps to form a second source electrode 1072 and a second drain electrode 1082. In the present embodiment, the formation order and the specific deposition process of the second gate 1092, the second source 1072, and the second drain 1082 are not limited. For example, the second source electrode 1072 and the second drain electrode 1082 may be formed after the first source electrode 1071 and the first drain electrode 1081 are formed, and the second gate electrode 1092 may be formed after the first gate electrode 1091 is formed.

Referring to fig. 65 to 77, in another embodiment of the present invention, a monolithically integrated semiconductor device is further provided, wherein the semiconductor device includes a first device and a second device, and forms a power switching system. In this embodiment, the first device is, for example, a metal-oxide semiconductor field effect transistor (MOSFET) and is a silicon-based control device, and the second device is, for example, a High Electron Mobility Transistor (HEMT) and is a power device. In this embodiment, when the two devices are located on different substrates 100, the switches of the system are susceptible to the influence of parasitic capacitance, and the silicon-based control device and the gallium nitride power device are integrated in the present application, so that the junction parasitic phenomenon can be effectively suppressed.

Referring to fig. 65, in the present embodiment, a silicon substrate 100 is provided, and the substrate 100 is etched to form a bump 1003, wherein two sides of the bump 1003 are a platform with a height lower than that of the bump 1003. Where the mesa 1003 is used to form a first device, e.g., defined as a first region 1001, and the mesa on one side of the mesa 1003 is used to form a second device and isolation structure, e.g., defined as a second region 1002.

Referring to fig. 65, in the present embodiment, after the substrate 100 is etched, an isolation layer 147 is deposited on the substrate 100. The material of the isolation layer 147 is, for example, silicon oxide (SiO)₂). Wherein the thickness of the isolation layer 147 on the first region 1001 is less than the thickness of the isolation layer 147 on the second region 1002. In the present embodiment, the thickness of the isolation layer 147 on the first region 1001 is, for example, 18 to 30nm, specifically, 20nm, for exampleAnd forming a gate dielectric layer of the first device. The height of the isolation layer 147 on the second region 1002 is greater than the height of the isolation layer 147 on the first region 1001, and the thickness of the isolation layer 147 on the second region 1002 is, for example, 1.0-1.5um, for forming an isolation structure between the first device and the second device.

Referring to fig. 65-66, in the present embodiment, after forming the isolation layer 147, a polysilicon layer 148 is deposited on the isolation layer 147, and a mask layer 149 is deposited on the multi-pass layer. The material of the mask layer 149 is, for example, silicon oxide (SiO)₂) And the thickness of the mask layer 149 is, for example, 1-1.8um, specifically, 1.5 um. Wherein polysilicon layer 148 is used to form the gate of the first device. The isolation layer 147 serves as a mask for epitaxial growth in the second device.

Referring to fig. 66-69, in the present embodiment, after forming the polysilicon layer 148 and the mask layer 149, silicon nitride (SiN) is deposited on the mask layer 149₃) The protective layer 150 is formed, the concave portion 151 is formed in the second region 1002 using the protective layer 150 as a mask, and after the concave portion 151 is formed, phosphoric acid (H) is used, for example₃PO₄) The protective layer 150 is removed. In this embodiment, after the protective layer 150 is formed, the protective layer 150, the mask layer 149, the polysilicon layer 148, the isolation layer 147 and the substrate 100 with a predetermined thickness are etched away in sequence on the protective layer 150 in the second region 1002 by, for example, dry etching, so as to form the recess 151. Wherein the recess 151 is formed to have a predetermined distance from the mesa 1003 to retain the isolation layer 147 between the recess 151 and the mesa 1003, and the isolation layer 147 between the recess 151 and the mesa 1003 may form a trench isolation structure between the first device and the second device. After the formation of the recess 151, the surface of the etched region may be smoothed to ensure the quality of the formed second device.

Referring to fig. 70, in the present embodiment, after the recess 151 is formed, the channel layer 102, the barrier layer 103 and the gate dielectric layer 152 of the second device are sequentially formed in the recess 151 by using the isolation layer 147 as a mask. A layer of gallium nitride is deposited in recess 151, for example, using Metal Organic Chemical Vapor Deposition (MOCVD), to form channel layer 102, and channel layer 102 is flush with the surface of substrate 100 in second region 1002. After forming the channel layer 102, a layer of aluminum gallium nitride is deposited on the surface of the channel layer 102 by using, for example, MOCVD, to form the barrier layer 103, and the barrier layer 103 is flush with the spacer layer 147. After the barrier layer 103 is formed, a layer of silicon nitride (SiN) is deposited on the barrier layer 103 as a gate dielectric layer 152 for the second device. The thickness of the gate dielectric layer 152 is, for example, 20-30 nm. After the gate dielectric layer 152 is formed, the isolation layer 147 is removed.

Referring to fig. 70 to 71, in the present embodiment, after the isolation layer 147 is removed, the polysilicon layer 148 is etched to form a first gate 1091. And the substrate 100 on both sides of the first gate 1091 is doped to form source and drain regions 156 of the first device. The first gate 1091 is disposed on the bump 1003 and located on a side away from the second device. The source region in this embodiment is disposed within the mesa 1003 and on a side of the first gate 1091 opposite the second device. The source region provided in this embodiment includes a P-type lightly doped region 155, a P-type heavily doped region 153 disposed on the P-type lightly doped region 155, and an N-type heavily doped region 154. The P-type heavily doped region 153 and the N-type heavily doped region 154 are flush with the interface of the mesa 1003, the P-type heavily doped region 153 and the N-type heavily doped region 154 are disposed side by side in depth, the N-type heavily doped region 154 is adjacent to the first gate 1091, and the P-type heavily doped region 153 is located on the side of the N-type heavily doped region 154 opposite to the first gate 1091. The doping depth of the P-type lightly doped region 155 is greater than the doping depths of the P-type heavily doped region 153 and the N-type heavily doped region 154, and the P-type lightly doped region 155 covers the P-type heavily doped region 153 and the N-type heavily doped region 154. The P-type lightly doped region 155 extends horizontally to below the first gate 1091 and partially overlaps the first gate 1091. The drain region 156 provided in this embodiment includes an N-type heavily doped region, the drain region 156 is disposed between the first gate 1091 and the second device, and the drain region 156 has a predetermined distance from the first gate 1091. And the doping depth of the drain region 156 is greater than the doping depths of the P-type heavily doped region 153 and the N-type heavily doped region 154 in the source region and less than the doping depth of the P-type lightly doped region 155 in the source region. In the present embodiment, the P-type dopant source is, for example, boron ion or boron fluoride ion (BF)₂) The N-type dopant source is, for example, phosphorous ions.

Referring to FIG. 71, in the present embodiment, a first gate 1091 is formed,After the source and drain regions 156, a passivation layer 157 is formed on the first gate 1091, the isolation layer 147, and the isolation structure between the first and second devices. For example, a layer of silicon oxide (SiO) may be deposited using Plasma Enhanced Chemical Vapor Deposition (PECVD)₂) To form a passivation layer 157. In some embodiments, after the passivation layer 157 is formed, an anneal may be performed to activate the dopants.

Referring to fig. 71 to 73, in the present embodiment, after the passivation layer 157 is formed, an opening 158 is formed in each of the second region 1002 at a side close to the first device and a side far from the first device. For example, the gate dielectric layer 152 and barrier layer 103 of the second device at the location where the opening 158 is desired are etched away to bring the opening 158 into contact with the channel layer 102. After the openings 158 are formed, the metal Ti/Al/Ni/Au is deposited within the two openings 158 to form the second source 1072 and the second drain 1082 of the second device. Where the second source 1072 is for example the second device near the first device and the second drain 1082 is for example the second device far from the first device.

Referring to fig. 74 to 75, in the present embodiment, after the second source electrode 1072 and the second drain electrode 1082 are formed, an opening 159 communicating with the source region and the drain region 156 is respectively opened on the passivation layer 157 and at both sides of the first gate 1091, and the opening 159 penetrates through the passivation layer 157 and the isolation layer 147. Aluminum metal is deposited in the opening 159 to form a first source 1071 and a first drain 1081. Wherein the first source 1071 contacts the source region and the first drain 1081 contacts the drain region.

Referring to fig. 76 to 77, in the present embodiment, after the first source electrode 1071 and the first drain electrode 1081 are formed, Ni/Au metal is deposited on the gate dielectric layer 152 to form a second gate electrode 1092. Wherein the second gate 1092 is adjacent to the drain side of the second device. Namely, the first device and the second device are manufactured. And after the first device and the second device are manufactured, at least one metal layer may be formed on the first device and the second device to connect the first device and the second device, so as to form the power switching system as shown in fig. 77. The number of metal layers is not limited, and the first device and the second device may be electrically connected as shown in fig. 77.

Referring to fig. 78 to 88, in another embodiment of the present invention, a monolithically integrated semiconductor device is further provided, wherein the semiconductor device includes a first device and a second device forming a half-bridge circuit. Wherein the first device and the second device are High Electron Mobility Transistors (HEMTs), and one HEMT is connected with a high level and the other HEMT is connected with a low level. The semiconductor device provided by the embodiment can prevent the occurrence of the back gate effect when the half-bridge circuit operates, and suppress the generation of the parasitic inductance.

Referring to fig. 81, in the present embodiment, a substrate is provided, and the substrate includes silicon layers with different polarities and a buried layer 160 disposed in the silicon layers. A particular substrate includes a first silicon layer 1004, a buried layer 160 disposed on the first silicon layer 1004, and a second silicon layer 1005 disposed on the buried layer 160. The first silicon layer 1004 is polar silicon Si (100), and the thickness of the first silicon layer 1004 is, for example, 1-1.1mm, specifically, 1 mm. The buried layer 160 is disposed on the first silicon layer 1004, and a material of the buried layer 160 is, for example, silicon oxide (SiO)₂) The thickness of the buried layer 160 is, for example, 1 to 1.1um, specifically, 1um, for example. The second silicon layer 1005 is disposed on the buried layer 160, and the second silicon layer 1005 is non-polar silicon Si (111), and the thickness of the second silicon layer 1005 is, for example, 1.5-1.6um, specifically, 1.5um, for example. After the substrate is formed, the substrate may be cleaned.

Referring to fig. 81, in the present embodiment, the buffer layer 161 is disposed on gan, the material of the buffer layer 161 is gan, and the thickness of the buffer layer 161 is 4000-. The channel layer 102 is disposed on the buffer layer 161, and the material of the channel layer 102 is, for example, gallium nitride. The thickness of the channel layer 102 is, for example, 400-450nm, and specifically, 420 nm. A barrier layer 103 is provided on the channel layer 102, and the material of the barrier layer 103 is, for example, aluminum gallium nitride. The thickness of the barrier layer 103 is, for example, 20 to 25nm, specifically, 24.7 nm. On the barrier layer 103, a cap layer 162 may be further disposed, and the material of the cap layer 162 is, for example, gallium nitride. The thickness of the cap layer 162 is, for example, 3 to 5nm, specifically, 3.2 nm.

Please refer toReferring to fig. 82, in the present embodiment, after forming the cap layer 162, isolation trenches 163 are etched in the epitaxial layer. An isolation trench 163 extends into the substrate and through the second silicon layer 1005 and a portion of the buried layer 160 to isolate the first device from the second device. For example, Cl can be used₂Or BCl₃And the cap layer 162, the barrier layer 103, the channel layer 102, the buffer layer 161, the second silicon layer 1005 and the buried layer 160 of a predetermined thickness are etched using Inductively Coupled Plasma (ICP) and stopped in the buried layer 160, thereby forming the isolation trench 163. In the present embodiment, the isolation trench 163 is disposed between the first device and the second device, and the isolation trench 163 extends into the buried layer 160 in the substrate, which can effectively isolate the substrates of the first device and the second device, prevent the back gate effect, and suppress the generation of parasitic inductance.

Referring to fig. 83 to 84, in the present embodiment, after the isolation trench 163 is formed, a gate opening is formed on two sides of the isolation trench 163 by etching. In subsequent steps, metal is deposited in the gate opening to form a gate. In this embodiment, the cap layer 162 at the gate position and the barrier layer 103 with a predetermined thickness may be dry etched to form the gate opening. The barrier layer 103 may remain 2-3nm thick at the bottom of the gate to form an enhancement mode device. In the present embodiment, the gate openings include, for example, a first gate opening 165 located at one side of the isolation trench 163 and a second gate opening 164 located at the other side of the isolation trench 163. And the first gate opening 165 at one side of the isolation trench 163 is located away from the isolation trench 163 and the second gate opening 164 at the other side of the isolation trench 163 is located close to the isolation trench 163. After the gate opening is formed, a passivation layer 166 is formed on the isolation trench 163, the gate opening, and the cap layer 162. And a layer of silicon nitride (Si) may be deposited on the isolation trench 163 and the cap layer 162, for example, by Low Pressure Chemical Vapor Deposition (LPCVD)₃N₄) A passivation layer 166 is formed.

Referring to fig. 85 to 86, in the present embodiment, after the passivation layer 166 is formed, tetraethyl silicate (PETEOS) is deposited on the passivation layer 166 as the protection layer 167. The passivation layer 167 fills the gate opening and is laid over the passivation layer 166. After forming the protection layer 167, a source opening and a drain opening are formed on both sides of the isolation trench 163 and on both sides of the gate opening by Reactive Ion Etching (RIE) and Inductively Coupled Plasma (ICP) etching, respectively. For example, a first source opening 168 and a first drain opening 169 are formed at one side of the isolation trench 163 and at both sides of the first gate opening 165, respectively. The first source opening 168 is located on a side of the first gate opening 165 away from the isolation trench 163, the first drain opening 169 is located between the first gate opening 165 and the isolation trench 163, and the distance between the first source opening 168 and the first gate opening 165 is much smaller than the distance between the first drain opening 169 and the first gate opening 165. A second source opening 170 and a second drain opening 171 are formed on the other side of the isolation trench 163 and on both sides of the second gate opening 164, respectively. The second drain opening 171 is located on a side of the second gate opening 164 away from the isolation trench 163, the second source opening 170 is located between the second gate opening 164 and the isolation trench 163, and a distance between the second source opening 170 and the second gate opening 164 is much smaller than a distance between the second drain opening 171 and the second gate opening 164.

Referring to fig. 86-88, in the present embodiment, after forming the electrode opening, a Ti/Al/Ti/TiN multilayer metal is magnetron sputtered in the source opening and the drain opening, and source and drain patterned lift-off and rapid thermal annealing are performed. Depositing metal in the first source opening 168 and over the first source opening 168 forms a first source 1071, depositing metal in the first drain opening 169 and over the first drain opening 169 forms a first drain 1081, depositing metal in the second source opening 170 and over the second source opening 170 forms a second source 1072, and depositing metal in the second drain opening 171 and over the second drain opening 171 forms a second drain 1082. After the source and drain are formed, for example, Reactive Ion Etching (RIE) is used to remove the protective layer 167 in the first gate opening 165 and the second gate opening 164, and TiN/Ti/Al multilayer metal is sputtered in the first gate opening 165 and the second gate opening 164 under magnetron sputtering, and then gate patterning stripping is performed to form a first gate 1091 and a second gate 1092, thereby forming a first device and a second device. In this embodiment, the first source 1071, the first gate 1091, the first drain 1081, the second source 1072, the second gate 1092 and the second drain 1082 are higher than the opening where the first source 1071, the first gate 1091, the second drain 1082 are located, and extend to two sides of the opening to form an electrode with a T-shaped structure. The passivation layer 166 and the T-shaped electrodes can further improve the withstand voltage of the enhanced GaN HEMT device, and the half-bridge circuit monolithic integration with good performance is realized.

Referring to fig. 89, in other embodiments, to avoid substrate bias effects of the integrated device, a buried oxide layer is disposed in the substrate. The present application may also provide an epitaxial structure with a superlattice buffer layer to avoid the substrate bias effect of the integrated device, and the buffer layer 101 with the superlattice structure 1013 may reduce on-resistance and suppress current collapse to reduce resistance, optimize a high quality buffer layer, and increase breakdown voltage.

Specifically, referring to fig. 89, in the present embodiment, the substrate 100 is, for example, a silicon substrate, the buffer layer 101 is disposed on the substrate 100, and the buffer layer 101 includes an aluminum nitride layer 1011, an aluminum gallium nitride layer 1012 disposed on the aluminum nitride layer 1011, and a superlattice structure 1013 disposed on the aluminum gallium nitride layer 1012. The thickness of the aluminum nitride layer 1011 is, for example, 100-120nm, and specifically, is, for example, 110nm, 115nm or 120 nm. The aluminum gallium nitride layer 1012 is disposed on the aluminum nitride layer 1011, and the thickness of the aluminum gallium nitride layer 1012 is, for example, 250-320nm, and specifically, 300 nm. The superlattice structure 1013 is disposed on the aluminum gallium nitride layer 1012, and the superlattice structure 1013 is, for example, a repeatedly stacked aluminum nitride layer and a gallium nitride layer. The thickness of the superlattice structure 1013 is, for example, 2400-2600nm, and specifically 2500nm, for example. The thickness of the aluminum nitride layer and the gallium nitride layer in the superlattice structure 1013 is not limited in this embodiment, and the aluminum nitride layer and the gallium nitride layer in the superlattice structure 1013 may have smaller thicknesses according to the process. On the superlattice structure 1013, the channel layer 102 is provided. In the present embodiment, the channel layer 102 is, for example, a gallium nitride layer of 1.2-1.8um, and the specific thickness of the channel layer 102 is, for example, 1.5 um. On the channel layer 102, a barrier layer 103 is provided, and in the present embodiment, the thickness of the barrier layer 103 is, for example, 20 to 30nm, specifically, 25nm, for example. A plurality of electrodes may be formed with the epitaxial structure provided in this embodiment to form a semiconductor device. The epitaxial structure provided by the embodiment uses the semiconductor device described in the present application, and the buffer layer having the superlattice structure 1013 in the epitaxial structure has a vertical isolation effect, so that the performance of the semiconductor device can be optimized. The buffer layer with the superlattice structure 1013 may improve voltage blocking capability, and the vertical isolation may also significantly reduce substrate bias effects. In addition, the vertical substrate leakage current is well suppressed at higher positive substrate bias voltages.

Referring to fig. 1 to 89, the epitaxial structure and the semiconductor device formed by the epitaxial structure provided in the present invention can be applied to various semiconductor structures, electronic components or electronic devices, such as a switch device, a power device, a radio frequency device, a light emitting diode, a micro light emitting diode, a display panel, a mobile phone, a watch, a notebook computer, a projection device, a charging pile, a Virtual Reality (VR) device, an Augmented Reality (AR) device, a portable electronic device, a game machine or other electronic devices.

The embodiments of the invention disclosed above are intended merely to aid in the explanation of the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor device, characterized in that it comprises at least:

a substrate;

a channel layer disposed on the substrate;

a barrier layer disposed on the channel layer;

a gate disposed on the barrier layer and between the source and the drain; and

2. The semiconductor device according to claim 1, wherein a material of the passivation layer is aluminum nitride.

3. The semiconductor device according to claim 1, wherein a material of the oxide layer is aluminum oxide.

4. The semiconductor device of claim 1, wherein the gate extends into the barrier layer a predetermined distance from a bottom of the barrier layer.

5. The semiconductor device of claim 1, wherein the barrier layer is a 3-6um gallium nitride layer, a 20-30nm aluminum gallium nitride layer.

6. The semiconductor device according to claim 1, wherein a material of the barrier layer is Al_0.23Ga_0.77N。

7. The semiconductor device of claim 1, wherein the gate comprises:

a titanium metal layer;

an aluminum metal layer disposed on the titanium metal layer;

a nickel metal layer disposed on the aluminum metal layer; and

and the gold metal layer is arranged on the nickel metal layer.

8. The semiconductor device of claim 1, wherein the gate is spaced from the source by a distance of 2-3 um.

9. The semiconductor device of claim 1, wherein the gate is spaced from the drain by a distance of 14-15 um.

10. An electronic device characterized by comprising the semiconductor device according to claim 1.