CN117438457B - Groove gate type GaN-based HEMT device and preparation method thereof - Google Patents

Groove gate type GaN-based HEMT device and preparation method thereof Download PDF

Info

Publication number
CN117438457B
CN117438457B CN202311725665.4A CN202311725665A CN117438457B CN 117438457 B CN117438457 B CN 117438457B CN 202311725665 A CN202311725665 A CN 202311725665A CN 117438457 B CN117438457 B CN 117438457B
Authority
CN
China
Prior art keywords
layer
barrier layer
algan
gan
ultrathin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202311725665.4A
Other languages
Chinese (zh)
Other versions
CN117438457A (en
Inventor
邹鹏辉
王文博
马飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhejiang Jimaike Microelectronics Co Ltd
Original Assignee
Zhejiang Jimaike Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhejiang Jimaike Microelectronics Co Ltd filed Critical Zhejiang Jimaike Microelectronics Co Ltd
Priority to CN202311725665.4A priority Critical patent/CN117438457B/en
Publication of CN117438457A publication Critical patent/CN117438457A/en
Application granted granted Critical
Publication of CN117438457B publication Critical patent/CN117438457B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/207Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Abstract

The invention provides a groove gate type GaN-based HEMT device and a preparation method thereof, the groove gate type GaN-based HEMT device comprises a substrate, an epitaxial lamination, a groove gate structure, a metal source electrode and a metal drain electrode, wherein the epitaxial lamination comprises a GaN channel layer and a barrier layer which are sequentially overlapped from bottom to top, and the groove gate structure comprises a GaN layer, an AlGaN layer with gradually changed Al component and a metal gate which are sequentially overlapped from bottom to top; the metal source and the metal drain are respectively arranged in openings penetrating through the barrier layer and reaching the GaN channel layer. The invention utilizes the local Al component graded AlGaN layer to generate high-concentration holes, and realizes the enhancement type GaN-based HEMT device for the depletion of the two-dimensional electronic device under the grid, and compared with P-type GaN, the Al component graded AlGaN layer has larger forbidden bandwidth, can effectively improve the grid leakage, improve the breakdown voltage and improve the reliability of the device.

Description

Groove gate type GaN-based HEMT device and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a groove gate type GaN-based HEMT device and a preparation method thereof.
Background
Most of the III-group nitrides have the excellent properties of large forbidden bandwidth, high electron saturation drift speed, good thermal stability and chemical stability, radiation resistance and the like, wherein hetero-junctions such as AlGaN/GaN, inAlN/GaN and the like have high-density and high-mobility two-dimensional electron gas (2 DEG) at a hetero-junction interface because of spontaneous polarization and piezoelectric polarization effects of the III-group nitrides, so that the III-group nitrides are very suitable for being applied to high-frequency high-power scenes. But conventional AlGaN/GaN heterojunction based High Electron Mobility Transistors (HEMTs) are in a normally-on state, i.e., depletion mode, due to the high concentration of 2DEG that naturally occurs when no gate voltage is applied to the AlGaN/GaN heterojunction.
For power device application design, transistors are required to be in a normally off state, i.e., enhancement mode devices, for safety and energy conservation considerations. The current common scheme for realizing the enhanced HEMT is as follows: a groove gate structure, a fluorine (F) ion implantation under the gate, a cascade structure and a P-GaN gate; the P-GaN gate HEMT is a structure commonly used in the industry at present because of a large threshold voltage. The P-GaN gate can realize the depletion of the 2DEG by lifting AlGaN/GaN under the gate, wherein the doping concentration of the P-GaN gate is higher due to the activation energy of Mg, the higher hole concentration is difficult to obtain, and the diffusion of Mg impurities into the channel layer can also bring about the reduction of the two-dimensional electron gas mobility. In addition, the P-GaN gate structure needs to etch away part of the P-GaN layer to expose the AlGaN barrier layer, and how to accurately control the etching thickness and alleviate the etching damage is a technical difficulty faced by the P-GaN gate structure. The problems of the growth and the process of the P-GaN gate structure can cause the problems of reliability, lower saturation current and the like of the device performance. How to obtain the high-performance and high-reliability AlGaN/GaN HEMTs is an important point of current industry and scientific research.
It should be noted that the foregoing description of the background art is only for the purpose of facilitating a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background section of the present application.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention is directed to providing a recessed gate type GaN-based HEMT device and a method for manufacturing the same, which are used for solving the problems of poor device reliability, difficult control of threshold voltage uniformity, and the like caused by the easy occurrence of gate leakage in the GaN-based HEMT device with a P-type gate structure in the prior art.
To achieve the above and other related objects, the present invention provides a groove gate type GaN-based HEMT device, comprising:
a substrate;
the epitaxial lamination is positioned on the substrate and comprises a GaN channel layer and a barrier layer which are sequentially overlapped from bottom to top, and the barrier layer is provided with a groove extending inwards from the surface of the barrier layer;
the groove gate structure is positioned in the groove and comprises a GaN layer, an AlGaN layer with gradually changed Al component and a metal gate which are sequentially overlapped from bottom to top;
the metal source electrode and the metal drain electrode are respectively arranged in openings penetrating through the GaN channel layer, and the metal source electrode and the metal drain electrode respectively form ohmic contact with the GaN channel layer.
Optionally, the barrier layer includes an ultrathin barrier layer and a top barrier layer grown on the GaN channel layer at intervals, the top barrier layer and the ultrathin barrier layer together define the groove, and the top barrier layer is disposed around the GaN layer and the AlGaN layer with graded Al composition.
Optionally, the AlGaN layer with graded Al composition has a variation of Al composition linearly decreasing to zero along the growth direction thereof, and the AlGaN layer with graded Al composition has a thickness ranging from 10nm to 20nm, wherein the AlGaN layer with graded Al composition forms schottky contact with the metal gate.
Optionally, the epitaxial stack further comprises a nucleation layer on the substrate, the nucleation layer comprising one or more of AlN, gaN, alGaN, the barrier layer comprising one or more of AlGaN barrier layer, inAlN barrier layer.
Optionally, the potential barrier is selected from an ultrathin AlGaN potential barrier layer and a top AlGaN potential barrier layer which are stacked, the top AlGaN potential barrier layer has an Al composition close to that of the ultrathin AlGaN potential barrier layer, and the Al composition of the ultrathin AlGaN potential barrier layer is larger than that of the AlGaN layer with gradually changed Al composition.
Optionally, the Al component of the ultrathin AlGaN barrier layer is 20-30% in mole percent, and the thickness of the ultrathin AlGaN barrier layer ranges from 5nm to 10nm.
The invention also provides a preparation method of the mixed groove gate type GaN-based HEMT device, which comprises the following steps:
providing a substrate, forming an epitaxial lamination on the substrate, wherein the step of forming the epitaxial lamination comprises the steps of sequentially epitaxially growing a GaN channel layer and a barrier layer;
defining a groove region on the barrier layer by photoetching;
sequentially epitaxially growing a GaN layer and an AlGaN layer with gradually changed Al components based on the groove region, wherein the thickness of a barrier layer below the GaN layer is smaller than that of a barrier layer outside the groove region;
etching the barrier layer based on a pattern mask to form an opening penetrating to the GaN channel layer;
and filling metal in the opening to form a metal source electrode and a metal drain electrode, wherein the metal source electrode and the metal drain electrode respectively form ohmic contact with the barrier layer, and a metal gate electrode is formed on the surface of the AlGaN layer with the gradually changed Al component.
Optionally, the method further comprises: and growing an ultrathin barrier layer and a top barrier layer on the GaN channel layer at intervals by the following steps: epitaxially growing the ultra-thin barrier layer; and after epitaxially growing the AlGaN layer with the graded Al composition, forming a top barrier layer surrounding the GaN layer and the AlGaN layer with the graded Al composition.
Optionally, the method further comprises: and growing an ultrathin AlGaN barrier layer and a top AlGaN barrier layer on the GaN channel layer at intervals, wherein the Al component in the ultrathin AlGaN barrier layer is 20-30% by mole percent, and the thickness range of the ultrathin AlGaN barrier layer is 5-10 nm.
Optionally, selectively growing the top-layer AlGaN barrier layer on the ultrathin AlGaN barrier layer through an MOCVD process, wherein the top surface of the top-layer AlGaN barrier layer is flush with the top surface of the AlGaN layer with gradually changed Al components.
Optionally, epitaxially growing the AlGaN layer with graded Al composition on the GaN layer by a high temperature epitaxy process, wherein the AlGaN layer with graded Al composition has a variation of Al composition linearly decreasing to zero along a growth direction thereof, and performing the high temperature epitaxy process at a temperature of 1050-1150 ℃.
Optionally, the step of lithographically defining the recess region on the barrier layer includes: depositing a hard mask layer on the ultrathin barrier layer; forming a photoetching pattern on the surface of the hard mask layer by adopting a photoetching process; and etching the hard mask layer by taking the window defined by the photoetching pattern as a mask to expose the ultrathin barrier layer.
As described above, the groove gate type GaN-based HEMT device and the manufacturing method thereof of the invention have the following beneficial effects:
the groove gate type GaN-based HEMT device provided by the invention comprises a groove extending from the surface of a barrier layer to the inside of the groove, a local Al component gradient AlGaN layer is grown at the groove, the Al component gradient AlGaN layer is adopted to replace the existing Mg doped GaN-based cap layer, the polarization gradient induces high-concentration holes, the depletion of a two-dimensional electronic device under a gate is realized, the enhanced GaN-based HEMT device is realized, the Al component gradient AlGaN layer has a larger forbidden bandwidth compared with P-type GaN, the gate leakage can be effectively improved, the breakdown voltage is improved, and the reliability of the device is improved; in addition, the barrier layer comprises an ultrathin barrier layer and a top barrier layer on the ultrathin barrier layer, the ultrathin barrier layer and the top barrier layer together define a groove, the thickness of the ultra-thin AlGaN barrier layer under the gate is accurately controllable, the uniformity of the threshold voltage of the device is improved, the thickness of the barrier layer outside the groove gate structure is not thinned, higher saturation current density can be obtained, and the power capacity of the device is improved.
According to the preparation method of the groove gate type GaN-based HEMT device, the enhancement type GaN-based HEMT device is realized by epitaxially growing the GaN layer and the AlGaN layer with gradually changed Al components based on the groove region defined on the barrier layer.
Drawings
Fig. 1 shows a schematic structure of a GaN-based HEMT device with an exemplary P-type gate structure.
Fig. 2 is a schematic structural diagram of a groove gate type GaN-based HEMT device according to an embodiment of the invention.
Fig. 3 is a schematic structural diagram of another example of a groove gate GaN-based HEMT device according to an embodiment of the invention.
Fig. 4 is a process flow diagram of preparing a recessed gate GaN-based HEMT device according to an embodiment of the invention.
Fig. 5A to 5I are schematic structural diagrams corresponding to each stage of a method for manufacturing a groove gate type GaN-based HEMT device according to an embodiment of the invention.
Fig. 6 shows transfer characteristic curves of the groove gate type GaN-based HEMT device and the P-type gate structure GaN-based device shown in fig. 1 according to the embodiment of the invention.
Fig. 7 shows breakdown characteristics of a recessed gate GaN-based HEMT device according to an embodiment of the invention and a P-type gate GaN-based device shown in fig. 1.
Description of element numbers:
1-a substrate; 2-a nucleation layer; a 30-GaN channel layer; 31-a high-resistance GaN buffer layer; a 4-barrier layer; a 5-GaN layer; a 6-AlGaN layer with gradually changed Al components; 412-grooves; 16-a silicon nitride hard mask layer; 162-groove region; a 26-silicon nitride protective layer; a 14-AlGaN barrier layer; a 15-P type GaN layer; 41-ultra-thin AlGaN barrier layers; 42-top AlGaN barrier layer; 7-metal gate; 8-metal source; 9-metal drain.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
The term "substrate" as referred to herein means a substrate including the substrate itself or a substrate having a material layer formed thereon.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complex.
Example 1
As shown in fig. 1, a GaN-based HEMT device with a P-type gate structure is shown, comprising: the epitaxial layer comprises a substrate 1, an epitaxial layer stack, a P-type gate structure, a metal source electrode 8 and a metal drain electrode 9, wherein the epitaxial layer stack comprises a nucleation layer 2, a GaN channel layer 30 and an AlGaN barrier layer 14 which are sequentially stacked; the P-type gate structure is located on the AlGaN barrier layer 14, and the P-type gate structure includes a P-type GaN layer 15 and a metal gate 7 disposed on the P-type GaN layer. The illustrated GaN-based HEMT device with the P-type gate structure realizes the depletion of 2DEG by lifting AlGaN/GaN under the gate through the P-type GaN gate, wherein the P-type GaN is usually realized by doping Mg, but the activation energy of the Mg is higher, higher hole concentration is difficult to obtain, and the diffusion of Mg impurities into a channel layer also brings about the reduction of the two-dimensional electron gas mobility.
In addition, the P-type grid structure needs to etch away part of the P-type GaN layer to expose the AlGaN barrier layer, and common dry etching has some problems, the lower etching precision leads to uneven threshold voltage of the device, the larger surface roughness of the etched groove is easy to generate electric field peak, the withstand voltage of the device is easy to be reduced, the reliability of the device is poor, the mobility of channel two-dimensional electron gas is reduced due to lattice damage generated in the etching process, and therefore the forward current of the device is reduced, and although lattice damage can be repaired to a certain extent by high-temperature annealing after groove etching, the fundamental problem can not be solved.
In order to realize the depletion of two-dimensional electron gas under a gate and improve the power capacity of the device, the invention provides a groove gate type GaN-based HEMT device, wherein a groove is formed under the gate by thinning a barrier layer under the gate, an Al component graded AlGaN layer locally combined with the groove is used for replacing a P-type GaN structure, and the depletion of two-dimensional electron gas under the gate is realized by utilizing the polarization gradient induction of the Al component graded AlGaN layer, so that an enhanced High Electron Mobility Transistor (HEMT) is realized.
Hereinafter, the recessed gate type GaN-based HEMT device provided by the invention will be specifically described with reference to the accompanying drawings.
Referring to fig. 2, the groove gate type GaN-based HEMT device provided by the embodiment of the invention includes: the substrate 1, the epitaxial lamination, the groove gate structure, the metal source electrode 8 and the metal drain electrode 9; the epitaxial lamination is positioned on the substrate 1, the epitaxial lamination comprises a GaN channel layer 30 and a barrier layer 4 which are sequentially overlapped from bottom to top, and the barrier layer 4 is provided with a groove 412 extending inwards from the surface of the barrier layer 4; the recess gate structure is located in the recess 412, and includes a GaN layer 5, an AlGaN layer 6 with graded Al composition, and a metal gate 7 stacked in sequence from bottom to top.
Specifically, the materials of the substrate 1 include, but are not limited to: a silicon carbide substrate, a sapphire substrate, a silicon substrate, a gallium nitride substrate, an aluminum nitride substrate, or a graphene substrate. The kind of the substrate is not particularly limited here, and may be selected as needed.
Through the technical scheme, high-concentration holes can be generated in the AlGaN layer with gradually changed Al components, so that the depletion of two-dimensional electron gas under the grid is realized, the enhancement HEMT effect is realized, and meanwhile, the negative effect of Mg doping is avoided.
As shown in fig. 2, the epitaxial stacked layer further comprises a nucleation layer 2 on the substrate 1, wherein the material of the nucleation layer 2 comprises one or more of AlN, gaN, alGaN, and the thickness of the nucleation layer 2 is 30 nm-100 nm. The epitaxial stack further comprises a high-resistance GaN buffer layer 31 between the nucleation layer 2 and the GaN channel layer 30, and a HEMT device with good anti-creeping performance can be prepared by arranging the high-resistance GaN buffer layer 31. For example, the doping ions of the high-resistance GaN buffer layer 31 may include one or a combination of Fe ions and C ions, and the thickness of the high-resistance GaN buffer layer 31 may be 300nm to 2 μm, such as 300nm, 800nm, 1 μm, 2 μm, etc.
In some embodiments, barrier layer 4 comprises an ultra-thin barrier layer and a top barrier layer grown at intervals on the GaN channel layer. As shown in fig. 3, when the barrier layer 4 is selected to be an ultrathin AlGaN barrier layer 41 and a top AlGaN barrier layer 42 which are stacked, the top AlGaN barrier layer 42 is disposed around the GaN layer 5 and the AlGaN layer 6 with graded Al composition, and the ultrathin AlGaN barrier layer 41 is exposed from the bottom of the groove; that is, the ultra-thin AlGaN barrier layer 41 and the top AlGaN barrier layer 42 on the ultra-thin barrier layer together define a recess 412.
In a specific embodiment, the thickness of the ultra-thin AlGaN barrier layer 41 ranges from 5nm to 10nm, the Al component is 20% -30% by mole, and the surface density of the two-dimensional electron gas can be ensured to be higher while the crystallization quality influence caused by the Al component is reduced by maintaining the thickness of the barrier layer outside the gate structure through the ultra-thin barrier layer below the gate structure.
In this embodiment, the top AlGaN barrier layer 42 has an Al composition close to that of the ultra-thin AlGaN barrier layer 41, and the Al composition of the ultra-thin AlGaN barrier layer 41 is 20% -30% in mole%. The AlGaN is more seriously lattice-mismatched with GaN, so that AlGaN cracks can be caused, performance is reduced, an ultrathin barrier layer is arranged below the gate structure, the thickness of the barrier layer outside the gate structure is not thinned, and the barrier layer can have 20-30% of Al component in mole percent based on the technical scheme.
With continued reference to fig. 3, the ultrathin AlGaN barrier layer 41 exposed at the bottom of the groove is sequentially provided with the GaN layer 5 and the AlGaN layer 6 with gradually changed Al components, the Al components of the ultrathin AlGaN barrier layer 41 are larger than those of the AlGaN layer 6 with gradually changed Al components, the AlGaN layer 6 with gradually changed Al components linearly decreases along the growth direction of the AlGaN layer 6, holes are induced by using polarization gradients of the AlGaN layer to enable the threshold voltage of the GaN-based HEMT device to be positively deviated, the polarization charge density generated in the mode is related to the gradient of the change of the Al components, and the AlGaN layer has a forbidden band width larger than that of the P-type GaN layer, so that gate leakage can be effectively improved and breakdown voltage can be improved; that is, the ultra-thin AlGaN barrier layer 41 has an Al composition larger than that of the end face of the AlGaN layer 6 adjacent to the GaN layer, in which the Al composition is graded. Preferably, the AlGaN layer has an Al composition variation linearly decreasing to zero along the growth direction thereof, so that two-dimensional electron gas below the gate structure can be completely exhausted, schottky contact is facilitated on the GaN surface exposed by the AlGaN layer, leakage current can be reduced, and surface oxidation of AlGaN can be prevented.
In some embodiments, the top AlGaN barrier layer 42 has an Al composition content close to that of the ultra thin AlGaN barrier layer 41, and the top AlGaN barrier layer 42 may be formed as a single layer or a stack such that the top surface of the top AlGaN barrier layer 42 is substantially flush or level with the top surface of the graded Al composition AlGaN layer. In a specific example, the thickness of the GaN layer 5 ranges from 3 nm to 10nm, for example, 5nm and 10nm; the AlGaN layer has a thickness in the range of 10nm to 20nm, for example, 5nm, 10nm, and 20nm.
Referring back to fig. 2, a metal source 8 and a metal drain 9 are respectively disposed in openings penetrating into the GaN channel layer, the metal source 8 and the metal drain 9 respectively forming ohmic contacts with the GaN channel layer 30. In a specific embodiment, the metal gate 7 may be selected from Ti/Au or Ti/Au metal layers, the metal gate 7 and the AlGaN layer 6 with graded Al composition form schottky contact, and the metal source 8 and the metal drain 8 may be selected from Ti/Al/Ni/Au multi-layer metal layers, respectively, so as to reduce the contact resistance of the device, thereby improving the electrical characteristics of the device.
Example two
Referring to fig. 4, the present embodiment provides a method for manufacturing a groove gate type GaN-based HEMT device, and the groove gate type GaN-based HEMT device described above is preferably manufactured by the method for manufacturing the groove gate type GaN-based HEMT device described in the present embodiment, and of course, may also be manufactured by other methods.
As shown in fig. 4, the preparation method comprises the following steps:
1) Providing a substrate, forming an epitaxial lamination layer on the substrate, wherein the step of forming the epitaxial lamination layer comprises the steps of sequentially epitaxially growing a GaN channel layer and a barrier layer;
2) Defining a groove region on the barrier layer by photoetching;
3) Sequentially epitaxially growing a GaN layer and an AlGaN layer with gradually changed Al components based on the groove region, wherein the thickness of a barrier layer below the GaN layer is smaller than that of a barrier layer outside the GaN layer;
4) Etching the barrier layer based on a pattern mask to form an opening penetrating to the GaN channel layer;
5) And filling metal in the opening to form a metal source electrode and a metal drain electrode, wherein the metal source electrode and the metal drain electrode respectively form ohmic contact with the GaN channel layer, and a metal grid electrode is formed on the surface of the AlGaN layer with the gradually changed Al component.
First, as shown in fig. 4, step 1) is performed: a substrate 1 is provided and an epitaxial stack is formed on the substrate 1, the step of forming the epitaxial stack comprising sequentially epitaxially growing a GaN channel layer 30 and a barrier layer.
Specifically, the materials of the substrate 1 include, but are not limited to: the silicon carbide substrate, the sapphire substrate, the silicon substrate, the gallium nitride substrate, the aluminum nitride substrate, or the graphene substrate is not particularly limited, and the type of the substrate may be selected as needed. The dimensions of the substrate 1 may be 6 inches, 8 inches wafer, 12 inches, etc., and the thickness and dimensions of the substrate 1 are not excessively limited herein.
As shown in fig. 5A, in some embodiments, the step of forming the epitaxial stack further comprises: before epitaxially growing the GaN channel layer 30, a nucleation layer 2 and a high-resistance GaN buffer layer 31 are sequentially epitaxially grown on the substrate 1, wherein the material of the nucleation layer 2 may include one or more of AlN, gaN, alGaN, and the thickness of the nucleation layer 2 is 30 nm-100 nm.
In a specific embodiment, an ultra-thin barrier layer and a top barrier layer are grown on the GaN channel layer 30 at intervals by: epitaxially growing the ultra-thin barrier layer; after epitaxially growing the Al-graded AlGaN layer 6, a top barrier layer is formed around the GaN layer 5 and the Al-graded AlGaN layer 6. Preferably, as shown in fig. 5A, an ultra-thin AlGaN barrier layer 41 and a top AlGaN barrier layer 42 are grown on the GaN channel layer at intervals, wherein the thickness of the ultra-thin AlGaN barrier layer 41 ranges from 5nm to 10nm, and the al composition is 20% -30% in mole percentage. In other embodiments, the barrier layer may be epitaxially grown continuously on the GaN channel layer 30, such as the barrier layer 4 shown in fig. 2.
In some examples, gaN channel layer 30 and barrier layer 4 are sequentially epitaxially grown by, for example, a Metal Organic Chemical Vapor Deposition (MOCVD) process, by which the growth rate can be controlled relatively precisely while being suitable for industrial production.
As shown in fig. 4, step 2) is performed to lithographically define a recess region on the barrier layer.
Specifically, step 2) includes: depositing a hard mask layer on the ultra-thin barrier layer 41; the hard mask layer is etched using the lithographically defined windows as a mask to define recessed regions 162 exposing the ultra-thin barrier layer.
As shown in fig. 5A to 5B, in a specific embodiment, step 2) includes: after forming the ultra-thin AlGaN barrier layer 41 on the GaN channel layer 30, forming a hard mask layer on the ultra-thin AlGaN barrier layer 41; the hard mask layer is etched based on a pattern mask to define a recessed region 162 exposing the ultra-thin AlGaN barrier layer.
In this embodiment, the silicon nitride hard mask layer 16 deposited on the ultra-thin AlGaN barrier layer 41 may be formed by depositing the silicon nitride hard mask layer 16 on the ultra-thin AlGaN barrier layer 41 by any one of the following processes: MOCVD, LPCVD, PECVD, ICPCVD.
In a specific example, the step of etching the hard mask layer based on the graphic mask includes: sequentially spin-coating photoresist on the hard mask layer, and photoetching to define a pattern area, wherein the pattern area corresponds to the position for forming a gate electrode in a subsequent process; and etching the hard mask layer by taking the pattern area defined by the photoresist as a mask, and defining a groove area 162 exposing the ultrathin AlGaN barrier layer. In this embodiment, the hard mask layer is selected from a silicon nitride hard mask layer, and the etching step of the silicon nitride hard mask layer may preferably be a Reactive Ion Etching (RIE) process, an inductively coupled plasma etching (ICP) process, or the like.
In the example of continuously growing the barrier layer 4 on the GaN channel layer 30, the barrier layer 4 may be thinned with the window defined by the recess region as a mask, so that the thickness of the barrier layer below the recess region is smaller than the thickness of the barrier layer outside the recess region, where the recess region corresponds to the position where the gate electrode is formed in the subsequent process.
After step 2), as shown in fig. 5C to 5D, step 3) is performed: and sequentially epitaxially growing a GaN layer 5 and an AlGaN layer 6 with gradually changed Al components based on the groove region, wherein the thickness of a barrier layer below the GaN layer is smaller than that of a barrier layer outside the GaN layer.
Specifically, the step of epitaxially growing the GaN layer 5 and the AlGaN layer 6 having a graded Al composition includes: based on the recess region 162 defined by the hard mask layer, a GaN layer 5 and an AlGaN layer 6 with gradually changed Al composition are selectively grown on the exposed ultrathin AlGaN barrier layer, and the AlGaN layer 6 with gradually changed Al composition has a reversely changed Al composition, that is, the Al composition gradually decreases along the growth direction of the AlGaN material, and the net polarization charges of adjacent electric dipole interfaces are negative, so that high-concentration holes are induced under the action of a polarization electric field, and the depletion of two-dimensional electron gas under the gate is realized.
In some embodiments, as shown in fig. 5C-5D, step 3) further comprises: and selectively growing a GaN layer 5 and an AlGaN layer 6 with gradually changed Al components on the exposed ultrathin AlGaN layer through an MOCVD process, wherein the ultrathin AlGaN barrier layer outside the groove area is covered with a silicon nitride hard mask layer, so that the GaN layer and the AlGaN layer with gradually changed Al components are preferentially deposited on the exposed ultrathin AlGaN barrier layer through the MOCVD process.
In a specific example, the AlGaN layer 6 with graded Al composition may be continuously grown on the GaN layer 5 by a high temperature epitaxy process, where the Al composition in the AlGaN layer 6 with graded Al composition linearly decreases to zero along the growth direction, and the high temperature epitaxy process is performed at a temperature of 1050-1150 ℃; that is, when the AlGaN layer 6 in which the Al composition is graded includes a first portion epitaxially grown in an initial stage and a second portion epitaxially grown in a termination stage, the first portion has an Al composition content smaller than that in the ultra-thin AlGaN barrier layer, and the second portion has an Al composition content close to zero. The process parameters such as the ratio of the aluminum source and the gallium source for epitaxially growing AlGaN, the reaction temperature, and the chamber pressure can be flexibly adjusted by those skilled in the art according to the required device performance, and are not particularly limited herein.
Further, step 3) further comprises: removing the hard mask layer covering the ultra-thin AlGaN barrier layer 41; depositing a protective layer to cover the ultrathin AlGaN barrier layer 41 and the AlGaN layer 6 with gradually changed Al components; selectively removing a part of the protective layer, and reserving the protective layer covered on the AlGaN layer 6 with the gradual change of the Al component for protecting the AlGaN layer 6 with the gradual change of the Al component from being damaged by a subsequent wet etching process; a top AlGaN barrier layer 42 is selectively grown over the exposed ultra thin AlGaN barrier layer. Preferably, as shown in fig. 5E to 5G, after the hard mask layer covering the ultra-thin barrier layer is removed, a silicon nitride protection layer 26 covering the ultra-thin AlGaN barrier layer 41 and the AlGaN layer 6 with graded Al composition is formed, wherein the thickness of the silicon nitride protection layer 26 is 20nm to 30nm, and the silicon nitride protection layer can be grown by any one of the following processes: MOCVD, LPCVD, PECVD, ICPCVD.
In some embodiments, the top AlGaN barrier layer 42 may be selectively grown on the ultrathin AlGaN barrier layer 41 by an MOCVD process until the top surface of the top AlGaN barrier layer 42 is substantially flush or flush with the top surface of the AlGaN layer 6 with graded Al composition, which is helpful for performing subsequent processes, such as photolithography, so that exposure operation is performed on the flush surface, focusing light can be performed at the same resolution, the resolution and repeatability of the chip pattern are ensured, and the thin film deposition process is performed on the surface without obvious steps, so that non-uniformity and cracks that may be generated in film formation at the steps are avoided, the top AlGaN barrier layer 42 is epitaxially grown on the exposed surface of the ultrathin AlGaN barrier layer 41, and the Al composition of the top AlGaN barrier layer 42 is consistent with the Al composition of the underlying ultrathin AlGaN barrier layer. The ultra-thin AlGaN barrier layer 41 and the top AlGaN barrier layer 42 which together define the groove are formed through a secondary epitaxial process, and the AlGaN barrier layer thinned through an etching process is replaced, so that the thickness control capability of the ultra-thin AlGaN barrier layer under the gate can be improved, the threshold voltage uniformity of the device is improved, and the reliability of the device is improved.
In this embodiment, the wet etching process, such as BOE (HF: NH) 4 F) The solution removes the silicon nitride protective layer 26 covering the AlGaN layer 6 with graded Al composition.
As shown in fig. 4, step 4) is performed to etch the barrier layer based on a pattern mask, thereby forming an opening penetrating to the GaN channel layer.
Specifically, as shown in fig. 5H, step 4) includes: an opening (not shown) is formed to sequentially penetrate the top AlGaN barrier layer 42 and the ultra-thin AlGaN barrier layer 41 to expose the GaN channel layer.
Subsequently, as shown in fig. 5I, step 5) is performed: and filling metal in the opening to form a metal source electrode 8 and a metal drain electrode 9, filling metal in the opening to form the metal source electrode 8 and the metal drain electrode 9, and forming a metal gate electrode 7 on the surface of the AlGaN layer 6 with the gradual change Al component. Regarding the photolithography process for forming the pattern mask, a series of operations such as gumming, exposing, developing, etc. commonly used in the art may be adopted, and will not be described herein.
It should be noted that the material and the preparation method of the metal source and the metal drain described in the foregoing exemplary embodiments may be adopted in the present invention, and other manners commonly used in the art may also be adopted in the present invention, which are not limited herein.
In this embodiment, the step of forming the metal source electrode 8 and the metal drain electrode 9 includes: an annealing process is performed at 800-850 ℃ for 1-5 min to form ohmic contacts between the metal source electrode 8 and the metal drain electrode 9 and the GaN channel layer 30.
In some embodiments, at step 5), forming the metal gate 7 includes: after defining a pattern area of a grid electrode on the Al component gradient AlGaN layer 6, depositing metal on the surface of the photoresist according to the defined pattern area of the grid electrode; subsequently, the photoresist is stripped while removing the metal attached to the photoresist together, leaving a metal electrode on the Al-composition graded AlGaN layer, the metal gate 7 forming a schottky contact with the Al-composition graded AlGaN layer 6. For example, the metal gate 7 may be selected from a Ni/Au or Ti/Au metal layer.
In a specific example, the end face of the AlGaN layer 6 with graded Al composition has an Al content of almost zero, i.e. the surface of the resulting material layer is mainly GaN, which is advantageous for the metal gate to form a schottky contact.
In order to verify the advantages of the implementation mode of the invention in static characteristics, the preferred mode of the groove gate type GaN-based HEMT device and the GaN-based HEMT device with the P-type gate structure shown in fig. 1 are adopted as comparative examples to respectively carry out simulation tests of transfer characteristics and breakdown characteristics, wherein the transfer characteristics and the breakdown characteristics are respectively tested at a drain voltage V D The transfer characteristic at 5V is shown in fig. 6, and the breakdown characteristic at a gate voltage Vg of 0V is shown in fig. 7.
As can be seen from the transfer characteristic curve of fig. 6, compared with the GaN-based HEMT device with the P-type gate structure, the recessed gate GaN-based HEMT device of the present invention has higher saturation current density and higher threshold voltage.
Comparing the three-terminal breakdown voltage of the groove gate type GaN-based HEMT device of the invention with that of the GaN-based HEMT device of the P type gate structure shown in fig. 1, the groove gate type GaN-based HEMT device of the invention can be seen to be in the V shape when the gate voltage Vg of the device of the invention is 0V DS Lower leakage current than the comparative example device, with higher breakdown voltage.
In summary, the groove gate type GaN-based HEMT device and the preparation method thereof have the following beneficial effects:
the groove gate type GaN-based HEMT device provided by the invention comprises the groove extending from the surface of the barrier layer to the inside of the groove, the AlGaN layer with gradually changed local Al component grows in the groove, the AlGaN layer with gradually changed Al component is adopted to replace the existing Mg doped GaN-based cap layer, high-concentration holes are generated, the depletion of a two-dimensional electronic device under a gate is realized, the enhanced GaN-based HEMT device is realized, the Al component gradually changed AlGaN layer has a larger forbidden band width compared with P-type GaN, the gate leakage can be effectively improved, the breakdown voltage is improved, and the reliability of the device is improved.
According to the preparation method of the groove gate type GaN-based HEMT device, the enhancement type GaN-based HEMT device is realized by epitaxially growing the GaN layer and the AlGaN layer with gradually changed Al components based on the groove region defined on the barrier layer; in addition, the ultra-thin barrier layer is grown through an epitaxial process, the barrier layer thinned through an etching process is replaced, the thickness control capability of the ultra-thin barrier layer under the gate is improved, unstable current caused by the etching method is avoided, and the reliability of the device is improved.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (12)

1. The groove gate type GaN-based HEMT device is characterized by comprising:
a substrate;
the epitaxial lamination is positioned on the substrate and comprises a GaN channel layer and a barrier layer which are sequentially overlapped from bottom to top, and the barrier layer is provided with a groove extending inwards from the surface of the barrier layer;
the groove gate structure is positioned in the groove and comprises a GaN layer, an AlGaN layer with gradually changed Al components and a metal gate which are sequentially overlapped from bottom to top, and the AlGaN layer with gradually changed Al components has the Al component change which linearly decreases to zero along the growth direction;
the metal source electrode and the metal drain electrode are respectively arranged in an opening penetrating through the GaN channel layer, ohmic contact is formed between the metal source electrode and the metal drain electrode and the GaN channel layer, and Schottky contact is formed between the AlGaN layer with gradually changed Al components and the metal gate electrode.
2. The recessed gate type GaN-based HEMT device of claim 1, wherein: the barrier layer comprises an ultrathin barrier layer and a top barrier layer which are grown on the GaN channel layer at intervals, the top barrier layer and the ultrathin barrier layer jointly define the groove, and the top barrier layer is arranged around the GaN layer and the AlGaN layer with gradually changed Al components.
3. The recessed gate type GaN-based HEMT device of claim 1, wherein: the thickness range of the AlGaN layer with the gradual change Al component is 10nm-20nm.
4. The recessed gate type GaN-based HEMT device of claim 1, wherein: the epitaxial stack further includes a nucleation layer on the substrate, the nucleation layer including one or more of AlN, gaN, alGaN, the barrier layer including one or more of an AlGaN barrier layer, an InAlN barrier layer.
5. The recessed gate type GaN-based HEMT device of claim 2, wherein: the barrier layer is selected from an ultrathin AlGaN barrier layer and a top AlGaN barrier layer which are stacked, the top AlGaN barrier layer is provided with an Al component close to the ultrathin AlGaN barrier layer, and the Al component of the ultrathin AlGaN barrier layer is larger than that of the AlGaN layer with gradually changed Al component.
6. The recessed gate type GaN-based HEMT device of claim 5, wherein: the Al component of the ultrathin AlGaN barrier layer is 20-30% by mole percent, and the thickness range of the ultrathin AlGaN barrier layer is 5-10 nm.
7. The preparation method of the groove gate type GaN-based HEMT device is characterized by comprising the following steps of:
providing a substrate, forming an epitaxial lamination on the substrate, wherein the step of forming the epitaxial lamination comprises the steps of sequentially epitaxially growing a GaN channel layer and a barrier layer;
defining a groove region on the barrier layer by photoetching;
sequentially epitaxially growing a GaN layer and an AlGaN layer with gradually changed Al components based on the groove region, wherein the thickness of a barrier layer below the GaN layer is smaller than that of a barrier layer outside the groove region, and the AlGaN layer with gradually changed Al components linearly decreases to zero along the growth direction;
etching the barrier layer based on a pattern mask to form an opening penetrating to the GaN channel layer;
and filling metal in the opening to form a metal source electrode and a metal drain electrode, wherein the metal source electrode and the metal drain electrode respectively form ohmic contact with the barrier layer, a metal grid electrode is formed on the surface of the AlGaN layer with gradually changed Al components, and the AlGaN layer with gradually changed Al components and the metal grid electrode form Schottky contact.
8. The method for manufacturing the recessed gate type GaN-based HEMT device of claim 7, further comprising: and growing an ultrathin barrier layer and a top barrier layer on the GaN channel layer at intervals by the following steps: epitaxially growing the ultra-thin barrier layer; and after epitaxially growing the AlGaN layer with the graded Al composition, forming a top barrier layer surrounding the GaN layer and the AlGaN layer with the graded Al composition.
9. The method for manufacturing the recessed gate type GaN-based HEMT device of claim 7, further comprising: and growing an ultrathin AlGaN barrier layer and a top AlGaN barrier layer on the GaN channel layer at intervals, wherein the Al component in the ultrathin AlGaN barrier layer is 20-30% by mole percent, and the thickness range of the ultrathin AlGaN barrier layer is 5-10 nm.
10. The method for manufacturing the groove gate type GaN-based HEMT device according to claim 9, which is characterized in that: and selectively growing the top AlGaN barrier layer on the ultrathin AlGaN barrier layer through an MOCVD process, wherein the top surface of the top AlGaN barrier layer is flush with the top surface of the AlGaN layer with gradually changed Al components.
11. The method for manufacturing the groove gate type GaN-based HEMT device according to claim 7, which is characterized in that: and epitaxially growing the Al-component graded AlGaN layer on the GaN layer through a high-temperature epitaxial process, and executing the high-temperature epitaxial process at the temperature of 1050-1150 ℃, wherein the Al-component graded AlGaN layer has Al component variation linearly decreasing to zero along the growth direction.
12. The method of manufacturing a recessed gate GaN-based HEMT device of claim 8, wherein the step of lithographically defining the recessed region on the barrier layer comprises: depositing a hard mask layer on the ultrathin barrier layer; forming a photoetching pattern on the surface of the hard mask layer by adopting a photoetching process; and etching the hard mask layer by taking the window defined by the photoetching pattern as a mask to expose the ultrathin barrier layer.
CN202311725665.4A 2023-12-15 2023-12-15 Groove gate type GaN-based HEMT device and preparation method thereof Active CN117438457B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311725665.4A CN117438457B (en) 2023-12-15 2023-12-15 Groove gate type GaN-based HEMT device and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311725665.4A CN117438457B (en) 2023-12-15 2023-12-15 Groove gate type GaN-based HEMT device and preparation method thereof

Publications (2)

Publication Number Publication Date
CN117438457A CN117438457A (en) 2024-01-23
CN117438457B true CN117438457B (en) 2024-03-22

Family

ID=89551819

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311725665.4A Active CN117438457B (en) 2023-12-15 2023-12-15 Groove gate type GaN-based HEMT device and preparation method thereof

Country Status (1)

Country Link
CN (1) CN117438457B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101477951A (en) * 2009-01-13 2009-07-08 中山大学 Enhanced AlGaN/GaN field effect tube and manufacturing method thereof
CN113937155A (en) * 2021-09-29 2022-01-14 西安电子科技大学 HEMT (high electron mobility transistor) device with gradually-changed components and composite barrier layer and preparation method thereof
CN115548095A (en) * 2022-10-13 2022-12-30 复旦大学 Enhanced gallium nitride device and manufacturing method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112652659B (en) * 2019-10-09 2024-02-13 联华电子股份有限公司 High electron mobility transistor and manufacturing method thereof
CN115132585A (en) * 2021-03-29 2022-09-30 联华电子股份有限公司 High electron mobility transistor and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101477951A (en) * 2009-01-13 2009-07-08 中山大学 Enhanced AlGaN/GaN field effect tube and manufacturing method thereof
CN113937155A (en) * 2021-09-29 2022-01-14 西安电子科技大学 HEMT (high electron mobility transistor) device with gradually-changed components and composite barrier layer and preparation method thereof
CN115548095A (en) * 2022-10-13 2022-12-30 复旦大学 Enhanced gallium nitride device and manufacturing method thereof

Also Published As

Publication number Publication date
CN117438457A (en) 2024-01-23

Similar Documents

Publication Publication Date Title
CN110190116B (en) High-threshold-voltage normally-off high-electron-mobility transistor and preparation method thereof
JP4179539B2 (en) Compound semiconductor device and manufacturing method thereof
US8680580B2 (en) Field effect transistor and process for manufacturing same
US9543391B2 (en) High electron mobility transistor having reduced threshold voltage variation and method of manufacturing the same
EP2657976A2 (en) Compound Semiconductor Device and Manufacturing Method of the Same
US20040201038A1 (en) Compound semiconductor device and its manufacture
KR20070032790A (en) Methods of fabricating nitride based transistors having a cap layer and a recessed gate
US10381469B2 (en) Semiconductor device and method of manufacturing the same
CN110648914B (en) Method for improving breakdown voltage of gallium nitride transistor
CN216354230U (en) Semiconductor device and application thereof
TWI701835B (en) High electron mobility transistor
WO2022199309A1 (en) Hemt device having p-gan cap layer and preparation method therefor
CN111584628B (en) Enhanced GaN HEMT device and preparation method thereof
CN117438457B (en) Groove gate type GaN-based HEMT device and preparation method thereof
JP2008010461A (en) Hetero-junction field effect transistor, and manufacturing method of hetero-junction field effect transistor
CN111755330A (en) Semiconductor structure and manufacturing method thereof
CN111739800B (en) Preparation method of SOI-based concave gate enhanced GaN power switch device
JP5169515B2 (en) Compound semiconductor device
CN112768508B (en) Back gate full-control AlGaN/GaN heterojunction enhanced power HEMT device and preparation method thereof
CN115588616B (en) Method and device for manufacturing enhanced gallium nitride high electron mobility transistor
CN113035934B (en) GaN-based HEMT device and preparation method thereof
CN113889412B (en) Ohmic contact GaN device and preparation method thereof
CN216749909U (en) GaN semiconductor device integrating multiple working modes
WO2022205469A1 (en) Iii nitride semiconductor wafers
CN117766564A (en) Enhanced n-channel GaN high electron mobility transistor based on p-GaN buried layer structure regulation threshold and preparation method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant