CN111463260B - Vertical high electron mobility field effect transistor and preparation method thereof - Google Patents

Abstract

The invention discloses a vertical type high electron mobility field effect transistor and a preparation method thereof. The present invention provides a vertical high electron mobility field effect transistor, comprising: a substrate; a current blocking layer disposed on one side of the substrate, the current blocking layer having conductive through holes; The channel layer on the side of the channel layer; the barrier layer arranged on the side of the channel layer away from the current blocking layer, a first two-dimensional electron gas is formed at the interface where the barrier layer and the channel layer are in contact, and the first two-dimensional electron gas is formed On the side of the channel layer, the barrier layer has a groove, and the distance between the bottom of the groove and the channel layer is not more than 5 nm; the passivation layer is arranged on the side of the barrier layer away from the channel layer; it is arranged in the groove A second two-dimensional electron gas is formed at the interface between the semiconductor layer and the channel layer, and the second two-dimensional electron gas is formed on one side of the semiconductor layer. Thereby, normally-off characteristics of the vertical type high electron mobility field effect transistor can be easily realized.

Description

Vertical high electron mobility field effect transistor and preparation method thereof

technical field

The present invention relates to the field of semiconductors, in particular to a vertical high electron mobility field effect transistor and a preparation method thereof.

Background technique

With the improvement of scientific and technological level, the third-generation semiconductor materials represented by gallium nitride (GaN) are widely used due to their advantages of large band gap, high critical breakdown field strength, high electron saturation drift rate and high thermal conductivity. It is widely used in the preparation of high-frequency, high-temperature, high-power power electronic devices, and is used in high-tech fields such as mobile communications, radar base stations, and aerospace. For example, gallium nitride (GaN)-based high electron mobility field effect transistor (HEMT) devices, due to the AlGaN/GaN heterojunction will form a higher concentration of two-dimensional electron gas at the heterojunction interface, making GaN (GaN)-based high electron mobility field effect transistor (HEMT) devices have the characteristics of high reverse blocking voltage, low forward conduction resistance, and high operating frequency, and are widely used in high current, low power consumption, and high voltage switching devices. . For AlGaN/GaN devices, the enhancement mode (normally off) characteristic of the high electron mobility field effect transistor (HEMT) device is more than the depletion mode (normally on) characteristic of the high electron mobility field effect transistor (HEMT) device. wider range of applications.

However, the current vertical high electron mobility field effect transistors and their fabrication methods still need to be improved.

SUMMARY OF THE INVENTION

The present invention is made based on the inventors' findings and understanding of the following facts and problems:

The current gallium nitride (GaN)-based high electron mobility field effect transistor (HEMT) devices are mainly lateral devices. In the off state, electrons injected from the source can pass through the gallium nitride (GaN) buffer layer to reach the drain. A leakage channel is formed. Excessive leakage current of the buffer layer will lead to premature breakdown of the device, which cannot give full play to the high withstand voltage advantages of gallium nitride (GaN) materials, thus limiting the high electron mobility field effect transistors based on gallium nitride (GaN) (HEMT) devices are used in high voltage applications, and lateral gallium nitride (GaN)-based high electron mobility field effect transistor (HEMT) devices mainly rely on the active region between the gate and drain to withstand the voltage. To obtain a large breakdown voltage, it is necessary to design a large gate-drain distance, which increases the chip area and is not conducive to the development trend of portability and miniaturization. Compared with lateral gallium nitride (GaN) based high electron mobility field effect transistor (HEMT) devices, vertical gallium nitride (GaN) based high electron mobility field effect transistor (HEMT) devices have the following advantages: No longer limited by the lateral size, the device mainly withstands the voltage through the vertical spacing between the gate and the drain. The lateral size of the device can be designed to be very small, which can save the chip area; at the same time, the p-type GaN current blocking layer and the n-type The p-n junction formed between the GaN buffer layers can effectively block electrons injected from the source, thereby suppressing the device buffer layer leakage current. In addition, gallium nitride (GaN)-based high electron mobility field effect transistor (HEMT) devices, while high carrier concentration and electron mobility, while helping to provide very low series resistance, also make them exhibit Due to the characteristics of normally-on devices, a negative pressure source needs to be introduced to turn off the device in practical circuit applications, which poses a safety hazard and increases the complexity and cost of the circuit.

For lateral devices, the current technical means for realizing enhancement-mode (normally-off) high electron mobility field effect transistors (HEMTs) mainly include: (1) p-GaN gate structure; (2) fluorine ion implantation technology; (3) gate groove etching technology; (4) cascade mode. However, in technical means (1), a p-type GaN layer is inserted between the AlGaN/GaN heterojunction material and the gate, and the energy band of the AlGaN barrier layer is raised through the p-type GaN layer, thereby depleting the two-dimensional electron gas (2DEG), to realize enhancement mode high electron mobility field effect transistor (HEMT), but limited by the current fabrication process, the activation rate of p-type doping in GaN is low, and the two-dimensional electron gas in the channel cannot be completely depleted (2DEG), resulting in a low threshold voltage of the device; in technical means ( ₂ ), the AlGaN barrier layer under the gate is treated with CF plasma, and the F entering the AlGaN barrier layer will capture electrons to form negatively charged F ions, deplete the two-dimensional electron gas (2DEG) in the channel, and realize an enhancement-type high electron mobility field effect transistor (HEMT), but implanting F ions into the AlGaN barrier layer will affect the AlGaN barrier on the one hand. On the other hand, the thin barrier layer makes the distribution of F ions difficult to control, and it is very close to the two-dimensional electron gas (2DEG) in the channel, which will reduce the electron concentration and mobility in the channel; technology In means (3), an enhancement mode high electron mobility field effect transistor (HEMT) is realized by using a trench gate structure, and the trench etching can effectively deplete the two-dimensional electron gas (2DEG) in the region under the gate, and improve the threshold voltage, However, groove etching requires precise control of the etching depth and reduction of etching damage caused by plasma treatment, and the process requirements are strict; in technical means (4), the cascade structure can be used to prepare an enhanced high electron mobility field effect transistor (HEMT). However, the topology of the enhancement-mode high electron mobility field effect transistor (HEMT) realized by the cascade structure is complex, requiring three devices, and limited by the current technology, the on-chip integration of these three devices at the process level cannot be realized. Therefore, they need to be interconnected by means of substrates and metal wires, which increases product cost and introduces additional internal parasitics. Likewise, for vertical devices, the aforementioned drawbacks also exist.

Therefore, if a new vertical high electron mobility field effect transistor and its preparation method can be proposed, the conductive channel of the 2DEG can be easily and completely blocked, without causing damage to the barrier layer, etc., the operation is simple, and the production cost is Low, and high breakdown voltage, better withstand voltage performance, will be able to solve the above problems to a large extent.

In view of this, in one aspect of the present invention, the present invention provides a vertical type high electron mobility field effect transistor. According to an embodiment of the present invention, the vertical type high electron mobility field effect transistor comprises: a substrate; a current blocking layer, the current blocking layer is disposed on one side of the substrate, and the current blocking layer has a conductive a hole; a channel layer, the channel layer is provided on the side of the current blocking layer away from the substrate; a potential barrier layer, the potential barrier layer is provided on the side of the channel layer away from the current blocking layer On one side, a first two-dimensional electron gas is formed at the interface between the barrier layer and the channel layer, and the first two-dimensional electron gas is formed on one side of the channel layer, and the potential barrier There is a groove in the layer, and the distance between the bottom of the groove and the channel layer is not more than 5nm; a passivation layer, the passivation layer is arranged on a part of the barrier layer away from the channel layer. side, and the passivation layer covers the sidewall of the barrier layer facing the inside of the groove, the passivation layer does not cover the bottom of the groove; a semiconductor layer, the semiconductor layer is disposed on the groove In the groove, a second two-dimensional electron gas is formed at the interface between the semiconductor layer and the channel layer, and the second two-dimensional electron gas is formed on one side of the semiconductor layer. Therefore, in the vertical high electron mobility field effect transistor, the conductive channel formed by the first two-dimensional electron gas passing through the conductive through hole can be blocked by the passivation layer and the second two-dimensional electron gas, which can easily To achieve normally-off characteristics, the vertical high electron mobility field effect transistor has better performance, higher breakdown voltage, better withstand voltage performance, higher reliability and stability, and the vertical high electron mobility field effect transistor. The effect transistor also has at least one of the following advantages: (1) the channel layer of the two-dimensional electron gas can be completely blocked without using a doping activation process, and it is beneficial to improve the threshold voltage of the device; (2) etching recessed The precision requirements of the groove are low, which can reduce the difficulty of the process; (3) the two-dimensional electron gas in the conductive channel can be depleted without using the ion implantation process, and the shutdown can be realized, which can avoid the damage to the barrier layer caused by the ion implantation. ; (4) There is no need to use the cascade mode, the normally-off characteristic of the device can be realized on a single chip, the cost can be reduced, and the introduction of additional parasitic parameters can be avoided.

According to an embodiment of the present invention, the forbidden band width of the barrier layer is larger than the forbidden band width of the channel layer, and the forbidden band width of the semiconductor layer is smaller than the forbidden band width of the channel layer. Therefore, a heterojunction structure can be formed between the barrier layer and the channel layer, the first two-dimensional electron gas can be generated at the interface of the heterojunction, and the first two-dimensional electron gas can be formed on the side close to the channel layer. A heterojunction structure can be formed between the layer and the channel layer, a second two-dimensional electron gas can be generated at the interface of the heterojunction, and the second two-dimensional electron gas can be formed on the side close to the semiconductor layer, which can better realize the vertical type. The normally-off characteristics of the high electron mobility field effect transistor device and the vertical high electron mobility field effect transistor device have high reliability and stability, and have better performance.

According to an embodiment of the present invention, the material for forming the barrier layer includes Al mGa _{(1-m) N} crystal, wherein 0.15≤m≤0.80, and the thickness of the barrier layer is not less than 30 nm. Therefore, a heterojunction structure can be formed between the barrier layer formed of the above-mentioned material and the channel layer, the first two-dimensional electron gas with higher concentration can be generated at the interface of the heterojunction, and the thickness of the barrier layer is the above In the range, it can have better performance, and can further improve the performance of the vertical type high electron mobility field effect transistor device.

According to an embodiment of the present invention, the material for forming the semiconductor layer includes InnGa _{(1-n) N} crystal, wherein 0<n≦0.45, and the thickness of the semiconductor layer is not less than 30 nm. Therefore, the semiconductor layer formed of this material can form a heterojunction structure with the channel layer, and a second two-dimensional electron gas with a higher concentration can be generated at the interface of the heterojunction, which can further improve the vertical high electron mobility. Field effect transistor device performance. Moreover, when the thickness of the semiconductor layer is in the above range, it can have better performance, and can further improve the performance of the vertical type high electron mobility field effect transistor device.

According to an embodiment of the present invention, the thickness of the current blocking layer is h, and 10 nm≦h<1000 nm. Therefore, when the thickness of the current blocking layer is in the above range, the current leakage of the vertical high electron mobility field effect transistor can be better suppressed, and the performance of the vertical high electron mobility field effect transistor device can be further improved.

According to an embodiment of the present invention, the vertical type high electron mobility field effect transistor further comprises: a nucleation layer, the nucleation layer is provided on one side of the substrate; a buffer layer, the buffer layer is provided on the a side of the nucleation layer away from the substrate, the current blocking layer is formed in the buffer layer; an anti-diffusion layer, the anti-diffusion layer is arranged on the side of the buffer layer away from the nucleation layer ; the channel layer is arranged on the side of the anti-diffusion layer away from the buffer layer; the gate is arranged on the side of the semiconductor layer away from the channel layer, and the groove is located on the side of the semiconductor layer away from the channel layer. The orthographic projection of the gate on the substrate is not greater than the orthographic projection of the gate on the substrate, and the orthographic projection of the gate on the substrate is not less than that of the conductive via on the substrate The orthographic projection of ; the source electrode, the source electrode is arranged on the side of the barrier layer away from the channel layer, the source electrode is in contact with the barrier layer; the drain electrode, the drain electrode is arranged on the side of the barrier layer away from the channel layer The side of the substrate remote from the nucleation layer. Therefore, the nucleation layer can match the substrate material with the buffer layer, the buffer layer can suppress the current leakage of the vertical high electron mobility field effect transistor device, and the anti-diffusion layer can better prevent the ions in the current blocking layer from In the subsequent process, it diffuses into the channel layer to reduce the mobility of the two-dimensional electron gas in the channel layer, which can improve the performance of the vertical high electron mobility field effect transistor device, and the gate can form a better Schottky with the semiconductor layer. The base contact, the source can be directly contacted with the barrier layer to form a good ohmic contact, and the drain is made under the substrate, which can make the entire surface of the device in a low electric field state, which can effectively avoid the concentration of the electric field on the edge of the gate. The withstand voltage performance is not limited by the lateral size. The device mainly withstands the withstand voltage through the vertical spacing between the gate and the drain. The lateral size of the device can be designed to be smaller, which can effectively save the area of the chip and further improve the vertical performance of high electron mobility field effect transistor devices.

According to an embodiment of the present invention, the material for forming the substrate includes gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, silicon One or more of; the material for forming the buffer layer includes one or more of n-type gallium nitride crystal and unintentionally doped gallium nitride crystal; the material for forming the anti-diffusion layer includes nitrogen aluminum; the material for forming the current blocking layer includes p-type gallium nitride; the material for forming the channel layer includes unintentionally doped gallium nitride crystal; the material for forming the passivation layer includes silicon dioxide, One or more of silicon nitride; the material for forming the source electrode and the drain electrode includes one or more of titanium, aluminum, nickel, gold, and tantalum; the material for forming the gate electrode includes nickel , one or more of gold, palladium and platinum. Thereby, the use performance of the vertical type high electron mobility field effect transistor device can be further improved.

In another aspect of the present invention, the present invention provides a method for fabricating any one of the foregoing vertical high electron mobility field effect transistors. According to an embodiment of the present invention, the method includes: providing a substrate; forming a current blocking layer on one side of the substrate, the current blocking layer having conductive vias therein; and making the current blocking layer away from the substrate A channel layer is formed on one side of the channel layer; a barrier layer is formed on the side of the channel layer away from the current blocking layer, and a first two-dimensional layer is formed at the interface where the barrier layer and the channel layer are in contact. electron gas, the first two-dimensional electron gas is formed on one side of the channel layer, a groove is formed in the barrier layer, and the distance between the bottom of the groove and the channel layer is not greater than 5 nm; a passivation layer is formed on the side of the barrier layer away from the channel layer, the passivation layer covers the sidewall of the barrier layer facing the inside of the groove, and the passivation layer does not covering the bottom of the groove; a semiconductor layer is formed in the groove, a second two-dimensional electron gas is formed at the interface of the semiconductor layer and the channel layer, and the second two-dimensional electron gas is formed at one side of the semiconductor layer. Therefore, in this method, the conductive channel formed by the first two-dimensional electron gas passing through the conductive through hole can be blocked by the passivation layer and the second two-dimensional electron gas, and the vertical vertical electron gas with normally-off characteristics can be easily prepared. The vertical high electron mobility field effect transistor prepared by the method has better performance, higher breakdown voltage, better withstand voltage performance, higher reliability and stability, and , using this method to prepare a vertical high electron mobility field effect transistor also has at least one of the following advantages: (1) The channel layer of the two-dimensional electron gas can be completely blocked without using a doping activation process, and it is beneficial to Improve the threshold voltage of the device; (2) The precision requirements of the etching groove are low, which can reduce the difficulty of the process; (3) The two-dimensional electron gas in the conductive channel can be depleted without using an ion implantation process to achieve shutdown, The damage to the barrier layer caused by ion implantation can be avoided; (4) the normally-off characteristic of the device can be realized on a single chip without adopting the cascade mode, which can reduce the cost and avoid the introduction of additional parasitic parameters.

According to an embodiment of the present invention, forming the barrier layer further includes: growing an AlmGa _{(1-m) N} crystal material on a side of the channel layer away from the current blocking layer, wherein 0.15≤m≤ 0.80 to form a barrier layer preform; set a first mask on a part of the surface of the barrier layer preform on the side away from the channel layer; for the potential barrier not covered by the first mask The barrier layer preform is subjected to a first dry etching process to form the groove, wherein the difference between the etching depth of the first dry etching process and the thickness of the barrier layer preform is not greater than 5nm ; Remove the first mask to form the barrier layer. Therefore, the barrier layer can be easily formed, which is favorable for preparing a vertical type high electron mobility field effect transistor device with better performance.

According to an embodiment of the present invention, forming the passivation layer further includes: depositing a passivation layer material on a side of the barrier layer away from the channel layer, so as to form a passivation layer preform; A second mask is arranged on the surface of the layer preform, and the second mask covers the area except the bottom of the groove; the passivation layer preform not covered by the second mask is subjected to the first mask Two dry etching processes are performed to form the passivation layer, the passivation layer covering the surface of the barrier layer on the side away from the channel layer and covering the groove facing the barrier layer inner sidewalls; removing the second mask. Therefore, the passivation layer can be easily generated, and the use performance of the prepared vertical high electron mobility field effect transistor device can be further improved.

According to an embodiment of the present invention, before forming the current blocking layer, the method further includes: forming a buffer layer on one side of the substrate, and a material for forming the buffer layer includes: n-type gallium nitride crystal, non- One or more of intentionally doped gallium nitride crystals; forming the current blocking layer further comprises: implanting Mg ²⁺ , At least one of Al ³⁺ , and through an annealing process, a current blocking layer is formed on the side of the buffer layer away from the substrate, and the current blocking layer has conductive through holes without ions implanted, forming all the The material of the current blocking layer includes p-type gallium nitride. Therefore, the current blocking layer can be easily formed in the buffer layer, and the performance of the vertical high electron mobility field effect transistor device can be further improved.

According to an embodiment of the present invention, before forming the current blocking layer, the method further includes: forming a buffer layer on one side of the substrate, and a material for forming the buffer layer includes: n-type gallium nitride crystal, non- one or more of intentionally doped gallium nitride crystals; forming the current blocking layer further comprises: growing a p-type gallium nitride layer in situ on a side of the buffer layer away from the substrate, and passing In the dry etching process, the conductive through hole is formed in the p-type gallium nitride layer, and the current blocking layer is formed. Therefore, the current blocking layer can be easily formed on the side of the buffer layer, thereby further improving the performance of the vertical type high electron mobility field effect transistor device.

According to an embodiment of the present invention, before forming the current blocking layer, the method further includes: forming a buffer layer on one side of the substrate, and a material for forming the buffer layer includes: n-type gallium nitride crystal, non- One or more of intentionally doped gallium nitride crystals; dry etching is performed on part of the buffer layer, so as to form the etched first and second recesses, and The etched conductive via, the conductive via is located between the first recessed portion and the second recessed portion; secondary epitaxial growth is performed in the first recessed portion and the second recessed portion p-type gallium nitride layer so as to form the current blocking layer with the conductive via. Therefore, the current blocking layer can be easily formed in the buffer layer, and the performance of the vertical high electron mobility field effect transistor device can be further improved.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of embodiments taken in conjunction with the accompanying drawings, wherein:

FIG. 1 shows a schematic structural diagram of a vertical high electron mobility field effect transistor according to an embodiment of the present invention;

FIG. 2 shows a schematic structural diagram of a vertical high electron mobility field effect transistor according to another embodiment of the present invention;

3 shows a flow chart of a method for fabricating a vertical high electron mobility field effect transistor according to an embodiment of the present invention;

FIG. 4 shows a flowchart of a method for fabricating a vertical high electron mobility field effect transistor according to another embodiment of the present invention;

5 shows a flow chart of a method for fabricating a vertical high electron mobility field effect transistor according to yet another embodiment of the present invention;

6 shows a flowchart of a method for fabricating a vertical high electron mobility field effect transistor according to yet another embodiment of the present invention;

7 shows a flowchart of a method for fabricating a vertical high electron mobility field effect transistor according to yet another embodiment of the present invention;

FIG. 8 shows a flowchart of a method for fabricating a vertical high electron mobility field effect transistor according to yet another embodiment of the present invention; and

FIG. 9 shows a flowchart of a method for fabricating a vertical high electron mobility field effect transistor according to yet another embodiment of the present invention.

Description of reference numbers:

100: substrate; 110: nucleation layer; 120: buffer layer; 121: first recess; 122: second recess; 200: current blocking layer; 201: conductive via; 210: anti-diffusion layer; 222: p-type gallium nitride layer; 300: channel layer; 310: first two-dimensional electron gas; 320: second two-dimensional electron gas; 400: barrier layer; 401: groove; 500: passivation layer; 600: semiconductor layer; 700: gate electrode; 800: source electrode; 900: drain electrode; 1000: vertical type high electron mobility field effect transistor.

Detailed ways

The following describes in detail the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary, only used to explain the present invention, and should not be construed as a limitation of the present invention.

In one aspect of the present invention, the present invention provides a vertical type high electron mobility field effect transistor. According to an embodiment of the present invention, referring to FIG. 1 , the vertical high electron mobility field effect transistor 1000 may include: a substrate 100 , a current blocking layer 200 , a channel layer 300 , a barrier layer 400 , a passivation layer 500 and a semiconductor Layer 600. The current blocking layer 200 is provided on one side of the substrate 100, and the current blocking layer 200 has conductive vias 201; the channel layer 300 is provided on the side of the current blocking layer 200 away from the substrate 100; the potential barrier layer 400 is provided on the side of the current blocking layer 200 away from the substrate 100 On the side of the channel layer 300 away from the current blocking layer 200 , a first two-dimensional electron gas 310 is formed at the interface between the barrier layer 400 and the channel layer 300 , and the first two-dimensional electron gas 310 is formed on the channel layer 300 On one side, the barrier layer 400 has a groove (not marked in the figure), and the distance between the bottom of the groove and the channel layer 300 is not greater than 5 nm, that is, the depth f of the groove and the thickness d of the barrier layer 300 The difference is not more than 5nm (for example, as shown in FIG. 1, the distance between the bottom of the groove and the channel layer 300 is 0, that is, the depth f of the groove and the thickness d of the barrier layer 400 are equal); The passivation layer 500 is disposed on the side of the barrier layer 400 away from the channel layer 300, and the passivation layer 500 covers the sidewall of the barrier layer 400 facing the inside of the groove, and the passivation layer 500 does not cover the bottom of the groove; the semiconductor layer The 600 is disposed in the groove, a second two-dimensional electron gas 320 is formed at the interface between the semiconductor layer 600 and the channel layer 300 , and the second two-dimensional electron gas 320 is formed on one side of the semiconductor layer 600 . Therefore, the conductive channel formed by the first two-dimensional electron gas 310 through the conductive via 201 can be blocked by the passivation layer 500 and the second two-dimensional electron gas 320, and the vertical high electron mobility can be easily realized The normally-off characteristics of the field effect transistor 1000 device, the voltage withstand performance of the vertical high electron mobility field effect transistor 1000 device is good, the use performance of the vertical high electron mobility field effect transistor 1000 device is good, and the vertical The high electron mobility field effect transistor 1000 device also has at least one of the following advantages: (1) The channel layer of the two-dimensional electron gas can be completely blocked without using a doping activation process, and it is beneficial to improve the threshold value of the device (2) The precision requirement of the etching groove is low, which can reduce the difficulty of the process; (3) The two-dimensional electron gas in the conductive channel can be depleted without using the ion implantation process, and the shutdown can be realized, which can avoid the ion implantation. damage to the barrier layer; (4) no need to use the cascade mode, the normally-off characteristic of the device can be realized on a single chip, the cost can be reduced, and the introduction of additional parasitic parameters can be avoided.

According to the embodiment of the present invention, the materials of the barrier layer 400 , the channel layer 300 and the semiconductor layer 600 are not particularly limited, as long as the forbidden band width of the barrier layer 400 is greater than that of the channel layer 300 , the The forbidden band width may be smaller than the forbidden band width of the channel layer 300 . Therefore, a heterojunction structure can be formed between the barrier layer 400 and the channel layer 300 , the first two-dimensional electron gas 310 can be generated at the interface of the heterojunction, and the first two-dimensional electron gas 310 can be formed close to the channel layer. 300 side, a heterojunction structure can be formed between the semiconductor layer 600 and the channel layer 300 , a second two-dimensional electron gas 320 can be generated at the interface of the heterojunction, and the second two-dimensional electron gas 320 can be formed close to the semiconductor layer 600 On one side, the normally-off characteristics of the vertical high electron mobility field effect transistor device 1000 can be better achieved, and the vertical high electron mobility field effect transistor device 1000 has better withstand voltage performance, high reliability and stability, Better performance.

According to the embodiment of the present invention, the material for forming the substrate 100 is not particularly limited, and those skilled in the art can select it according to the actual situation. For example, according to embodiments of the present invention, the material forming the substrate 100 may include gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium , one or more of silicon. Therefore, the substrate 100 formed of this material can have better performance in use.

According to the embodiment of the present invention, the material for forming the current blocking layer 200 is not particularly limited, and those skilled in the art can select it as required. For example, the material forming the current blocking layer 200 may include p-type gallium nitride. Therefore, when the current blocking layer 200 is formed of the material, the current leakage of the vertical high electron mobility field effect transistor 1000 can be better suppressed, and the performance of the vertical high electron mobility field effect transistor 1000 can be improved. According to an embodiment of the present invention, the thickness of the current blocking layer 200 may be h, specifically, 10nm≤h<1000nm, for example, may be 20nm, may be 50nm, may be 100nm, may be 200nm, may be 300nm, may be 500nm, may be 600nm, may be 700nm, may be 800nm, may be 900nm, etc. Therefore, when the thickness of the current blocking layer 200 is within the above range, the current leakage of the vertical high electron mobility field effect transistor 1000 can be further suppressed, and the performance of the vertical high electron mobility field effect transistor 1000 can be improved.

Specifically, the material for forming the channel layer 300 is not particularly limited, and can be selected by those skilled in the art as required. For example, the material forming the channel layer 300 may include unintentionally doped gallium nitride crystals. Therefore, when the channel layer 300 is formed of the material, the withstand voltage performance of the vertical high electron mobility field effect transistor 1000 can be improved, and the device can be operated at a higher temperature, and the channel formed by the material can be improved. A heterojunction structure can be formed between the layer 300 and the subsequently formed barrier layer 400, and a two-dimensional electron gas with higher electron concentration and electron mobility can be generated at the interface of the heterojunction, and the on-resistance is low. The use performance of the vertical type high electron mobility field effect transistor 1000 can be further improved.

According to an embodiment of the present invention, referring to FIG. 2 , the vertical high electron mobility field effect transistor 1000 may further include: a nucleation layer 110 , a buffer layer 120 and an anti-diffusion layer 210 , wherein the nucleation layer 110 is disposed on the substrate 100, the buffer layer 120 is disposed on the side of the nucleation layer 110 away from the substrate 100, the current blocking layer 200 is formed in the buffer layer 120, and the anti-diffusion layer 210 is disposed on the side of the buffer layer 120 away from the nucleation layer 110 , the channel layer 300 is disposed on the side of the anti-diffusion layer 210 away from the buffer layer 120 . Therefore, the nucleation layer 110 can match the material of the substrate 100 with the buffer layer 120, and the anti-diffusion layer 210 can better prevent the ions in the current blocking layer from diffusing into the channel layer in the subsequent process, thereby reducing the channel layer. Mobility of two-dimensional electron gas. According to an embodiment of the present invention, the material for forming the buffer layer 120 may include one or more of an n-type gallium nitride crystal and an unintentionally doped gallium nitride crystal. Therefore, the buffer layer 120 formed of the material can suppress the current leakage of the vertical high electron mobility field effect transistor 1000 and improve the performance of the vertical high electron mobility field effect transistor 1000 device. Specifically, the material for forming the anti-diffusion layer 210 may include aluminum nitride. Therefore, the anti-diffusion layer 210 formed of this material can better prevent ions in the current blocking layer from diffusing into the channel layer in subsequent processes, thereby reducing the mobility of the two-dimensional electron gas in the channel layer.

According to an embodiment of the present invention, the forbidden band width of the barrier layer 400 may be greater than that of the channel layer 300 . Therefore, a heterojunction structure can be formed between the barrier layer 400 and the channel layer 300 , the first two-dimensional electron gas 310 with a higher concentration can be formed at the interface of the heterojunction, and the first two-dimensional electron gas 310 can be Forming on the side close to the channel layer 300 with a smaller forbidden band width can further improve the performance of the vertical high electron mobility field effect transistor 1000 .

According to the embodiment of the present invention, the material for forming the barrier layer 400 is not particularly limited, and those skilled in the art can select it as required. Specifically, the material for forming the barrier layer 400 may include AlmGa _{(1-m) N} crystal, wherein 0.15≤m≤0.80, specifically, m may be 0.2, may be 0.3, may be 0.4, may be 0.5 , can be 0.6, can be 0.7, etc. Therefore, a heterojunction structure can be formed between the barrier layer 400 and the channel layer 300 formed of this material, and a first two-dimensional electron gas 310 with a relatively high concentration can be formed at the interface of the heterojunction, and the first two-dimensional electron gas 310 can be formed at the interface of the heterojunction. The dimensional electron gas 310 can be formed close to the side of the channel layer 300 with a smaller forbidden band width, which can further improve the performance of the vertical high electron mobility field effect transistor 1000 . Specifically, the thickness of the barrier layer 400 may be not less than 30 nm, for example, may be 35 nm, may be 40 nm, may be 45 nm, or the like. Therefore, when the thickness of the barrier layer 400 is in the above range, it can have better performance, and can further improve the performance of the vertical high electron mobility field effect transistor 1000 .

According to the embodiment of the present invention, the material for forming the passivation layer 500 is not particularly limited, and those skilled in the art can select it as required. Specifically, the material for forming the passivation layer 500 may include one or more of silicon dioxide and silicon nitride. Therefore, the passivation layer 500 formed of this material can improve the surface state of the device, and can isolate the barrier layer 400 and the semiconductor layer 600, prevent the barrier layer 400 and the semiconductor layer 600 from interacting with each other, and form a two-dimensional electron gas, In addition, the passivation layer 500 can block the first two-dimensional electron gas 310 flowing through the conductive via 201 together with the second two-dimensional electron gas 320 .

According to an embodiment of the present invention, the forbidden band width of the semiconductor layer 600 may be smaller than that of the channel layer 300 . Thus, a heterojunction structure can be formed between the semiconductor layer 600 and the channel layer 300 , the second two-dimensional electron gas 320 with a higher concentration can be formed at the interface of the heterojunction, and the second two-dimensional electron gas 320 can be formed On the side close to the semiconductor layer 600 with the smaller forbidden band width, the second two-dimensional electron gas 320 can induce polarization on the side of the channel layer 300 corresponding to the semiconductor layer 600 (ie, the area under the groove). holes, so that the first two-dimensional electron gas 310 in the area under the groove can be depleted, the first two-dimensional electron gas 310 can be further blocked from flowing through the conductive channel formed by the conductive through hole 201, and the first two-dimensional electron gas 310 can be further blocked. The normally-off characteristic of the vertical high electron mobility field effect transistor 1000 can be easily realized, and the performance of the vertical high electron mobility field effect transistor 1000 can be further improved.

According to the embodiment of the present invention, the material for forming the semiconductor layer 600 is not particularly limited, and those skilled in the art can select it as required. Specifically, the material for forming the semiconductor layer 600 may include InnGa _{(1-n) N} crystal, wherein 0<n≤0.45, specifically, n may be 0.1, may be 0.2, may be 0.3, may be 0.4, etc. . Therefore, the semiconductor layer 600 formed of this material can further increase the concentration of the second two-dimensional electron gas 320 at the interface of the heterojunction, improve the electron mobility, and further improve the use of the vertical high electron mobility field effect transistor 1000 device performance. Specifically, the thickness of the semiconductor layer 600 may not be less than 30 nm, for example, may be 35 nm, may be 40 nm, may be 45 nm, or the like. Therefore, when the thickness of the semiconductor layer 600 is within the above range, the performance of the vertical high electron mobility field effect transistor 1000 can be further improved.

According to an embodiment of the present invention, referring to FIG. 2 , the vertical high electron mobility field effect transistor 1000 may further include: a gate electrode 700 , a source electrode 800 and a drain electrode 900 , wherein the gate electrode 700 is disposed far from the semiconductor layer 600 . On one side of the channel layer 300, the orthographic projection of the groove on the substrate 100 is not greater than the orthographic projection of the gate 700 on the substrate 100, and the orthographic projection of the gate 700 on the substrate 100 is not smaller than the conductive via (Fig. It is not marked in FIG. 1, you can refer to the orthographic projection of the conductive via 201) on the substrate 100 in FIG. 400 is in contact, and the drain 900 is disposed on the side of the substrate 100 away from the nucleation layer 110 . Therefore, the gate electrode 700 can form a good Schottky contact with the semiconductor layer 600, the source electrode 800 can directly contact the barrier layer 400 to form a good ohmic contact, and the drain electrode 900 is fabricated under the substrate 100, so that the The entire surface of the device is in a low electric field state, which can effectively avoid the concentration of the electric field at the edge of the gate 700. The voltage withstand performance of the device is not limited by the lateral size. The device is mainly subjected to the vertical distance between the gate 700 and the drain 900. Withstanding voltage, the lateral size of the device can be designed to be smaller, the area of the device can be effectively saved, and the performance of the vertical high electron mobility field effect transistor 1000 device can be further improved. Specifically, the material for forming the gate 700 may include one or more of nickel, gold, palladium, and platinum. Therefore, the gate electrode 700 formed of the material can form a good Schottky contact with the semiconductor layer 600, which can further improve the performance of the vertical high electron mobility field effect transistor 1000 device. Specifically, the material for forming the source electrode 800 and the drain electrode 900 may include one or more of titanium, aluminum, nickel, gold, and tantalum. Therefore, the source electrode 800 formed of this material can directly contact the barrier layer 400 to form a good ohmic contact, and the drain electrode 900 formed of this material has good performance, which can further improve the vertical high electron mobility field effect transistor 1000 device performance.

To sum up, according to the vertical high electron mobility field effect transistor 1000 according to the embodiment of the present invention, the conductive channel formed by the first two-dimensional electron gas 310 through the conductive via 201 can be blocked by the passivation layer 500 and the second two-dimensional electron gas 310 The electron gas 320 is blocked, which can easily realize the normally-off characteristics of the vertical high electron mobility field effect transistor 1000 device. The vertical high electron mobility field effect transistor 1000 device has better performance and higher breakdown voltage. , the withstand voltage performance is good, reliability and stability are high, and when the vertical high electron mobility field effect transistor 1000 is working, when an external voltage is applied to the gate 700, the second two-dimensional electron gas 320 can be When depleted, the induced polarization holes generated on the side of the channel layer 300 corresponding to the gate 700 also disappear, and the first two-dimensional electron gas 310 can be re-conducted through the conductive channel formed by the conductive via 201 . The use performance of the vertical high electron mobility field effect transistor 1000 is good.

In another aspect of the present invention, the present invention provides a method for fabricating the aforementioned vertical high electron mobility field effect transistor. According to an embodiment of the present invention, with reference to FIG. 3 and FIG. 4 , the method includes:

S100: Provide substrate

In this step, a substrate is provided. According to an embodiment of the present invention, referring to (a) of FIG. 4 , the material for forming the substrate 100 is not particularly limited, for example, the material for forming the substrate 100 may include gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum One or more of indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, and silicon. Therefore, the substrate 100 formed of the material can have better performance, and can improve the performance of the vertical high electron mobility field effect transistor.

According to an embodiment of the present invention, in order to further improve the performance of the prepared high electron mobility field effect transistor, after the substrate 100 is provided, the method may further include: disposing a nucleation layer ( Not shown in the figure), and a buffer layer (not shown in the figure) is provided on the side of the nucleation layer away from the substrate 100, and an anti-diffusion layer (not shown in the figure) is formed on the side of the buffer layer away from the nucleation layer ). Thereby, the use performance of the vertical type high electron mobility field effect transistor device can be further improved.

S200: A current blocking layer is formed on one side of the substrate, and the current blocking layer has conductive vias

In this step, a current blocking layer is formed on one side of the substrate, and the current blocking layer has conductive through holes. According to an embodiment of the present invention, referring to (b) in FIG. 4 , a current blocking layer 200 is formed on one side of the substrate 100 , and the current blocking layer 200 has conductive vias 201 therein. Specifically, the material for forming the current blocking layer 200 is not particularly limited, for example, the material for forming the current blocking layer 200 may include p-type gallium nitride. Therefore, when the current blocking layer 200 is formed of the material, the current leakage of the vertical high electron mobility field effect transistor can be better suppressed, and the performance of the vertical high electron mobility field effect transistor device can be further improved. According to an embodiment of the present invention, the thickness of the current blocking layer 200 may be h, specifically, 10nm≤h<1000nm, for example, may be 20nm, may be 50nm, may be 100nm, may be 200nm, may be 300nm, may be 500nm, may be 600nm, may be 700nm, may be 800nm, may be 900nm, etc. Therefore, when the thickness of the current blocking layer 200 is within the above range, the current leakage of the vertical high electron mobility field effect transistor can be further suppressed, and the performance of the vertical high electron mobility field effect transistor device can be improved. Specifically, the current blocking layer 200 may be formed in the buffer layer. Thus, the current blocking layer 200 can be formed relatively easily.

According to an embodiment of the present invention, referring to FIG. 7 , before forming the current blocking layer 200 , the method may further include: forming a buffer layer 120 on one side of the substrate 100 , and the material for forming the buffer layer 120 may include: n-type gallium nitride One or more of crystals, unintentionally doped gallium nitride crystals. Therefore, the buffer layer 120 formed of the material can suppress the current leakage of the vertical high electron mobility field effect transistor, and improve the performance of the vertical high electron mobility field effect transistor device. Specifically, forming the current blocking layer 200 may further include: implanting at least one of Mg ²⁺ and Al ³⁺ on a part of the surface of the buffer layer 120 on the side away from the substrate 100 by an ion implantation process, and performing an annealing process to A current blocking layer 200 is formed on the side of the buffer layer away from the substrate 100 . The current blocking layer 200 has conductive vias 201 without ions implanted therein. The material for forming the current blocking layer 200 may include p-type gallium nitride. Therefore, the current blocking layer 200 can be easily formed in the buffer layer 120, thereby further improving the performance of the vertical high electron mobility field effect transistor device.

Specifically, referring to FIG. 8 , after forming the buffer layer 120 on one side of the substrate 100 , forming the current blocking layer 200 may further include: growing a p-type gallium nitride layer in situ on the side of the buffer layer 120 away from the substrate 100 222, and through a dry etching process, a conductive via 201 is formed in the p-type gallium nitride layer 222, and a current blocking layer 200 is formed. Therefore, the current blocking layer 200 can be easily formed on the side of the buffer layer 120, thereby further improving the performance of the vertical high electron mobility field effect transistor device.

Specifically, referring to FIG. 9 , after forming the buffer layer 120 on one side of the substrate 100 , forming the current blocking layer 200 may further include: performing dry etching on a part of the buffer layer 120 to form an etched The first recessed portion 121 and the second recessed portion 122, and the unetched conductive via 201, the conductive via 201 is located between the first recessed portion 121 and the second recessed portion 122; A p-type gallium nitride layer is secondary epitaxially grown in the two recesses 122 to form the current blocking layer 200 having the conductive via 201 . Therefore, the current blocking layer 200 can be easily formed in the buffer layer 120, thereby further improving the performance of the vertical high electron mobility field effect transistor device.

S300 : forming a channel layer on the side of the current blocking layer away from the substrate

In this step, a channel layer is formed on the side of the current blocking layer away from the substrate. According to an embodiment of the present invention, referring to (c) of FIG. 4 , a channel layer 300 is formed on a side of the current blocking layer 200 away from the substrate 100 . Specifically, the material for forming the channel layer 300 is not particularly limited, for example, the material for forming the channel layer 300 may include unintentionally doped gallium nitride crystal. Therefore, when the channel layer 300 is formed of this material, the withstand voltage performance of the vertical high electron mobility field effect transistor device can be improved, and the device can be operated at a higher temperature, and the channel layer 300 formed of this material can be A heterojunction structure can be formed between the subsequently formed barrier layer, and a two-dimensional electron gas with high electron concentration and electron mobility can be generated at the heterojunction interface, and the on-resistance is low, which can be further improved Performance of Vertical High Electron Mobility Field Effect Transistor Devices.

S400 : forming a barrier layer on the side of the channel layer away from the current blocking layer, and forming a groove in the barrier layer

In this step, a barrier layer is formed on the side of the channel layer away from the current blocking layer, and a groove is formed in the barrier layer. According to an embodiment of the present invention, referring to (d) of FIG. 4 , a barrier layer 400 is formed on a side of the channel layer 300 away from the current blocking layer 200 , and a groove 401 is formed in the barrier layer 400 . Specifically, a barrier layer 400 is formed on the side of the channel layer 300 away from the current blocking layer 200 , and a first two-dimensional electron gas 310 is formed at the interface where the barrier layer 400 and the channel layer 300 are in contact. The electron gas 310 is formed on the side of the channel layer 300, and a groove 401 is formed in the barrier layer 400. The distance between the bottom of the groove 401 and the channel layer 300 is not greater than 5 nm, that is, the depth f of the groove 401 and the potential The difference between the thicknesses d of the barrier layers 300 is not more than 5 nm. Therefore, the process of forming the groove 401 is also relatively simple, and the performance of the vertical high electron mobility field effect transistor can be further improved. Specifically, the distance between the bottom of the groove 401 and the channel layer 300 is not greater than 5 nm, such as 3 nm, 1 nm, or 0, that is, the depth f of the groove 401 and the thickness of the barrier layer 400 are equal, Therefore, when the semiconductor layer is subsequently formed in the groove 401, the second two-dimensional electron gas can be preferably formed between the semiconductor layer and the channel layer 300, and the etching process of the groove 401 is relatively simple, and the etching process is relatively simple. The accuracy requirements are low, and it is easy to operate.

Specifically, the forbidden band width of the barrier layer 400 may be greater than the forbidden band width of the channel layer 300 , so that the first two-dimensional electron gas 310 can be preferably formed close to the channel layer 300 with the smaller forbidden band width. side. Specifically, the material for forming the barrier layer 400 may include AlmGa _{(1-m) N} crystal, wherein 0.15≤m≤0.80. Therefore, the barrier layer 400 formed of this material can further improve the performance of the vertical type high electron mobility field effect transistor. Specifically, the thickness d of the barrier layer 400 may be not less than 30 nm, for example, may be 35 nm, may be 40 nm, may be 45 nm, or the like. Therefore, when the thickness d of the barrier layer 400 is in the above range, the performance of the vertical type high electron mobility field effect transistor device can be further improved. Specifically, referring to FIG. 5 , forming the barrier layer may further include:

S401: forming a barrier layer preform

In this step, AlmGa _{(1-m) N} crystal material may be grown on the side of the channel layer away from the current blocking layer, wherein 0.15≤m≤0.80, so as to form a barrier layer preform.

S402: Set the first mask

In this step, a first mask may be provided on a part of the surface of the barrier layer preform on the side away from the channel layer. Specifically, the material for forming the first mask may include silicon dioxide or silicon nitride.

S403 : perform a first dry etching process on the barrier layer preform not covered by the first mask to form a groove

In this step, a first dry etching process may be performed on the barrier layer preform not covered by the first mask, for example, inductively coupled plasma etching (ICP), reactive ion etching (RIE), Electron cyclotron resonance plasma etching (ECR), or ion beam etching (IBE) and other methods are used to etch the barrier layer preform not covered by the first mask, so as to form grooves, wherein the first dry method The difference between the etching depth of the etching process and the thickness of the barrier layer preform is not more than 5 nm. As a result, the etching precision requirements when forming the grooves are low, the process difficulty can be reduced, and the vertical type high electron mobility field effect transistor device with better performance can be better prepared.

S404: Remove the first mask to form a barrier layer

In this step, the first mask is removed to form a barrier layer having grooves. Therefore, the barrier layer can be easily formed, which is favorable for preparing a vertical type high electron mobility field effect transistor device with better performance.

According to an embodiment of the present invention, after forming the barrier layer, the method may further include: preparing a source electrode on a surface of the barrier layer on the side away from the channel layer. Specifically, at least one of electron beam evaporation technology or magnetron sputtering technology can be used to deposit a metal material in the region corresponding to the source electrode to form the source electrode, and then anneal the source electrode to form the source electrode ohmic contact. Specifically, the material for forming the source electrode may include one or more of titanium, aluminum, nickel, gold, and tantalum. Thus, the use performance of the prepared vertical high electron mobility field effect transistor device can be further improved.

According to an embodiment of the present invention, after forming the barrier layer, the method may further include: preparing a drain electrode on the surface of the substrate on the side away from the nucleation layer. Specifically, at least one of electron beam evaporation technology or magnetron sputtering technology can be used to deposit a metal material in the region corresponding to the drain to form the drain, and then anneal the drain to form the ohmic contact of the drain. Specifically, the material for forming the drain may include one or more of titanium, aluminum, nickel, gold, and tantalum. Thus, the use performance of the prepared vertical high electron mobility field effect transistor device can be further improved.

S500: forming a passivation layer on the side of the barrier layer away from the channel layer

In this step, a passivation layer is formed on the side of the barrier layer away from the channel layer. According to an embodiment of the present invention, referring to (e) in FIG. 4 , a passivation layer 500 is formed on the side of the barrier layer 400 away from the channel layer 300 , and the passivation layer 500 covers the interior of the barrier layer 400 toward the groove 401 sidewalls, the passivation layer 500 does not cover the bottom of the groove 401 . Therefore, the passivation layer 500 can better improve the surface state of the device, and can isolate the barrier layer 400 from the semiconductor layer subsequently formed in the groove 401 , preventing the barrier layer 400 and the subsequent semiconductor layer formed in the groove 401 The semiconductor layers interact with each other to form a two-dimensional electron gas, causing problems such as leakage current, and the passivation layer 500 and the second two-dimensional electron gas 320 can block the first two-dimensional electron gas 310 together. Specifically, the material for forming the passivation layer 500 may include one or more of silicon dioxide and silicon nitride. Therefore, the passivation layer 500 formed of this material can further improve the surface state of the device, isolate the barrier layer 400 and the semiconductor layer subsequently formed in the groove 401, and improve the prepared vertical high electron mobility field effect transistor device. Use performance. Specifically, referring to FIG. 6 , forming the passivation layer may further include:

S501: forming a passivation layer preform

In this step, a passivation layer material may be deposited on a side of the barrier layer away from the channel layer, so as to form a passivation layer preform. Specifically, a metal organic compound chemical vapor deposition method (MOCVD) or a plasma enhanced chemical vapor deposition method (PECVD) can be used to grow a layer on the side of the barrier layer away from the channel layer (that is, in the region between the source electrodes) passivation layer. Therefore, the passivation layer can be easily generated, and the use performance of the prepared vertical high electron mobility field effect transistor device can be further improved.

S502: Set a second mask, the second mask covers the area except the bottom of the groove

In this step, a second mask may be provided on the surface of the passivation layer preform, and the second mask covers the area except the bottom of the groove. Specifically, the material for forming the second mask may include silicon dioxide or silicon nitride.

S503: Perform a second dry etching process on the passivation layer preform not covered by the second mask to form a passivation layer

In this step, a second dry etching process is performed on the passivation layer preform not covered by the second mask to form a passivation layer. Specifically, a second dry etching process may be performed on the passivation layer preform not covered by the second mask, for example, inductively coupled plasma etching (ICP), reactive ion etching (RIE), electron The passivation layer preform not covered by the second mask is etched by methods such as cyclotron resonance plasma etching (ECR), or ion beam etching (IBE), so as to form a passivation layer that covers the barrier The layer faces away from the surface of the side of the channel layer and covers the sidewall of the barrier layer facing the inside of the groove. Therefore, the passivation layer can be formed relatively simply, and the use performance of the prepared vertical high electron mobility field effect transistor device can be further improved.

S504: Remove the second mask

In this step, the second mask is removed. As a result, the passivation layer can be easily formed, and the passivation layer can better cover the surface of the barrier layer on the side away from the channel layer, and cover the sidewall of the barrier layer facing the inside of the groove, which can better improve the The surface state of the device, and can isolate the barrier layer from the semiconductor layer formed in the groove subsequently, prevent the barrier layer and the semiconductor layer formed in the groove from interacting with each other, form a two-dimensional electron gas, and generate leakage current In addition, the passivation layer can block the first two-dimensional electron gas together with the second two-dimensional electron gas, which can further improve the performance of the prepared vertical high electron mobility field effect transistor device.

S600: Forming a semiconductor layer in the groove

In this step, a semiconductor layer is formed in the groove. According to an embodiment of the present invention, referring to (f) in FIG. 4 , a semiconductor layer 600 is formed in the groove 401 , and a second two-dimensional electron gas 320 is formed at the interface between the semiconductor layer 600 and the channel layer 300 . The electron gas 320 is formed on the side of the semiconductor layer 600 . In this way, the second two-dimensional electron gas 320 can generate polarization-induced holes on one side of the channel layer 300 corresponding to the semiconductor layer 600 (ie, the region under the groove 401 ). The first two-dimensional electron gas 310 in the area below 401 is depleted, which can further block the conductive channel formed by the first two-dimensional electron gas 310 flowing through the conductive through hole, and can easily prepare a vertical type with normally-off characteristics. The high electron mobility field effect transistor device can further improve the performance of the vertical type high electron mobility field effect transistor device. Specifically, the semiconductor layer 600 can be formed by depositing a semiconductor material in the groove 401 by using a metal organic compound chemical vapor deposition method (MOCVD). Thereby, the semiconductor layer 600 can be formed relatively easily. Specifically, the material for forming the semiconductor layer 600 may include InnGa _{(1-n) N} crystal, where 0<n≦0.45. Therefore, the forbidden band width of the semiconductor layer 600 formed of this material can be smaller than the forbidden band width of the channel layer 300, and the heterojunction interface between the semiconductor layer 600 and the channel layer 300 can form a higher concentration and higher electron mobility. The second two-dimensional electron gas 320 is higher, and the second two-dimensional electron gas 320 is formed on the side close to the semiconductor layer 600 with the smaller forbidden band width, and the second two-dimensional electron gas 320 can make the electron gas corresponding to the semiconductor layer 600 One side of the channel layer 300 (that is, the region under the groove) generates holes that induce polarization, so that the first two-dimensional electron gas 310 in the region under the groove can be depleted, which can further block the first two-dimensional electron gas 310. A two-dimensional electron gas 310 flows through the conductive channel formed by the conductive through hole, which can easily prepare a vertical high electron mobility field effect transistor device with normally-off characteristics, and can further improve the prepared vertical high electron mobility field. Performance of Effect Transistor Devices. Specifically, the thickness of the semiconductor layer 600 may not be less than 30 nm, for example, may be 35 nm, may be 40 nm, may be 45 nm, or the like. Therefore, when the thickness of the semiconductor layer 600 is in the above range, the performance of the vertical type high electron mobility field effect transistor device can be further improved.

According to an embodiment of the present invention, after the semiconductor layer 600 is formed in the groove 401, the method may further include: using a photolithography process, etching a gate window on the side of the semiconductor layer 600 away from the channel layer 300, and at the gate Grids are prepared in the window. Specifically, an electron beam evaporation technique or a magnetron sputtering technique can be used to deposit a metal material in the gate window to form the gate. Thus, the gate electrode can form Schottky contact with the semiconductor layer 600 . Specifically, the material for forming the gate may include one or more of nickel, gold, palladium, and platinum. Therefore, the gate formed of the material can form a good Schottky contact with the semiconductor layer 600, which can further improve the performance of the prepared vertical high electron mobility field effect transistor device.

To sum up, in this method, a first two-dimensional electron gas is formed at the interface where the barrier layer and the channel layer are in contact, the first two-dimensional electron gas is formed on the side of the channel layer, and the first two-dimensional electron gas is formed in the barrier layer The groove, so that the difference between the depth of the groove and the thickness of the barrier layer is not greater than 5nm, and a passivation layer is formed on the side of the barrier layer far from the channel layer, so that the passivation layer covers the inner side of the barrier layer toward the groove The sidewall of the groove, the passivation layer does not cover the bottom of the groove, and then a semiconductor layer is formed in the groove, and a second two-dimensional electron gas is formed at the interface between the semiconductor layer and the channel layer, and the second two-dimensional electron gas is formed on the semiconductor layer. On the layer side, in this method, the conductive channel formed by the first two-dimensional electron gas passing through the conductive via can be blocked by the passivation layer and the second two-dimensional electron gas, and a vertical type with normally-off characteristics can be easily prepared. The high electron mobility field effect transistor, the vertical type high electron mobility field effect transistor device prepared by the method has better performance, higher breakdown voltage, better withstand voltage performance, and higher reliability and stability.

In the description of this specification, the orientation or positional relationship indicated by the terms "upper", "lower", "bottom", "one side", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention It is not intended that the present invention must be constructed and operated in a particular orientation, and therefore should not be construed as a limitation of the present invention.

In the description of this specification, description with reference to the terms "one embodiment", "another embodiment", etc. means that a particular feature, structure, material or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention . In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine the different embodiments or examples described in this specification, as well as the features of the different embodiments or examples, without conflicting each other.

Although the embodiments of the present invention have been shown and described above, it should be understood that the above-mentioned embodiments are exemplary and should not be construed as limiting the present invention. Embodiments are subject to variations, modifications, substitutions and variations.

Claims (13)

1. A vertical high electron mobility field effect transistor, comprising:

a substrate;

a current blocking layer disposed on one side of the substrate, the current blocking layer having a conductive via therein;

the channel layer is arranged on one side, far away from the substrate, of the current blocking layer;

a barrier layer disposed on a side of the channel layer away from the current blocking layer, a first two-dimensional electron gas being formed at an interface where the barrier layer and the channel layer are in contact, the first two-dimensional electron gas being formed on the side of the channel layer, the barrier layer having a groove therein, a distance between a bottom of the groove and the channel layer being not more than 5 nm;

the passivation layer is arranged on one side, far away from the channel layer, of the barrier layer, covers the side wall, facing the inside of the groove, of the barrier layer, and does not cover the bottom of the groove;

a semiconductor layer disposed in the groove, a second two-dimensional electron gas formed at an interface of the semiconductor layer and the channel layer, the second two-dimensional electron gas being formed at one side of the semiconductor layer.

2. The vertical high electron mobility field effect transistor according to claim 1, wherein the barrier layer has a forbidden bandwidth greater than that of the channel layer, and the semiconductor layer has a forbidden bandwidth less than that of the channel layer.

3. The vertical hemt of claim 1, wherein said barrier layer is formed from a material comprising Al _m Ga _(1-m) And the N crystal, wherein m is more than or equal to 0.15 and less than or equal to 0.80, and the thickness of the barrier layer is not less than 30 nm.

4. The vertical high electron mobility field effect transistor according to claim 1, wherein a material forming the semiconductor layer comprises In _n Ga _(1-n) And N is more than 0 and less than or equal to 0.45, and the thickness of the semiconductor layer is not less than 30 nm.

5. The vertical high electron mobility field effect transistor according to claim 1, wherein the thickness of the current blocking layer is h, and h is 10nm ≦ h < 1000 nm.

6. The vertical high electron mobility field effect transistor of claim 1, further comprising:

a nucleation layer disposed on one side of the substrate;

a buffer layer disposed on a side of the nucleation layer remote from the substrate, the current blocking layer being formed in the buffer layer;

the diffusion preventing layer is arranged on one side of the buffer layer far away from the nucleating layer;

the channel layer is arranged on one side, far away from the buffer layer, of the diffusion-proof layer;

the grid electrode is arranged on one side, away from the channel layer, of the semiconductor layer, the orthographic projection of the groove on the substrate is not larger than that of the grid electrode on the substrate, and the orthographic projection of the grid electrode on the substrate is not smaller than that of the conductive through hole on the substrate;

the source electrode is arranged on one side, far away from the channel layer, of the barrier layer, and the source electrode is in contact with the barrier layer;

a drain disposed on a side of the substrate away from the nucleation layer.

7. The vertical high electron mobility field effect transistor according to claim 6,

the material for forming the substrate comprises one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium and silicon;

the material forming the buffer layer comprises one or more of n-type gallium nitride crystals and unintentionally doped gallium nitride crystals;

the material for forming the diffusion preventing layer comprises aluminum nitride;

the material forming the current blocking layer comprises p-type gallium nitride;

the material forming the channel layer comprises unintentionally doped gallium nitride crystals;

the material for forming the passivation layer comprises one or more of silicon dioxide and silicon nitride;

the material for forming the source electrode and the drain electrode comprises one or more of titanium, aluminum, nickel, gold and tantalum;

the material for forming the grid electrode comprises one or more of nickel, gold, palladium and platinum.

8. A method of manufacturing the vertical high electron mobility field effect transistor of any of claims 1 to 7, comprising:

providing a substrate;

forming a current blocking layer on one side of the substrate, wherein the current blocking layer is provided with a conductive through hole;

forming a channel layer on one side of the current blocking layer far away from the substrate;

forming a barrier layer on one side of the channel layer far away from the current blocking layer, wherein a first two-dimensional electron gas is formed at an interface where the barrier layer and the channel layer are in contact, the first two-dimensional electron gas is formed on one side of the channel layer, a groove is formed in the barrier layer, and the distance between the bottom of the groove and the channel layer is not more than 5 nm;

forming a passivation layer on one side of the barrier layer away from the channel layer, wherein the passivation layer covers the side wall of the barrier layer facing the inner part of the groove, and the passivation layer does not cover the bottom of the groove;

and forming a semiconductor layer in the groove, wherein a second two-dimensional electron gas is formed at an interface of the semiconductor layer and the channel layer, and the second two-dimensional electron gas is formed on one side of the semiconductor layer.

9. The method of claim 8, wherein forming the barrier layer further comprises:

growing Al on the side of the channel layer far away from the current barrier layer _m Ga _(1-m) An N crystal material, wherein 0.15. ltoreq. m.ltoreq.0.80, to form a barrier layer preform;

arranging a first mask on the partial surface of one side of the barrier layer prefabricated body far away from the channel layer;

performing a first dry etching process on the barrier layer preform uncovered by the first mask so as to form the groove, wherein a difference between an etching depth of the first dry etching process and a thickness of the barrier layer preform is not more than 5 nm;

and removing the first mask to form the barrier layer.

10. The method of claim 8, wherein forming the passivation layer further comprises:

depositing a passivation layer material on a side of the barrier layer remote from the channel layer to form a passivation layer preform;

arranging a second mask on the surface of the passivation layer prefabricated body, wherein the second mask covers the region except the bottom of the groove;

performing a second dry etching treatment on the passivation layer prefabricated body which is not covered by the second mask so as to form the passivation layer, wherein the passivation layer covers the surface of the barrier layer on the side far away from the channel layer and covers the side wall of the barrier layer facing the inside of the groove;

and removing the second mask.

11. The method of claim 8, wherein prior to forming the current blocking layer, the method further comprises:

forming a buffer layer on one side of the substrate, the buffer layer being formed of a material including: one or more of an n-type gallium nitride crystal, an unintentionally doped gallium nitride crystal;

forming the current blocking layer further comprises:

implanting Mg into partial surface of the buffer layer far away from the substrate by ion implantation process ²⁺ 、Al ³⁺ And forming a current blocking layer on the side of the buffer layer far away from the substrate through an annealing process, wherein the current blocking layer is provided with a conductive through hole which is not implanted with ions, and the material for forming the current blocking layer comprises p-type gallium nitride.

12. The method of claim 8, wherein prior to forming the current blocking layer, the method further comprises:

forming a buffer layer on one side of the substrate, the buffer layer being formed of a material including: one or more of an n-type gallium nitride crystal, an unintentionally doped gallium nitride crystal;

forming the current blocking layer further comprises:

and growing a p-type gallium nitride layer in situ on one side of the buffer layer, which is far away from the substrate, and forming the conductive through hole in the p-type gallium nitride layer through dry etching treatment to form the current blocking layer.

13. The method of claim 8, wherein prior to forming the current blocking layer, the method further comprises:

forming a buffer layer on one side of the substrate, the buffer layer being formed of a material including: one or more of an n-type gallium nitride crystal, an unintentionally doped gallium nitride crystal;

performing dry etching treatment on a partial region of the buffer layer so as to form a first depressed part and a second depressed part after etching and the conductive through hole which is not etched, wherein the conductive through hole is positioned between the first depressed part and the second depressed part;

epitaxially growing a p-type gallium nitride layer twice in the first and second recesses so as to form the current blocking layer having the conductive via.

Images